diff options
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
-rw-r--r-- | arch/arm/mach-exynos/pm.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e19013051772..f105bd2b6765 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -38,29 +38,29 @@ | |||
38 | #include <mach/pmu.h> | 38 | #include <mach/pmu.h> |
39 | 39 | ||
40 | static struct sleep_save exynos4_set_clksrc[] = { | 40 | static struct sleep_save exynos4_set_clksrc[] = { |
41 | { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, | 41 | { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, |
42 | { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, | 42 | { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, |
43 | { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, | 43 | { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, |
44 | { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, | 44 | { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, |
45 | { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, | 45 | { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, |
46 | { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, | 46 | { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, |
47 | { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, | 47 | { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, |
48 | { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, | 48 | { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, |
49 | { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, | 49 | { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, |
50 | }; | 50 | }; |
51 | 51 | ||
52 | static struct sleep_save exynos4210_set_clksrc[] = { | 52 | static struct sleep_save exynos4210_set_clksrc[] = { |
53 | { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, | 53 | { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, |
54 | }; | 54 | }; |
55 | 55 | ||
56 | static struct sleep_save exynos4_epll_save[] = { | 56 | static struct sleep_save exynos4_epll_save[] = { |
57 | SAVE_ITEM(S5P_EPLL_CON0), | 57 | SAVE_ITEM(EXYNOS4_EPLL_CON0), |
58 | SAVE_ITEM(S5P_EPLL_CON1), | 58 | SAVE_ITEM(EXYNOS4_EPLL_CON1), |
59 | }; | 59 | }; |
60 | 60 | ||
61 | static struct sleep_save exynos4_vpll_save[] = { | 61 | static struct sleep_save exynos4_vpll_save[] = { |
62 | SAVE_ITEM(S5P_VPLL_CON0), | 62 | SAVE_ITEM(EXYNOS4_VPLL_CON0), |
63 | SAVE_ITEM(S5P_VPLL_CON1), | 63 | SAVE_ITEM(EXYNOS4_VPLL_CON1), |
64 | }; | 64 | }; |
65 | 65 | ||
66 | static struct sleep_save exynos4_core_save[] = { | 66 | static struct sleep_save exynos4_core_save[] = { |
@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void) | |||
239 | locktime = (3000 / pll_in_rate) * p_div; | 239 | locktime = (3000 / pll_in_rate) * p_div; |
240 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | 240 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); |
241 | 241 | ||
242 | __raw_writel(lockcnt, S5P_EPLL_LOCK); | 242 | __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); |
243 | 243 | ||
244 | s3c_pm_do_restore_core(exynos4_epll_save, | 244 | s3c_pm_do_restore_core(exynos4_epll_save, |
245 | ARRAY_SIZE(exynos4_epll_save)); | 245 | ARRAY_SIZE(exynos4_epll_save)); |
@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void) | |||
257 | locktime = 750; | 257 | locktime = 750; |
258 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | 258 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); |
259 | 259 | ||
260 | __raw_writel(lockcnt, S5P_VPLL_LOCK); | 260 | __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); |
261 | 261 | ||
262 | s3c_pm_do_restore_core(exynos4_vpll_save, | 262 | s3c_pm_do_restore_core(exynos4_vpll_save, |
263 | ARRAY_SIZE(exynos4_vpll_save)); | 263 | ARRAY_SIZE(exynos4_vpll_save)); |
@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void) | |||
268 | 268 | ||
269 | do { | 269 | do { |
270 | if (epll_wait) { | 270 | if (epll_wait) { |
271 | pll_con = __raw_readl(S5P_EPLL_CON0); | 271 | pll_con = __raw_readl(EXYNOS4_EPLL_CON0); |
272 | if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) | 272 | if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) |
273 | epll_wait = 0; | 273 | epll_wait = 0; |
274 | } | 274 | } |
275 | 275 | ||
276 | if (vpll_wait) { | 276 | if (vpll_wait) { |
277 | pll_con = __raw_readl(S5P_VPLL_CON0); | 277 | pll_con = __raw_readl(EXYNOS4_VPLL_CON0); |
278 | if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) | 278 | if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) |
279 | vpll_wait = 0; | 279 | vpll_wait = 0; |
280 | } | 280 | } |
281 | } while (epll_wait || vpll_wait); | 281 | } while (epll_wait || vpll_wait); |