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-rw-r--r--arch/arm/mach-exynos/platsmp.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60f7c5be057d..95e04bd5813f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,7 +20,6 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/irqchip/arm-gic.h>
24 23
25#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
26#include <asm/smp_plat.h> 25#include <asm/smp_plat.h>
@@ -76,13 +75,6 @@ static DEFINE_SPINLOCK(boot_lock);
76static void __cpuinit exynos_secondary_init(unsigned int cpu) 75static void __cpuinit exynos_secondary_init(unsigned int cpu)
77{ 76{
78 /* 77 /*
79 * if any interrupts are already enabled for the primary
80 * core (e.g. timer irq), then they will not have been enabled
81 * for us: do so
82 */
83 gic_secondary_init(0);
84
85 /*
86 * let the primary processor know we're out of the 78 * let the primary processor know we're out of the
87 * pen, then head off into the C entry point 79 * pen, then head off into the C entry point
88 */ 80 */