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Diffstat (limited to 'arch/arm/mach-exynos/mach-armlex4210.c')
-rw-r--r--arch/arm/mach-exynos/mach-armlex4210.c215
1 files changed, 215 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
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+++ b/arch/arm/mach-exynos/mach-armlex4210.c
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1/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/gpio.h>
12#include <linux/io.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/smsc911x.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/cpu.h>
22#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h>
26#include <plat/regs-srom.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG4 | \
43 S5PV210_UFCON_RXTRIG4)
44
45static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .flags = 0,
49 .ucon = ARMLEX4210_UCON_DEFAULT,
50 .ulcon = ARMLEX4210_ULCON_DEFAULT,
51 .ufcon = ARMLEX4210_UFCON_DEFAULT,
52 },
53 [1] = {
54 .hwport = 1,
55 .flags = 0,
56 .ucon = ARMLEX4210_UCON_DEFAULT,
57 .ulcon = ARMLEX4210_ULCON_DEFAULT,
58 .ufcon = ARMLEX4210_UFCON_DEFAULT,
59 },
60 [2] = {
61 .hwport = 2,
62 .flags = 0,
63 .ucon = ARMLEX4210_UCON_DEFAULT,
64 .ulcon = ARMLEX4210_ULCON_DEFAULT,
65 .ufcon = ARMLEX4210_UFCON_DEFAULT,
66 },
67 [3] = {
68 .hwport = 3,
69 .flags = 0,
70 .ucon = ARMLEX4210_UCON_DEFAULT,
71 .ulcon = ARMLEX4210_ULCON_DEFAULT,
72 .ufcon = ARMLEX4210_UFCON_DEFAULT,
73 },
74};
75
76static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
77 .cd_type = S3C_SDHCI_CD_PERMANENT,
78 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
79#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
80 .max_width = 8,
81 .host_caps = MMC_CAP_8_BIT_DATA,
82#endif
83};
84
85static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
86 .cd_type = S3C_SDHCI_CD_GPIO,
87 .ext_cd_gpio = EXYNOS4_GPX2(5),
88 .ext_cd_gpio_invert = 1,
89 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
90 .max_width = 4,
91};
92
93static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_PERMANENT,
95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
96 .max_width = 4,
97};
98
99static void __init armlex4210_sdhci_init(void)
100{
101 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
102 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
103 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
104}
105
106static void __init armlex4210_wlan_init(void)
107{
108 /* enable */
109 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
110 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
111
112 /* reset */
113 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
114 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
115
116 /* wakeup */
117 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
118 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
119}
120
121static struct resource armlex4210_smsc911x_resources[] = {
122 [0] = {
123 .start = EXYNOS4_PA_SROM_BANK(3),
124 .end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
125 .flags = IORESOURCE_MEM,
126 },
127 [1] = {
128 .start = IRQ_EINT(27),
129 .end = IRQ_EINT(27),
130 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
131 },
132};
133
134static struct smsc911x_platform_config smsc9215_config = {
135 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
136 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
137 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
138 .phy_interface = PHY_INTERFACE_MODE_MII,
139 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
140};
141
142static struct platform_device armlex4210_smsc911x = {
143 .name = "smsc911x",
144 .id = -1,
145 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
146 .resource = armlex4210_smsc911x_resources,
147 .dev = {
148 .platform_data = &smsc9215_config,
149 },
150};
151
152static struct platform_device *armlex4210_devices[] __initdata = {
153 &s3c_device_hsmmc0,
154 &s3c_device_hsmmc2,
155 &s3c_device_hsmmc3,
156 &s3c_device_rtc,
157 &s3c_device_wdt,
158 &exynos4_device_sysmmu,
159 &samsung_asoc_dma,
160 &armlex4210_smsc911x,
161 &exynos4_device_ahci,
162};
163
164static void __init armlex4210_smsc911x_init(void)
165{
166 u32 cs1;
167
168 /* configure nCS1 width to 16 bits */
169 cs1 = __raw_readl(S5P_SROM_BW) &
170 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
171 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
172 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
173 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
174 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
175 S5P_SROM_BW__NCS1__SHIFT;
176 __raw_writel(cs1, S5P_SROM_BW);
177
178 /* set timing for nCS1 suitable for ethernet chip */
179 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
180 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
181 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
182 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
183 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
184 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
185 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
186}
187
188static void __init armlex4210_map_io(void)
189{
190 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
191 s3c24xx_init_clocks(24000000);
192 s3c24xx_init_uarts(armlex4210_uartcfgs,
193 ARRAY_SIZE(armlex4210_uartcfgs));
194}
195
196static void __init armlex4210_machine_init(void)
197{
198 armlex4210_smsc911x_init();
199
200 armlex4210_sdhci_init();
201
202 armlex4210_wlan_init();
203
204 platform_add_devices(armlex4210_devices,
205 ARRAY_SIZE(armlex4210_devices));
206}
207
208MACHINE_START(ARMLEX4210, "ARMLEX4210")
209 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
210 .atag_offset = 0x100,
211 .init_irq = exynos4_init_irq,
212 .map_io = armlex4210_map_io,
213 .init_machine = armlex4210_machine_init,
214 .timer = &exynos4_timer,
215MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 15:49:18 -0500