2 files changed, 0 insertions, 97 deletions
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index f5e9fd8e37b4..3ba4f547534b 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,83 +9,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                mov     \tmp, #0
-                mrc     p15, 0, \base, c0, c0, 5
-                and     \base, \base, #3
-                cmp     \base, #0
-                beq     1f
-                ldr     \tmp, =gic_bank_offset
-                ldr     \tmp, [\tmp]
-                cmp     \base, #1
-                beq     1f
-                cmp     \base, #2
-                addeq   \tmp, \tmp, \tmp
-                addne   \tmp, \tmp, \tmp, LSL #1
-1:              ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                add     \base, \base, \tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #15
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                addne   \irqnr, \irqnr, #32
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
deleted file mode 100644
index 284330e571d2..000000000000
--- a/arch/arm/mach-exynos/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * EXYNOS4 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */

diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S index f5e9fd8e37b4..3ba4f547534b 100644 --- a/arch/arm/mach-exynos/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,83 +9,8 @@
9	* warranty of any kind, whether express or implied.	9	* warranty of any kind, whether express or implied.
10	*/	10	*/
11		11
12	#include <mach/hardware.h>
13	#include <mach/map.h>
14	#include <asm/hardware/gic.h>
15
16	.macro disable_fiq	12	.macro disable_fiq
17	.endm	13	.endm
18		14
19	.macro get_irqnr_preamble, base, tmp
20	mov \tmp, #0
21
22	mrc p15, 0, \base, c0, c0, 5
23	and \base, \base, #3
24	cmp \base, #0
25	beq 1f
26
27	ldr \tmp, =gic_bank_offset
28	ldr \tmp, [\tmp]
29	cmp \base, #1
30	beq 1f
31
32	cmp \base, #2
33	addeq \tmp, \tmp, \tmp
34	addne \tmp, \tmp, \tmp, LSL #1
35
36	1: ldr \base, =gic_cpu_base_addr
37	ldr \base, [\base]
38	add \base, \base, \tmp
39	.endm
40
41	.macro arch_ret_to_user, tmp1, tmp2	15	.macro arch_ret_to_user, tmp1, tmp2
42	.endm	16	.endm
43
44	/*
45	* The interrupt numbering scheme is defined in the
46	* interrupt controller spec. To wit:
47	*
48	* Interrupts 0-15 are IPI
49	* 16-28 are reserved
50	* 29-31 are local. We allow 30 to be used for the watchdog.
51	* 32-1020 are global
52	* 1021-1022 are reserved
53	* 1023 is "spurious" (no interrupt)
54	*
55	* For now, we ignore all local interrupts so only return an interrupt if it's
56	* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
57	*
58	* A simple read from the controller will tell us the number of the highest
59	* priority enabled interrupt. We then just need to check whether it is in the
60	* valid range for an IRQ (30-1020 inclusive).
61	*/
62
63	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
64
65	ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
66
67	ldr \tmp, =1021
68
69	bic \irqnr, \irqstat, #0x1c00
70
71	cmp \irqnr, #15
72	cmpcc \irqnr, \irqnr
73	cmpne \irqnr, \tmp
74	cmpcs \irqnr, \irqnr
75	addne \irqnr, \irqnr, #32
76
77	.endm
78
79	/* We assume that irqstat (the raw value of the IRQ acknowledge
80	* register) is preserved from the macro above.
81	* If there is an IPI, we immediately signal end of interrupt on the
82	* controller, since this requires the original irqstat value which
83	* we won't easily be able to recreate later.
84	*/
85
86	.macro test_for_ipi, irqnr, irqstat, base, tmp
87	bic \irqnr, \irqstat, #0x1c00
88	cmp \irqnr, #16
89	strcc \irqstat, [\base, #GIC_CPU_EOI]
90	cmpcs \irqnr, \irqnr
91	.endm


diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h deleted file mode 100644 index 284330e571d2..000000000000 --- a/arch/arm/mach-exynos/include/mach/vmalloc.h +++ /dev/null
@@ -1,22 +0,0 @@
1	/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2	*
3	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4	* http://www.samsung.com
5	*
6	* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7	*
8	* Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9	*
10	* This program is free software; you can redistribute it and/or modify
11	* it under the terms of the GNU General Public License version 2 as
12	* published by the Free Software Foundation.
13	*
14	* EXYNOS4 vmalloc definition
15	*/
16
17	#ifndef __ASM_ARCH_VMALLOC_H
18	#define __ASM_ARCH_VMALLOC_H __FILE__
19
20	#define VMALLOC_END 0xF6000000UL
21
22	#endif /* __ASM_ARCH_VMALLOC_H */