diff options
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/entry-macro.S')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/entry-macro.S | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S index f5e9fd8e37b4..3ba4f547534b 100644 --- a/arch/arm/mach-exynos/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos/include/mach/entry-macro.S | |||
| @@ -9,83 +9,8 @@ | |||
| 9 | * warranty of any kind, whether express or implied. | 9 | * warranty of any kind, whether express or implied. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <mach/hardware.h> | ||
| 13 | #include <mach/map.h> | ||
| 14 | #include <asm/hardware/gic.h> | ||
| 15 | |||
| 16 | .macro disable_fiq | 12 | .macro disable_fiq |
| 17 | .endm | 13 | .endm |
| 18 | 14 | ||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | mov \tmp, #0 | ||
| 21 | |||
| 22 | mrc p15, 0, \base, c0, c0, 5 | ||
| 23 | and \base, \base, #3 | ||
| 24 | cmp \base, #0 | ||
| 25 | beq 1f | ||
| 26 | |||
| 27 | ldr \tmp, =gic_bank_offset | ||
| 28 | ldr \tmp, [\tmp] | ||
| 29 | cmp \base, #1 | ||
| 30 | beq 1f | ||
| 31 | |||
| 32 | cmp \base, #2 | ||
| 33 | addeq \tmp, \tmp, \tmp | ||
| 34 | addne \tmp, \tmp, \tmp, LSL #1 | ||
| 35 | |||
| 36 | 1: ldr \base, =gic_cpu_base_addr | ||
| 37 | ldr \base, [\base] | ||
| 38 | add \base, \base, \tmp | ||
| 39 | .endm | ||
| 40 | |||
| 41 | .macro arch_ret_to_user, tmp1, tmp2 | 15 | .macro arch_ret_to_user, tmp1, tmp2 |
| 42 | .endm | 16 | .endm |
| 43 | |||
| 44 | /* | ||
| 45 | * The interrupt numbering scheme is defined in the | ||
| 46 | * interrupt controller spec. To wit: | ||
| 47 | * | ||
| 48 | * Interrupts 0-15 are IPI | ||
| 49 | * 16-28 are reserved | ||
| 50 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 51 | * 32-1020 are global | ||
| 52 | * 1021-1022 are reserved | ||
| 53 | * 1023 is "spurious" (no interrupt) | ||
| 54 | * | ||
| 55 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 56 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 57 | * | ||
| 58 | * A simple read from the controller will tell us the number of the highest | ||
| 59 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 60 | * valid range for an IRQ (30-1020 inclusive). | ||
| 61 | */ | ||
| 62 | |||
| 63 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 64 | |||
| 65 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 66 | |||
| 67 | ldr \tmp, =1021 | ||
| 68 | |||
| 69 | bic \irqnr, \irqstat, #0x1c00 | ||
| 70 | |||
| 71 | cmp \irqnr, #15 | ||
| 72 | cmpcc \irqnr, \irqnr | ||
| 73 | cmpne \irqnr, \tmp | ||
| 74 | cmpcs \irqnr, \irqnr | ||
| 75 | addne \irqnr, \irqnr, #32 | ||
| 76 | |||
| 77 | .endm | ||
| 78 | |||
| 79 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 80 | * register) is preserved from the macro above. | ||
| 81 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 82 | * controller, since this requires the original irqstat value which | ||
| 83 | * we won't easily be able to recreate later. | ||
| 84 | */ | ||
| 85 | |||
| 86 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 87 | bic \irqnr, \irqstat, #0x1c00 | ||
| 88 | cmp \irqnr, #16 | ||
| 89 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 90 | cmpcs \irqnr, \irqnr | ||
| 91 | .endm | ||