diff options
Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r-- | arch/arm/mach-exynos/common.c | 60 |
1 files changed, 47 insertions, 13 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 031c1e5b3dfe..7f1f2687147d 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -26,10 +26,12 @@ | |||
26 | #include <asm/hardware/gic.h> | 26 | #include <asm/hardware/gic.h> |
27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | #include <asm/cacheflush.h> | ||
29 | 30 | ||
30 | #include <mach/regs-irq.h> | 31 | #include <mach/regs-irq.h> |
31 | #include <mach/regs-pmu.h> | 32 | #include <mach/regs-pmu.h> |
32 | #include <mach/regs-gpio.h> | 33 | #include <mach/regs-gpio.h> |
34 | #include <mach/pmu.h> | ||
33 | 35 | ||
34 | #include <plat/cpu.h> | 36 | #include <plat/cpu.h> |
35 | #include <plat/clock.h> | 37 | #include <plat/clock.h> |
@@ -45,6 +47,8 @@ | |||
45 | #include <plat/regs-serial.h> | 47 | #include <plat/regs-serial.h> |
46 | 48 | ||
47 | #include "common.h" | 49 | #include "common.h" |
50 | #define L2_AUX_VAL 0x7C470001 | ||
51 | #define L2_AUX_MASK 0xC200ffff | ||
48 | 52 | ||
49 | static const char name_exynos4210[] = "EXYNOS4210"; | 53 | static const char name_exynos4210[] = "EXYNOS4210"; |
50 | static const char name_exynos4212[] = "EXYNOS4212"; | 54 | static const char name_exynos4212[] = "EXYNOS4212"; |
@@ -173,7 +177,12 @@ static struct map_desc exynos4_iodesc[] __initdata = { | |||
173 | }, { | 177 | }, { |
174 | .virtual = (unsigned long)S5P_VA_DMC0, | 178 | .virtual = (unsigned long)S5P_VA_DMC0, |
175 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), | 179 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), |
176 | .length = SZ_4K, | 180 | .length = SZ_64K, |
181 | .type = MT_DEVICE, | ||
182 | }, { | ||
183 | .virtual = (unsigned long)S5P_VA_DMC1, | ||
184 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), | ||
185 | .length = SZ_64K, | ||
177 | .type = MT_DEVICE, | 186 | .type = MT_DEVICE, |
178 | }, { | 187 | }, { |
179 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, | 188 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, |
@@ -433,23 +442,48 @@ core_initcall(exynos4_core_init); | |||
433 | #ifdef CONFIG_CACHE_L2X0 | 442 | #ifdef CONFIG_CACHE_L2X0 |
434 | static int __init exynos4_l2x0_cache_init(void) | 443 | static int __init exynos4_l2x0_cache_init(void) |
435 | { | 444 | { |
436 | /* TAG, Data Latency Control: 2cycle */ | 445 | int ret; |
437 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); | 446 | ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); |
447 | if (!ret) { | ||
448 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); | ||
449 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
450 | return 0; | ||
451 | } | ||
438 | 452 | ||
439 | if (soc_is_exynos4210()) | 453 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { |
440 | __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 454 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; |
441 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | 455 | /* TAG, Data Latency Control: 2 cycles */ |
442 | __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | 456 | l2x0_saved_regs.tag_latency = 0x110; |
457 | |||
458 | if (soc_is_exynos4212() || soc_is_exynos4412()) | ||
459 | l2x0_saved_regs.data_latency = 0x120; | ||
460 | else | ||
461 | l2x0_saved_regs.data_latency = 0x110; | ||
462 | |||
463 | l2x0_saved_regs.prefetch_ctrl = 0x30000007; | ||
464 | l2x0_saved_regs.pwr_ctrl = | ||
465 | (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); | ||
443 | 466 | ||
444 | /* L2X0 Prefetch Control */ | 467 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); |
445 | __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | ||
446 | 468 | ||
447 | /* L2X0 Power Control */ | 469 | __raw_writel(l2x0_saved_regs.tag_latency, |
448 | __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, | 470 | S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); |
449 | S5P_VA_L2CC + L2X0_POWER_CTRL); | 471 | __raw_writel(l2x0_saved_regs.data_latency, |
472 | S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | ||
450 | 473 | ||
451 | l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); | 474 | /* L2X0 Prefetch Control */ |
475 | __raw_writel(l2x0_saved_regs.prefetch_ctrl, | ||
476 | S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | ||
477 | |||
478 | /* L2X0 Power Control */ | ||
479 | __raw_writel(l2x0_saved_regs.pwr_ctrl, | ||
480 | S5P_VA_L2CC + L2X0_POWER_CTRL); | ||
481 | |||
482 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | ||
483 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); | ||
484 | } | ||
452 | 485 | ||
486 | l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); | ||
453 | return 0; | 487 | return 0; |
454 | } | 488 | } |
455 | 489 | ||