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Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r--arch/arm/mach-exynos/common.c37
1 files changed, 18 insertions, 19 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 647c8434610c..c59e18871006 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -17,6 +17,8 @@
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
20 22
21#include <asm/proc-fns.h> 23#include <asm/proc-fns.h>
22#include <asm/exception.h> 24#include <asm/exception.h>
@@ -385,6 +387,13 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
385 } 387 }
386} 388}
387 389
390#ifdef CONFIG_OF
391static const struct of_device_id exynos4_dt_irq_match[] = {
392 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
393 {},
394};
395#endif
396
388void __init exynos4_init_irq(void) 397void __init exynos4_init_irq(void)
389{ 398{
390 int irq; 399 int irq;
@@ -392,7 +401,12 @@ void __init exynos4_init_irq(void)
392 401
393 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
394 403
395 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); 404 if (!of_have_populated_dt())
405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
406#ifdef CONFIG_OF
407 else
408 of_irq_init(exynos4_dt_irq_match);
409#endif
396 410
397 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
398 412
@@ -460,15 +474,6 @@ int __init exynos_init(void)
460 return device_register(&exynos4_dev); 474 return device_register(&exynos4_dev);
461} 475}
462 476
463static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
464 [0] = {
465 .name = "uclk1",
466 .divisor = 1,
467 .min_baud = 0,
468 .max_baud = 0,
469 },
470};
471
472/* uart registration process */ 477/* uart registration process */
473 478
474void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) 479void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -476,16 +481,10 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
476 struct s3c2410_uartcfg *tcfg = cfg; 481 struct s3c2410_uartcfg *tcfg = cfg;
477 u32 ucnt; 482 u32 ucnt;
478 483
479 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 484 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
480 if (!tcfg->clocks) { 485 tcfg->has_fracval = 1;
481 tcfg->has_fracval = 1;
482 tcfg->clocks = exynos4_serial_clocks;
483 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
484 }
485 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
486 }
487 486
488 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 487 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
489} 488}
490 489
491static DEFINE_SPINLOCK(eint_lock); 490static DEFINE_SPINLOCK(eint_lock);