1 files changed, 66 insertions, 40 deletions

diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5c..fe1851914dac 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1009,46 +1009,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
 
 static struct clksrc_clk clksrcs[] = {
         {
-                .clk    = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.0",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.1",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.2",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.3",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-        }, {
                 .clk            = {
                         .name           = "sclk_pwm",
                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
@@ -1237,6 +1197,54 @@ static struct clksrc_clk clksrcs[] = {
         }
 };
 
+static struct clksrc_clk clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart1 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart2 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uart3 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -1271,6 +1279,20 @@ static struct clksrc_clk *sysclks[] = {
         &clk_mout_mfc1,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart0,
+        &clk_sclk_uart1,
+        &clk_sclk_uart2,
+        &clk_sclk_uart3,
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+};
+
 static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1478,11 +1500,15 @@ void __init exynos4_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
                 s3c_register_clksrc(sclk_tv[ptr], 1);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
 
         register_syscore_ops(&exynos4_clock_syscore_ops);
         s3c24xx_register_clock(&dummy_apb_pclk);