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Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos5.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982d0f8e..5cd7a8b8868c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
455 .ctrlbit = (1 << 20), 455 .ctrlbit = (1 << 20),
456 }, { 456 }, {
457 .name = "hsmmc", 457 .name = "hsmmc",
458 .devname = "s3c-sdhci.0", 458 .devname = "exynos4-sdhci.0",
459 .parent = &exynos5_clk_aclk_200.clk, 459 .parent = &exynos5_clk_aclk_200.clk,
460 .enable = exynos5_clk_ip_fsys_ctrl, 460 .enable = exynos5_clk_ip_fsys_ctrl,
461 .ctrlbit = (1 << 12), 461 .ctrlbit = (1 << 12),
462 }, { 462 }, {
463 .name = "hsmmc", 463 .name = "hsmmc",
464 .devname = "s3c-sdhci.1", 464 .devname = "exynos4-sdhci.1",
465 .parent = &exynos5_clk_aclk_200.clk, 465 .parent = &exynos5_clk_aclk_200.clk,
466 .enable = exynos5_clk_ip_fsys_ctrl, 466 .enable = exynos5_clk_ip_fsys_ctrl,
467 .ctrlbit = (1 << 13), 467 .ctrlbit = (1 << 13),
468 }, { 468 }, {
469 .name = "hsmmc", 469 .name = "hsmmc",
470 .devname = "s3c-sdhci.2", 470 .devname = "exynos4-sdhci.2",
471 .parent = &exynos5_clk_aclk_200.clk, 471 .parent = &exynos5_clk_aclk_200.clk,
472 .enable = exynos5_clk_ip_fsys_ctrl, 472 .enable = exynos5_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 14), 473 .ctrlbit = (1 << 14),
474 }, { 474 }, {
475 .name = "hsmmc", 475 .name = "hsmmc",
476 .devname = "s3c-sdhci.3", 476 .devname = "exynos4-sdhci.3",
477 .parent = &exynos5_clk_aclk_200.clk, 477 .parent = &exynos5_clk_aclk_200.clk,
478 .enable = exynos5_clk_ip_fsys_ctrl, 478 .enable = exynos5_clk_ip_fsys_ctrl,
479 .ctrlbit = (1 << 15), 479 .ctrlbit = (1 << 15),
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
813static struct clksrc_clk exynos5_clk_sclk_mmc0 = { 813static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
814 .clk = { 814 .clk = {
815 .name = "sclk_mmc", 815 .name = "sclk_mmc",
816 .devname = "s3c-sdhci.0", 816 .devname = "exynos4-sdhci.0",
817 .parent = &exynos5_clk_dout_mmc0.clk, 817 .parent = &exynos5_clk_dout_mmc0.clk,
818 .enable = exynos5_clksrc_mask_fsys_ctrl, 818 .enable = exynos5_clksrc_mask_fsys_ctrl,
819 .ctrlbit = (1 << 0), 819 .ctrlbit = (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
824static struct clksrc_clk exynos5_clk_sclk_mmc1 = { 824static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
825 .clk = { 825 .clk = {
826 .name = "sclk_mmc", 826 .name = "sclk_mmc",
827 .devname = "s3c-sdhci.1", 827 .devname = "exynos4-sdhci.1",
828 .parent = &exynos5_clk_dout_mmc1.clk, 828 .parent = &exynos5_clk_dout_mmc1.clk,
829 .enable = exynos5_clksrc_mask_fsys_ctrl, 829 .enable = exynos5_clksrc_mask_fsys_ctrl,
830 .ctrlbit = (1 << 4), 830 .ctrlbit = (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
835static struct clksrc_clk exynos5_clk_sclk_mmc2 = { 835static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
836 .clk = { 836 .clk = {
837 .name = "sclk_mmc", 837 .name = "sclk_mmc",
838 .devname = "s3c-sdhci.2", 838 .devname = "exynos4-sdhci.2",
839 .parent = &exynos5_clk_dout_mmc2.clk, 839 .parent = &exynos5_clk_dout_mmc2.clk,
840 .enable = exynos5_clksrc_mask_fsys_ctrl, 840 .enable = exynos5_clksrc_mask_fsys_ctrl,
841 .ctrlbit = (1 << 8), 841 .ctrlbit = (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
846static struct clksrc_clk exynos5_clk_sclk_mmc3 = { 846static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
847 .clk = { 847 .clk = {
848 .name = "sclk_mmc", 848 .name = "sclk_mmc",
849 .devname = "s3c-sdhci.3", 849 .devname = "exynos4-sdhci.3",
850 .parent = &exynos5_clk_dout_mmc3.clk, 850 .parent = &exynos5_clk_dout_mmc3.clk,
851 .enable = exynos5_clksrc_mask_fsys_ctrl, 851 .enable = exynos5_clksrc_mask_fsys_ctrl,
852 .ctrlbit = (1 << 12), 852 .ctrlbit = (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
990 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), 990 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
991 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), 991 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
992 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), 992 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
993 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), 993 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), 994 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), 995 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), 996 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
997 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), 997 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
998 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), 998 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
999 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), 999 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),