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Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos5.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c51
1 files changed, 49 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, 165 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
166}; 166};
167 167
168static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
169 .clk = {
170 .name = "mout_bpll_fout",
171 },
172 .sources = &clk_src_bpll_fout,
173 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
174};
175
176static struct clk *exynos5_clk_src_bpll_list[] = {
177 [0] = &clk_fin_bpll,
178 [1] = &exynos5_clk_mout_bpll_fout.clk,
179};
180
181static struct clksrc_sources exynos5_clk_src_bpll = {
182 .sources = exynos5_clk_src_bpll_list,
183 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
184};
185
168static struct clksrc_clk exynos5_clk_mout_bpll = { 186static struct clksrc_clk exynos5_clk_mout_bpll = {
169 .clk = { 187 .clk = {
170 .name = "mout_bpll", 188 .name = "mout_bpll",
171 }, 189 },
172 .sources = &clk_src_bpll, 190 .sources = &exynos5_clk_src_bpll,
173 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, 191 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
174}; 192};
175 193
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
207 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, 225 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
208}; 226};
209 227
228static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
229 .clk = {
230 .name = "mout_mpll_fout",
231 },
232 .sources = &clk_src_mpll_fout,
233 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
234};
235
236static struct clk *exynos5_clk_src_mpll_list[] = {
237 [0] = &clk_fin_mpll,
238 [1] = &exynos5_clk_mout_mpll_fout.clk,
239};
240
241static struct clksrc_sources exynos5_clk_src_mpll = {
242 .sources = exynos5_clk_src_mpll_list,
243 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
244};
245
210struct clksrc_clk exynos5_clk_mout_mpll = { 246struct clksrc_clk exynos5_clk_mout_mpll = {
211 .clk = { 247 .clk = {
212 .name = "mout_mpll", 248 .name = "mout_mpll",
213 }, 249 },
214 .sources = &clk_src_mpll, 250 .sources = &exynos5_clk_src_mpll,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, 251 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
216}; 252};
217 253
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
474 .enable = exynos5_clk_ip_peris_ctrl, 510 .enable = exynos5_clk_ip_peris_ctrl,
475 .ctrlbit = (1 << 20), 511 .ctrlbit = (1 << 20),
476 }, { 512 }, {
513 .name = "watchdog",
514 .parent = &exynos5_clk_aclk_66.clk,
515 .enable = exynos5_clk_ip_peris_ctrl,
516 .ctrlbit = (1 << 19),
517 }, {
477 .name = "hsmmc", 518 .name = "hsmmc",
478 .devname = "exynos4-sdhci.0", 519 .devname = "exynos4-sdhci.0",
479 .parent = &exynos5_clk_aclk_200.clk, 520 .parent = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
1031 &exynos5_clk_mout_apll, 1072 &exynos5_clk_mout_apll,
1032 &exynos5_clk_sclk_apll, 1073 &exynos5_clk_sclk_apll,
1033 &exynos5_clk_mout_bpll, 1074 &exynos5_clk_mout_bpll,
1075 &exynos5_clk_mout_bpll_fout,
1034 &exynos5_clk_mout_bpll_user, 1076 &exynos5_clk_mout_bpll_user,
1035 &exynos5_clk_mout_cpll, 1077 &exynos5_clk_mout_cpll,
1036 &exynos5_clk_mout_epll, 1078 &exynos5_clk_mout_epll,
1037 &exynos5_clk_mout_mpll, 1079 &exynos5_clk_mout_mpll,
1080 &exynos5_clk_mout_mpll_fout,
1038 &exynos5_clk_mout_mpll_user, 1081 &exynos5_clk_mout_mpll_user,
1039 &exynos5_clk_vpllsrc, 1082 &exynos5_clk_vpllsrc,
1040 &exynos5_clk_sclk_vpll, 1083 &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
1098 &exynos5_clk_sclk_hdmi27m, 1141 &exynos5_clk_sclk_hdmi27m,
1099 &exynos5_clk_sclk_hdmiphy, 1142 &exynos5_clk_sclk_hdmiphy,
1100 &clk_fout_bpll, 1143 &clk_fout_bpll,
1144 &clk_fout_bpll_div2,
1101 &clk_fout_cpll, 1145 &clk_fout_cpll,
1146 &clk_fout_mpll_div2,
1102 &exynos5_clk_armclk, 1147 &exynos5_clk_armclk,
1103}; 1148};
1104 1149
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
1263 1308
1264 clk_fout_apll.ops = &exynos5_fout_apll_ops; 1309 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1265 clk_fout_bpll.rate = bpll; 1310 clk_fout_bpll.rate = bpll;
1311 clk_fout_bpll_div2.rate = bpll >> 1;
1266 clk_fout_cpll.rate = cpll; 1312 clk_fout_cpll.rate = cpll;
1267 clk_fout_mpll.rate = mpll; 1313 clk_fout_mpll.rate = mpll;
1314 clk_fout_mpll_div2.rate = mpll >> 1;
1268 clk_fout_epll.rate = epll; 1315 clk_fout_epll.rate = epll;
1269 clk_fout_vpll.rate = vpll; 1316 clk_fout_vpll.rate = vpll;
1270 1317