diff options
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
| -rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 67 |
1 files changed, 48 insertions, 19 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c | |||
| @@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { | |||
| 586 | .ctrlbit = (1 << 13), | 586 | .ctrlbit = (1 << 13), |
| 587 | }, { | 587 | }, { |
| 588 | .name = "spi", | 588 | .name = "spi", |
| 589 | .devname = "s3c64xx-spi.0", | 589 | .devname = "exynos4210-spi.0", |
| 590 | .enable = exynos4_clk_ip_peril_ctrl, | 590 | .enable = exynos4_clk_ip_peril_ctrl, |
| 591 | .ctrlbit = (1 << 16), | 591 | .ctrlbit = (1 << 16), |
| 592 | }, { | 592 | }, { |
| 593 | .name = "spi", | 593 | .name = "spi", |
| 594 | .devname = "s3c64xx-spi.1", | 594 | .devname = "exynos4210-spi.1", |
| 595 | .enable = exynos4_clk_ip_peril_ctrl, | 595 | .enable = exynos4_clk_ip_peril_ctrl, |
| 596 | .ctrlbit = (1 << 17), | 596 | .ctrlbit = (1 << 17), |
| 597 | }, { | 597 | }, { |
| 598 | .name = "spi", | 598 | .name = "spi", |
| 599 | .devname = "s3c64xx-spi.2", | 599 | .devname = "exynos4210-spi.2", |
| 600 | .enable = exynos4_clk_ip_peril_ctrl, | 600 | .enable = exynos4_clk_ip_peril_ctrl, |
| 601 | .ctrlbit = (1 << 18), | 601 | .ctrlbit = (1 << 18), |
| 602 | }, { | 602 | }, { |
| @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { | |||
| 1242 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | 1242 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
| 1243 | }; | 1243 | }; |
| 1244 | 1244 | ||
| 1245 | static struct clksrc_clk exynos4_clk_mdout_spi0 = { | ||
| 1246 | .clk = { | ||
| 1247 | .name = "mdout_spi", | ||
| 1248 | .devname = "exynos4210-spi.0", | ||
| 1249 | }, | ||
| 1250 | .sources = &exynos4_clkset_group, | ||
| 1251 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | ||
| 1252 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | ||
| 1253 | }; | ||
| 1254 | |||
| 1255 | static struct clksrc_clk exynos4_clk_mdout_spi1 = { | ||
| 1256 | .clk = { | ||
| 1257 | .name = "mdout_spi", | ||
| 1258 | .devname = "exynos4210-spi.1", | ||
| 1259 | }, | ||
| 1260 | .sources = &exynos4_clkset_group, | ||
| 1261 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | ||
| 1262 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | ||
| 1263 | }; | ||
| 1264 | |||
| 1265 | static struct clksrc_clk exynos4_clk_mdout_spi2 = { | ||
| 1266 | .clk = { | ||
| 1267 | .name = "mdout_spi", | ||
| 1268 | .devname = "exynos4210-spi.2", | ||
| 1269 | }, | ||
| 1270 | .sources = &exynos4_clkset_group, | ||
| 1271 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | ||
| 1272 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | ||
| 1273 | }; | ||
| 1274 | |||
| 1245 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { | 1275 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { |
| 1246 | .clk = { | 1276 | .clk = { |
| 1247 | .name = "sclk_spi", | 1277 | .name = "sclk_spi", |
| 1248 | .devname = "s3c64xx-spi.0", | 1278 | .devname = "exynos4210-spi.0", |
| 1279 | .parent = &exynos4_clk_mdout_spi0.clk, | ||
| 1249 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1280 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
| 1250 | .ctrlbit = (1 << 16), | 1281 | .ctrlbit = (1 << 16), |
| 1251 | }, | 1282 | }, |
| 1252 | .sources = &exynos4_clkset_group, | 1283 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, |
| 1253 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | ||
| 1254 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | ||
| 1255 | }; | 1284 | }; |
| 1256 | 1285 | ||
| 1257 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { | 1286 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { |
| 1258 | .clk = { | 1287 | .clk = { |
| 1259 | .name = "sclk_spi", | 1288 | .name = "sclk_spi", |
| 1260 | .devname = "s3c64xx-spi.1", | 1289 | .devname = "exynos4210-spi.1", |
| 1290 | .parent = &exynos4_clk_mdout_spi1.clk, | ||
| 1261 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1291 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
| 1262 | .ctrlbit = (1 << 20), | 1292 | .ctrlbit = (1 << 20), |
| 1263 | }, | 1293 | }, |
| 1264 | .sources = &exynos4_clkset_group, | 1294 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, |
| 1265 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | ||
| 1266 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | ||
| 1267 | }; | 1295 | }; |
| 1268 | 1296 | ||
| 1269 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { | 1297 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { |
| 1270 | .clk = { | 1298 | .clk = { |
| 1271 | .name = "sclk_spi", | 1299 | .name = "sclk_spi", |
| 1272 | .devname = "s3c64xx-spi.2", | 1300 | .devname = "exynos4210-spi.2", |
| 1301 | .parent = &exynos4_clk_mdout_spi2.clk, | ||
| 1273 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1302 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
| 1274 | .ctrlbit = (1 << 24), | 1303 | .ctrlbit = (1 << 24), |
| 1275 | }, | 1304 | }, |
| 1276 | .sources = &exynos4_clkset_group, | 1305 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, |
| 1277 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | ||
| 1278 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | ||
| 1279 | }; | 1306 | }; |
| 1280 | 1307 | ||
| 1281 | /* Clock initialization code */ | 1308 | /* Clock initialization code */ |
| @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { | |||
| 1331 | &exynos4_clk_sclk_spi0, | 1358 | &exynos4_clk_sclk_spi0, |
| 1332 | &exynos4_clk_sclk_spi1, | 1359 | &exynos4_clk_sclk_spi1, |
| 1333 | &exynos4_clk_sclk_spi2, | 1360 | &exynos4_clk_sclk_spi2, |
| 1334 | 1361 | &exynos4_clk_mdout_spi0, | |
| 1362 | &exynos4_clk_mdout_spi1, | ||
| 1363 | &exynos4_clk_mdout_spi2, | ||
| 1335 | }; | 1364 | }; |
| 1336 | 1365 | ||
| 1337 | static struct clk_lookup exynos4_clk_lookup[] = { | 1366 | static struct clk_lookup exynos4_clk_lookup[] = { |
| @@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { | |||
| 1347 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), | 1376 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
| 1348 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | 1377 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), |
| 1349 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), | 1378 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), |
| 1350 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), | 1379 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), |
| 1351 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), | 1380 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), |
| 1352 | CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), | 1381 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), |
| 1353 | }; | 1382 | }; |
| 1354 | 1383 | ||
| 1355 | static int xtal_rate; | 1384 | static int xtal_rate; |