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Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 962c95e00c00..860b73fcd2a1 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -95,21 +95,21 @@ static struct sleep_save exynos4_clock_save[] = {
95}; 95};
96#endif 96#endif
97 97
98struct clk clk_sclk_hdmi27m = { 98static struct clk clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m", 99 .name = "sclk_hdmi27m",
100 .rate = 27000000, 100 .rate = 27000000,
101}; 101};
102 102
103struct clk clk_sclk_hdmiphy = { 103static struct clk clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy", 104 .name = "sclk_hdmiphy",
105}; 105};
106 106
107struct clk clk_sclk_usbphy0 = { 107static struct clk clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0", 108 .name = "sclk_usbphy0",
109 .rate = 27000000, 109 .rate = 27000000,
110}; 110};
111 111
112struct clk clk_sclk_usbphy1 = { 112static struct clk clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1", 113 .name = "sclk_usbphy1",
114}; 114};
115 115
@@ -218,7 +218,7 @@ static struct clksrc_clk clk_mout_apll = {
218 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 218 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
219}; 219};
220 220
221struct clksrc_clk clk_sclk_apll = { 221static struct clksrc_clk clk_sclk_apll = {
222 .clk = { 222 .clk = {
223 .name = "sclk_apll", 223 .name = "sclk_apll",
224 .parent = &clk_mout_apll.clk, 224 .parent = &clk_mout_apll.clk,
@@ -226,7 +226,7 @@ struct clksrc_clk clk_sclk_apll = {
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
227}; 227};
228 228
229struct clksrc_clk clk_mout_epll = { 229static struct clksrc_clk clk_mout_epll = {
230 .clk = { 230 .clk = {
231 .name = "mout_epll", 231 .name = "mout_epll",
232 }, 232 },
@@ -310,7 +310,7 @@ static struct clksrc_clk clk_periphclk = {
310 310
311/* Core list of CMU_CORE side */ 311/* Core list of CMU_CORE side */
312 312
313struct clk *clkset_corebus_list[] = { 313static struct clk *clkset_corebus_list[] = {
314 [0] = &clk_mout_mpll.clk, 314 [0] = &clk_mout_mpll.clk,
315 [1] = &clk_sclk_apll.clk, 315 [1] = &clk_sclk_apll.clk,
316}; 316};
@@ -375,7 +375,7 @@ struct clk *clkset_aclk_top_list[] = {
375 [1] = &clk_sclk_apll.clk, 375 [1] = &clk_sclk_apll.clk,
376}; 376};
377 377
378struct clksrc_sources clkset_aclk = { 378static struct clksrc_sources clkset_aclk = {
379 .sources = clkset_aclk_top_list, 379 .sources = clkset_aclk_top_list,
380 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 380 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
381}; 381};
@@ -446,7 +446,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
446 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), 446 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
447}; 447};
448 448
449struct clksrc_clk clk_sclk_vpll = { 449static struct clksrc_clk clk_sclk_vpll = {
450 .clk = { 450 .clk = {
451 .name = "sclk_vpll", 451 .name = "sclk_vpll",
452 }, 452 },