diff options
Diffstat (limited to 'arch/arm/mach-ep93xx/clock.c')
-rw-r--r-- | arch/arm/mach-ep93xx/clock.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index b2eede5531c8..6c4c1633ed12 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
@@ -72,58 +72,58 @@ static struct clk clk_h; | |||
72 | static struct clk clk_p; | 72 | static struct clk clk_p; |
73 | static struct clk clk_pll2; | 73 | static struct clk clk_pll2; |
74 | static struct clk clk_usb_host = { | 74 | static struct clk clk_usb_host = { |
75 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 75 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
76 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, | 76 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, |
77 | }; | 77 | }; |
78 | 78 | ||
79 | /* DMA Clocks */ | 79 | /* DMA Clocks */ |
80 | static struct clk clk_m2p0 = { | 80 | static struct clk clk_m2p0 = { |
81 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 81 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
82 | .enable_mask = 0x00020000, | 82 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, |
83 | }; | 83 | }; |
84 | static struct clk clk_m2p1 = { | 84 | static struct clk clk_m2p1 = { |
85 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 85 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
86 | .enable_mask = 0x00010000, | 86 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, |
87 | }; | 87 | }; |
88 | static struct clk clk_m2p2 = { | 88 | static struct clk clk_m2p2 = { |
89 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 89 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
90 | .enable_mask = 0x00080000, | 90 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, |
91 | }; | 91 | }; |
92 | static struct clk clk_m2p3 = { | 92 | static struct clk clk_m2p3 = { |
93 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 93 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
94 | .enable_mask = 0x00040000, | 94 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, |
95 | }; | 95 | }; |
96 | static struct clk clk_m2p4 = { | 96 | static struct clk clk_m2p4 = { |
97 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 97 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
98 | .enable_mask = 0x00200000, | 98 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, |
99 | }; | 99 | }; |
100 | static struct clk clk_m2p5 = { | 100 | static struct clk clk_m2p5 = { |
101 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 101 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
102 | .enable_mask = 0x00100000, | 102 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, |
103 | }; | 103 | }; |
104 | static struct clk clk_m2p6 = { | 104 | static struct clk clk_m2p6 = { |
105 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 105 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
106 | .enable_mask = 0x00800000, | 106 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, |
107 | }; | 107 | }; |
108 | static struct clk clk_m2p7 = { | 108 | static struct clk clk_m2p7 = { |
109 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 109 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
110 | .enable_mask = 0x00400000, | 110 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, |
111 | }; | 111 | }; |
112 | static struct clk clk_m2p8 = { | 112 | static struct clk clk_m2p8 = { |
113 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 113 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
114 | .enable_mask = 0x02000000, | 114 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, |
115 | }; | 115 | }; |
116 | static struct clk clk_m2p9 = { | 116 | static struct clk clk_m2p9 = { |
117 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 117 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
118 | .enable_mask = 0x01000000, | 118 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, |
119 | }; | 119 | }; |
120 | static struct clk clk_m2m0 = { | 120 | static struct clk clk_m2m0 = { |
121 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 121 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
122 | .enable_mask = 0x04000000, | 122 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, |
123 | }; | 123 | }; |
124 | static struct clk clk_m2m1 = { | 124 | static struct clk clk_m2m1 = { |
125 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | 125 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
126 | .enable_mask = 0x08000000, | 126 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, |
127 | }; | 127 | }; |
128 | 128 | ||
129 | #define INIT_CK(dev,con,ck) \ | 129 | #define INIT_CK(dev,con,ck) \ |
@@ -138,7 +138,7 @@ static struct clk_lookup clocks[] = { | |||
138 | INIT_CK(NULL, "hclk", &clk_h), | 138 | INIT_CK(NULL, "hclk", &clk_h), |
139 | INIT_CK(NULL, "pclk", &clk_p), | 139 | INIT_CK(NULL, "pclk", &clk_p), |
140 | INIT_CK(NULL, "pll2", &clk_pll2), | 140 | INIT_CK(NULL, "pll2", &clk_pll2), |
141 | INIT_CK(NULL, "usb_host", &clk_usb_host), | 141 | INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), |
142 | INIT_CK(NULL, "m2p0", &clk_m2p0), | 142 | INIT_CK(NULL, "m2p0", &clk_m2p0), |
143 | INIT_CK(NULL, "m2p1", &clk_m2p1), | 143 | INIT_CK(NULL, "m2p1", &clk_m2p1), |
144 | INIT_CK(NULL, "m2p2", &clk_m2p2), | 144 | INIT_CK(NULL, "m2p2", &clk_m2p2), |
@@ -186,8 +186,8 @@ static unsigned long get_uart_rate(struct clk *clk) | |||
186 | { | 186 | { |
187 | u32 value; | 187 | u32 value; |
188 | 188 | ||
189 | value = __raw_readl(EP93XX_SYSCON_CLOCK_CONTROL); | 189 | value = __raw_readl(EP93XX_SYSCON_PWRCNT); |
190 | if (value & EP93XX_SYSCON_CLOCK_UARTBAUD) | 190 | if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) |
191 | return EP93XX_EXT_CLK_RATE; | 191 | return EP93XX_EXT_CLK_RATE; |
192 | else | 192 | else |
193 | return EP93XX_EXT_CLK_RATE / 2; | 193 | return EP93XX_EXT_CLK_RATE / 2; |