1 files changed, 173 insertions, 44 deletions

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6c4c1633ed12..dda19cd76194 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -22,48 +22,39 @@
 #include <mach/hardware.h>
 
 
-/*
- * The EP93xx has two external crystal oscillators.  To generate the
- * required high-frequency clocks, the processor uses two phase-locked-
- * loops (PLLs) to multiply the incoming external clock signal to much
- * higher frequencies that are then divided down by programmable dividers
- * to produce the needed clocks.  The PLLs operate independently of one
- * another.
- */
-#define EP93XX_EXT_CLK_RATE     14745600
-#define EP93XX_EXT_RTC_RATE     32768
-
-
 struct clk {
         unsigned long   rate;
         int             users;
         int             sw_locked;
-        u32             enable_reg;
+        void __iomem    *enable_reg;
         u32             enable_mask;
 
         unsigned long   (*get_rate)(struct clk *clk);
+        int             (*set_rate)(struct clk *clk, unsigned long rate);
 };
 
 
 static unsigned long get_uart_rate(struct clk *clk);
 
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
+static int set_div_rate(struct clk *clk, unsigned long rate);
 
 static struct clk clk_uart1 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart2 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart3 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_pll1;
@@ -75,6 +66,22 @@ static struct clk clk_usb_host = {
         .enable_reg     = EP93XX_SYSCON_PWRCNT,
         .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
 };
+static struct clk clk_keypad = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_KEYTCHCLKDIV,
+        .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
+        .set_rate       = set_keytchclk_rate,
+};
+static struct clk clk_pwm = {
+        .rate           = EP93XX_EXT_CLK_RATE,
+};
+
+static struct clk clk_video = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
+        .enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
+        .set_rate       = set_div_rate,
+};
 
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
@@ -130,27 +137,30 @@ static struct clk clk_m2m1 = {
         { .dev_id = dev, .con_id = con, .clk = ck }
 
 static struct clk_lookup clocks[] = {
-        INIT_CK("apb:uart1", NULL, &clk_uart1),
-        INIT_CK("apb:uart2", NULL, &clk_uart2),
-        INIT_CK("apb:uart3", NULL, &clk_uart3),
-        INIT_CK(NULL, "pll1", &clk_pll1),
-        INIT_CK(NULL, "fclk", &clk_f),
-        INIT_CK(NULL, "hclk", &clk_h),
-        INIT_CK(NULL, "pclk", &clk_p),
-        INIT_CK(NULL, "pll2", &clk_pll2),
-        INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
-        INIT_CK(NULL, "m2p0", &clk_m2p0),
-        INIT_CK(NULL, "m2p1", &clk_m2p1),
-        INIT_CK(NULL, "m2p2", &clk_m2p2),
-        INIT_CK(NULL, "m2p3", &clk_m2p3),
-        INIT_CK(NULL, "m2p4", &clk_m2p4),
-        INIT_CK(NULL, "m2p5", &clk_m2p5),
-        INIT_CK(NULL, "m2p6", &clk_m2p6),
-        INIT_CK(NULL, "m2p7", &clk_m2p7),
-        INIT_CK(NULL, "m2p8", &clk_m2p8),
-        INIT_CK(NULL, "m2p9", &clk_m2p9),
-        INIT_CK(NULL, "m2m0", &clk_m2m0),
-        INIT_CK(NULL, "m2m1", &clk_m2m1),
+        INIT_CK("apb:uart1",            NULL,           &clk_uart1),
+        INIT_CK("apb:uart2",            NULL,           &clk_uart2),
+        INIT_CK("apb:uart3",            NULL,           &clk_uart3),
+        INIT_CK(NULL,                   "pll1",         &clk_pll1),
+        INIT_CK(NULL,                   "fclk",         &clk_f),
+        INIT_CK(NULL,                   "hclk",         &clk_h),
+        INIT_CK(NULL,                   "pclk",         &clk_p),
+        INIT_CK(NULL,                   "pll2",         &clk_pll2),
+        INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
+        INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
+        INIT_CK("ep93xx-fb",            NULL,           &clk_video),
+        INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
+        INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
+        INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
+        INIT_CK(NULL,                   "m2p2",         &clk_m2p2),
+        INIT_CK(NULL,                   "m2p3",         &clk_m2p3),
+        INIT_CK(NULL,                   "m2p4",         &clk_m2p4),
+        INIT_CK(NULL,                   "m2p5",         &clk_m2p5),
+        INIT_CK(NULL,                   "m2p6",         &clk_m2p6),
+        INIT_CK(NULL,                   "m2p7",         &clk_m2p7),
+        INIT_CK(NULL,                   "m2p8",         &clk_m2p8),
+        INIT_CK(NULL,                   "m2p9",         &clk_m2p9),
+        INIT_CK(NULL,                   "m2m0",         &clk_m2m0),
+        INIT_CK(NULL,                   "m2m1",         &clk_m2m1),
 };
 
 
@@ -160,9 +170,11 @@ int clk_enable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value |= clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value | clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 
         return 0;
@@ -175,9 +187,11 @@ void clk_disable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value &= ~clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 }
 EXPORT_SYMBOL(clk_disable);
@@ -202,6 +216,121 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val;
+        u32 div_bit;
+
+        val = __raw_readl(clk->enable_reg);
+
+        /*
+         * The Key Matrix and ADC clocks are configured using the same
+         * System Controller register.  The clock used will be either
+         * 1/4 or 1/16 the external clock rate depending on the
+         * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
+         * bit being set or cleared.
+         */
+        div_bit = clk->enable_mask >> 15;
+
+        if (rate == EP93XX_KEYTCHCLK_DIV4)
+                val |= div_bit;
+        else if (rate == EP93XX_KEYTCHCLK_DIV16)
+                val &= ~div_bit;
+        else
+                return -EINVAL;
+
+        ep93xx_syscon_swlocked_write(val, clk->enable_reg);
+        clk->rate = rate;
+        return 0;
+}
+
+static unsigned long calc_clk_div(unsigned long rate, int *psel, int *esel,
+                                  int *pdiv, int *div)
+{
+        unsigned long max_rate, best_rate = 0,
+                actual_rate = 0, mclk_rate = 0, rate_err = -1;
+        int i, found = 0, __div = 0, __pdiv = 0;
+
+        /* Don't exceed the maximum rate */
+        max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
+                       (unsigned long)EP93XX_EXT_CLK_RATE / 4);
+        rate = min(rate, max_rate);
+
+        /*
+         * Try the two pll's and the external clock
+         * Because the valid predividers are 2, 2.5 and 3, we multiply
+         * all the clocks by 2 to avoid floating point math.
+         *
+         * This is based on the algorithm in the ep93xx raster guide:
+         * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
+         *
+         */
+        for (i = 0; i < 3; i++) {
+                if (i == 0)
+                        mclk_rate = EP93XX_EXT_CLK_RATE * 2;
+                else if (i == 1)
+                        mclk_rate = clk_pll1.rate * 2;
+                else if (i == 2)
+                        mclk_rate = clk_pll2.rate * 2;
+
+                /* Try each predivider value */
+                for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
+                        __div = mclk_rate / (rate * __pdiv);
+                        if (__div < 2 || __div > 127)
+                                continue;
+
+                        actual_rate = mclk_rate / (__pdiv * __div);
+
+                        if (!found || abs(actual_rate - rate) < rate_err) {
+                                *pdiv = __pdiv - 3;
+                                *div = __div;
+                                *psel = (i == 2);
+                                *esel = (i != 0);
+                                best_rate = actual_rate;
+                                rate_err = abs(actual_rate - rate);
+                                found = 1;
+                        }
+                }
+        }
+
+        if (!found)
+                return 0;
+
+        return best_rate;
+}
+
+static int set_div_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long actual_rate;
+        int psel = 0, esel = 0, pdiv = 0, div = 0;
+        u32 val;
+
+        actual_rate = calc_clk_div(rate, &psel, &esel, &pdiv, &div);
+        if (actual_rate == 0)
+                return -EINVAL;
+        clk->rate = actual_rate;
+
+        /* Clear the esel, psel, pdiv and div bits */
+        val = __raw_readl(clk->enable_reg);
+        val &= ~0x7fff;
+
+        /* Set the new esel, psel, pdiv and div bits for the new clock rate */
+        val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
+                (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
+                (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
+        ep93xx_syscon_swlocked_write(val, clk->enable_reg);
+        return 0;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->set_rate)
+                return clk->set_rate(clk, rate);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
 
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };