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-rw-r--r--arch/arm/mach-dove/common.c616
-rw-r--r--arch/arm/mach-dove/mpp.c134
-rw-r--r--arch/arm/mach-dove/mpp.h362
3 files changed, 244 insertions, 868 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f1f81d..5ed51b84c1b2 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/mbus.h> 18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h> 20#include <linux/serial_8250.h>
23#include <linux/gpio.h> 21#include <linux/gpio.h>
24#include <asm/page.h> 22#include <asm/page.h>
25#include <asm/setup.h> 23#include <asm/setup.h>
@@ -32,11 +30,12 @@
32#include <mach/bridge-regs.h> 30#include <mach/bridge-regs.h>
33#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
34#include <linux/irq.h> 32#include <linux/irq.h>
35#include <plat/mv_xor.h>
36#include <plat/ehci-orion.h>
37#include <plat/time.h> 33#include <plat/time.h>
34#include <plat/common.h>
38#include "common.h" 35#include "common.h"
39 36
37static int get_tclk(void);
38
40/***************************************************************************** 39/*****************************************************************************
41 * I/O Address Mapping 40 * I/O Address Mapping
42 ****************************************************************************/ 41 ****************************************************************************/
@@ -70,463 +69,106 @@ void __init dove_map_io(void)
70} 69}
71 70
72/***************************************************************************** 71/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data dove_ehci_data = {
76 .dram = &dove_mbus_dram_info,
77 .phy_version = EHCI_PHY_NA,
78};
79
80static u64 ehci_dmamask = DMA_BIT_MASK(32);
81
82/*****************************************************************************
83 * EHCI0 72 * EHCI0
84 ****************************************************************************/ 73 ****************************************************************************/
85static struct resource dove_ehci0_resources[] = {
86 {
87 .start = DOVE_USB0_PHYS_BASE,
88 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = IRQ_DOVE_USB0,
92 .end = IRQ_DOVE_USB0,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device dove_ehci0 = {
98 .name = "orion-ehci",
99 .id = 0,
100 .dev = {
101 .dma_mask = &ehci_dmamask,
102 .coherent_dma_mask = DMA_BIT_MASK(32),
103 .platform_data = &dove_ehci_data,
104 },
105 .resource = dove_ehci0_resources,
106 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
107};
108
109void __init dove_ehci0_init(void) 74void __init dove_ehci0_init(void)
110{ 75{
111 platform_device_register(&dove_ehci0); 76 orion_ehci_init(&dove_mbus_dram_info,
77 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
112} 78}
113 79
114/***************************************************************************** 80/*****************************************************************************
115 * EHCI1 81 * EHCI1
116 ****************************************************************************/ 82 ****************************************************************************/
117static struct resource dove_ehci1_resources[] = {
118 {
119 .start = DOVE_USB1_PHYS_BASE,
120 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_DOVE_USB1,
124 .end = IRQ_DOVE_USB1,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device dove_ehci1 = {
130 .name = "orion-ehci",
131 .id = 1,
132 .dev = {
133 .dma_mask = &ehci_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &dove_ehci_data,
136 },
137 .resource = dove_ehci1_resources,
138 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
139};
140
141void __init dove_ehci1_init(void) 83void __init dove_ehci1_init(void)
142{ 84{
143 platform_device_register(&dove_ehci1); 85 orion_ehci_1_init(&dove_mbus_dram_info,
86 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
144} 87}
145 88
146/***************************************************************************** 89/*****************************************************************************
147 * GE00 90 * GE00
148 ****************************************************************************/ 91 ****************************************************************************/
149struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
150 .t_clk = 0,
151 .dram = &dove_mbus_dram_info,
152};
153
154static struct resource dove_ge00_shared_resources[] = {
155 {
156 .name = "ge00 base",
157 .start = DOVE_GE00_PHYS_BASE + 0x2000,
158 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device dove_ge00_shared = {
164 .name = MV643XX_ETH_SHARED_NAME,
165 .id = 0,
166 .dev = {
167 .platform_data = &dove_ge00_shared_data,
168 },
169 .num_resources = 1,
170 .resource = dove_ge00_shared_resources,
171};
172
173static struct resource dove_ge00_resources[] = {
174 {
175 .name = "ge00 irq",
176 .start = IRQ_DOVE_GE00_SUM,
177 .end = IRQ_DOVE_GE00_SUM,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device dove_ge00 = {
183 .name = MV643XX_ETH_NAME,
184 .id = 0,
185 .num_resources = 1,
186 .resource = dove_ge00_resources,
187 .dev = {
188 .coherent_dma_mask = 0xffffffff,
189 },
190};
191
192void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 92void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
193{ 93{
194 eth_data->shared = &dove_ge00_shared; 94 orion_ge00_init(eth_data, &dove_mbus_dram_info,
195 dove_ge00.dev.platform_data = eth_data; 95 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
196 96 0, get_tclk());
197 platform_device_register(&dove_ge00_shared);
198 platform_device_register(&dove_ge00);
199} 97}
200 98
201/***************************************************************************** 99/*****************************************************************************
202 * SoC RTC 100 * SoC RTC
203 ****************************************************************************/ 101 ****************************************************************************/
204static struct resource dove_rtc_resource[] = {
205 {
206 .start = DOVE_RTC_PHYS_BASE,
207 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
208 .flags = IORESOURCE_MEM,
209 }, {
210 .start = IRQ_DOVE_RTC,
211 .flags = IORESOURCE_IRQ,
212 }
213};
214
215void __init dove_rtc_init(void) 102void __init dove_rtc_init(void)
216{ 103{
217 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); 104 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
218} 105}
219 106
220/***************************************************************************** 107/*****************************************************************************
221 * SATA 108 * SATA
222 ****************************************************************************/ 109 ****************************************************************************/
223static struct resource dove_sata_resources[] = {
224 {
225 .name = "sata base",
226 .start = DOVE_SATA_PHYS_BASE,
227 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .name = "sata irq",
231 .start = IRQ_DOVE_SATA,
232 .end = IRQ_DOVE_SATA,
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237static struct platform_device dove_sata = {
238 .name = "sata_mv",
239 .id = 0,
240 .dev = {
241 .coherent_dma_mask = DMA_BIT_MASK(32),
242 },
243 .num_resources = ARRAY_SIZE(dove_sata_resources),
244 .resource = dove_sata_resources,
245};
246
247void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 110void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
248{ 111{
249 sata_data->dram = &dove_mbus_dram_info; 112 orion_sata_init(sata_data, &dove_mbus_dram_info,
250 dove_sata.dev.platform_data = sata_data; 113 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
251 platform_device_register(&dove_sata); 114
252} 115}
253 116
254/***************************************************************************** 117/*****************************************************************************
255 * UART0 118 * UART0
256 ****************************************************************************/ 119 ****************************************************************************/
257static struct plat_serial8250_port dove_uart0_data[] = {
258 {
259 .mapbase = DOVE_UART0_PHYS_BASE,
260 .membase = (char *)DOVE_UART0_VIRT_BASE,
261 .irq = IRQ_DOVE_UART_0,
262 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
263 .iotype = UPIO_MEM,
264 .regshift = 2,
265 .uartclk = 0,
266 }, {
267 },
268};
269
270static struct resource dove_uart0_resources[] = {
271 {
272 .start = DOVE_UART0_PHYS_BASE,
273 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
274 .flags = IORESOURCE_MEM,
275 }, {
276 .start = IRQ_DOVE_UART_0,
277 .end = IRQ_DOVE_UART_0,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device dove_uart0 = {
283 .name = "serial8250",
284 .id = 0,
285 .dev = {
286 .platform_data = dove_uart0_data,
287 },
288 .resource = dove_uart0_resources,
289 .num_resources = ARRAY_SIZE(dove_uart0_resources),
290};
291
292void __init dove_uart0_init(void) 120void __init dove_uart0_init(void)
293{ 121{
294 platform_device_register(&dove_uart0); 122 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
123 IRQ_DOVE_UART_0, get_tclk());
295} 124}
296 125
297/***************************************************************************** 126/*****************************************************************************
298 * UART1 127 * UART1
299 ****************************************************************************/ 128 ****************************************************************************/
300static struct plat_serial8250_port dove_uart1_data[] = {
301 {
302 .mapbase = DOVE_UART1_PHYS_BASE,
303 .membase = (char *)DOVE_UART1_VIRT_BASE,
304 .irq = IRQ_DOVE_UART_1,
305 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
306 .iotype = UPIO_MEM,
307 .regshift = 2,
308 .uartclk = 0,
309 }, {
310 },
311};
312
313static struct resource dove_uart1_resources[] = {
314 {
315 .start = DOVE_UART1_PHYS_BASE,
316 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
317 .flags = IORESOURCE_MEM,
318 }, {
319 .start = IRQ_DOVE_UART_1,
320 .end = IRQ_DOVE_UART_1,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct platform_device dove_uart1 = {
326 .name = "serial8250",
327 .id = 1,
328 .dev = {
329 .platform_data = dove_uart1_data,
330 },
331 .resource = dove_uart1_resources,
332 .num_resources = ARRAY_SIZE(dove_uart1_resources),
333};
334
335void __init dove_uart1_init(void) 129void __init dove_uart1_init(void)
336{ 130{
337 platform_device_register(&dove_uart1); 131 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
132 IRQ_DOVE_UART_1, get_tclk());
338} 133}
339 134
340/***************************************************************************** 135/*****************************************************************************
341 * UART2 136 * UART2
342 ****************************************************************************/ 137 ****************************************************************************/
343static struct plat_serial8250_port dove_uart2_data[] = {
344 {
345 .mapbase = DOVE_UART2_PHYS_BASE,
346 .membase = (char *)DOVE_UART2_VIRT_BASE,
347 .irq = IRQ_DOVE_UART_2,
348 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
349 .iotype = UPIO_MEM,
350 .regshift = 2,
351 .uartclk = 0,
352 }, {
353 },
354};
355
356static struct resource dove_uart2_resources[] = {
357 {
358 .start = DOVE_UART2_PHYS_BASE,
359 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
360 .flags = IORESOURCE_MEM,
361 }, {
362 .start = IRQ_DOVE_UART_2,
363 .end = IRQ_DOVE_UART_2,
364 .flags = IORESOURCE_IRQ,
365 },
366};
367
368static struct platform_device dove_uart2 = {
369 .name = "serial8250",
370 .id = 2,
371 .dev = {
372 .platform_data = dove_uart2_data,
373 },
374 .resource = dove_uart2_resources,
375 .num_resources = ARRAY_SIZE(dove_uart2_resources),
376};
377
378void __init dove_uart2_init(void) 138void __init dove_uart2_init(void)
379{ 139{
380 platform_device_register(&dove_uart2); 140 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
141 IRQ_DOVE_UART_2, get_tclk());
381} 142}
382 143
383/***************************************************************************** 144/*****************************************************************************
384 * UART3 145 * UART3
385 ****************************************************************************/ 146 ****************************************************************************/
386static struct plat_serial8250_port dove_uart3_data[] = {
387 {
388 .mapbase = DOVE_UART3_PHYS_BASE,
389 .membase = (char *)DOVE_UART3_VIRT_BASE,
390 .irq = IRQ_DOVE_UART_3,
391 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
392 .iotype = UPIO_MEM,
393 .regshift = 2,
394 .uartclk = 0,
395 }, {
396 },
397};
398
399static struct resource dove_uart3_resources[] = {
400 {
401 .start = DOVE_UART3_PHYS_BASE,
402 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
403 .flags = IORESOURCE_MEM,
404 }, {
405 .start = IRQ_DOVE_UART_3,
406 .end = IRQ_DOVE_UART_3,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device dove_uart3 = {
412 .name = "serial8250",
413 .id = 3,
414 .dev = {
415 .platform_data = dove_uart3_data,
416 },
417 .resource = dove_uart3_resources,
418 .num_resources = ARRAY_SIZE(dove_uart3_resources),
419};
420
421void __init dove_uart3_init(void) 147void __init dove_uart3_init(void)
422{ 148{
423 platform_device_register(&dove_uart3); 149 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
150 IRQ_DOVE_UART_3, get_tclk());
424} 151}
425 152
426/***************************************************************************** 153/*****************************************************************************
427 * SPI0 154 * SPI
428 ****************************************************************************/ 155 ****************************************************************************/
429static struct orion_spi_info dove_spi0_data = {
430 .tclk = 0,
431};
432
433static struct resource dove_spi0_resources[] = {
434 {
435 .start = DOVE_SPI0_PHYS_BASE,
436 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
437 .flags = IORESOURCE_MEM,
438 }, {
439 .start = IRQ_DOVE_SPI0,
440 .end = IRQ_DOVE_SPI0,
441 .flags = IORESOURCE_IRQ,
442 },
443};
444
445static struct platform_device dove_spi0 = {
446 .name = "orion_spi",
447 .id = 0,
448 .resource = dove_spi0_resources,
449 .dev = {
450 .platform_data = &dove_spi0_data,
451 },
452 .num_resources = ARRAY_SIZE(dove_spi0_resources),
453};
454
455void __init dove_spi0_init(void) 156void __init dove_spi0_init(void)
456{ 157{
457 platform_device_register(&dove_spi0); 158 orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
458} 159}
459 160
460/*****************************************************************************
461 * SPI1
462 ****************************************************************************/
463static struct orion_spi_info dove_spi1_data = {
464 .tclk = 0,
465};
466
467static struct resource dove_spi1_resources[] = {
468 {
469 .start = DOVE_SPI1_PHYS_BASE,
470 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
471 .flags = IORESOURCE_MEM,
472 }, {
473 .start = IRQ_DOVE_SPI1,
474 .end = IRQ_DOVE_SPI1,
475 .flags = IORESOURCE_IRQ,
476 },
477};
478
479static struct platform_device dove_spi1 = {
480 .name = "orion_spi",
481 .id = 1,
482 .resource = dove_spi1_resources,
483 .dev = {
484 .platform_data = &dove_spi1_data,
485 },
486 .num_resources = ARRAY_SIZE(dove_spi1_resources),
487};
488
489void __init dove_spi1_init(void) 161void __init dove_spi1_init(void)
490{ 162{
491 platform_device_register(&dove_spi1); 163 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
492} 164}
493 165
494/***************************************************************************** 166/*****************************************************************************
495 * I2C 167 * I2C
496 ****************************************************************************/ 168 ****************************************************************************/
497static struct mv64xxx_i2c_pdata dove_i2c_data = {
498 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
499 .freq_n = 3,
500 .timeout = 1000, /* Default timeout of 1 second */
501};
502
503static struct resource dove_i2c_resources[] = {
504 {
505 .name = "i2c base",
506 .start = DOVE_I2C_PHYS_BASE,
507 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
508 .flags = IORESOURCE_MEM,
509 }, {
510 .name = "i2c irq",
511 .start = IRQ_DOVE_I2C,
512 .end = IRQ_DOVE_I2C,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device dove_i2c = {
518 .name = MV64XXX_I2C_CTLR_NAME,
519 .id = 0,
520 .num_resources = ARRAY_SIZE(dove_i2c_resources),
521 .resource = dove_i2c_resources,
522 .dev = {
523 .platform_data = &dove_i2c_data,
524 },
525};
526
527void __init dove_i2c_init(void) 169void __init dove_i2c_init(void)
528{ 170{
529 platform_device_register(&dove_i2c); 171 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
530} 172}
531 173
532/***************************************************************************** 174/*****************************************************************************
@@ -554,208 +196,22 @@ struct sys_timer dove_timer = {
554}; 196};
555 197
556/***************************************************************************** 198/*****************************************************************************
557 * XOR
558 ****************************************************************************/
559static struct mv_xor_platform_shared_data dove_xor_shared_data = {
560 .dram = &dove_mbus_dram_info,
561};
562
563/*****************************************************************************
564 * XOR 0 199 * XOR 0
565 ****************************************************************************/ 200 ****************************************************************************/
566static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
567
568static struct resource dove_xor0_shared_resources[] = {
569 {
570 .name = "xor 0 low",
571 .start = DOVE_XOR0_PHYS_BASE,
572 .end = DOVE_XOR0_PHYS_BASE + 0xff,
573 .flags = IORESOURCE_MEM,
574 }, {
575 .name = "xor 0 high",
576 .start = DOVE_XOR0_HIGH_PHYS_BASE,
577 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
578 .flags = IORESOURCE_MEM,
579 },
580};
581
582static struct platform_device dove_xor0_shared = {
583 .name = MV_XOR_SHARED_NAME,
584 .id = 0,
585 .dev = {
586 .platform_data = &dove_xor_shared_data,
587 },
588 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
589 .resource = dove_xor0_shared_resources,
590};
591
592static struct resource dove_xor00_resources[] = {
593 [0] = {
594 .start = IRQ_DOVE_XOR_00,
595 .end = IRQ_DOVE_XOR_00,
596 .flags = IORESOURCE_IRQ,
597 },
598};
599
600static struct mv_xor_platform_data dove_xor00_data = {
601 .shared = &dove_xor0_shared,
602 .hw_id = 0,
603 .pool_size = PAGE_SIZE,
604};
605
606static struct platform_device dove_xor00_channel = {
607 .name = MV_XOR_NAME,
608 .id = 0,
609 .num_resources = ARRAY_SIZE(dove_xor00_resources),
610 .resource = dove_xor00_resources,
611 .dev = {
612 .dma_mask = &dove_xor0_dmamask,
613 .coherent_dma_mask = DMA_BIT_MASK(64),
614 .platform_data = &dove_xor00_data,
615 },
616};
617
618static struct resource dove_xor01_resources[] = {
619 [0] = {
620 .start = IRQ_DOVE_XOR_01,
621 .end = IRQ_DOVE_XOR_01,
622 .flags = IORESOURCE_IRQ,
623 },
624};
625
626static struct mv_xor_platform_data dove_xor01_data = {
627 .shared = &dove_xor0_shared,
628 .hw_id = 1,
629 .pool_size = PAGE_SIZE,
630};
631
632static struct platform_device dove_xor01_channel = {
633 .name = MV_XOR_NAME,
634 .id = 1,
635 .num_resources = ARRAY_SIZE(dove_xor01_resources),
636 .resource = dove_xor01_resources,
637 .dev = {
638 .dma_mask = &dove_xor0_dmamask,
639 .coherent_dma_mask = DMA_BIT_MASK(64),
640 .platform_data = &dove_xor01_data,
641 },
642};
643
644void __init dove_xor0_init(void) 201void __init dove_xor0_init(void)
645{ 202{
646 platform_device_register(&dove_xor0_shared); 203 orion_xor0_init(&dove_mbus_dram_info,
647 204 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
648 /* 205 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
649 * two engines can't do memset simultaneously, this limitation
650 * satisfied by removing memset support from one of the engines.
651 */
652 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
653 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
654 platform_device_register(&dove_xor00_channel);
655
656 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
657 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
658 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
659 platform_device_register(&dove_xor01_channel);
660} 206}
661 207
662/***************************************************************************** 208/*****************************************************************************
663 * XOR 1 209 * XOR 1
664 ****************************************************************************/ 210 ****************************************************************************/
665static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
666
667static struct resource dove_xor1_shared_resources[] = {
668 {
669 .name = "xor 0 low",
670 .start = DOVE_XOR1_PHYS_BASE,
671 .end = DOVE_XOR1_PHYS_BASE + 0xff,
672 .flags = IORESOURCE_MEM,
673 }, {
674 .name = "xor 0 high",
675 .start = DOVE_XOR1_HIGH_PHYS_BASE,
676 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
677 .flags = IORESOURCE_MEM,
678 },
679};
680
681static struct platform_device dove_xor1_shared = {
682 .name = MV_XOR_SHARED_NAME,
683 .id = 1,
684 .dev = {
685 .platform_data = &dove_xor_shared_data,
686 },
687 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
688 .resource = dove_xor1_shared_resources,
689};
690
691static struct resource dove_xor10_resources[] = {
692 [0] = {
693 .start = IRQ_DOVE_XOR_10,
694 .end = IRQ_DOVE_XOR_10,
695 .flags = IORESOURCE_IRQ,
696 },
697};
698
699static struct mv_xor_platform_data dove_xor10_data = {
700 .shared = &dove_xor1_shared,
701 .hw_id = 0,
702 .pool_size = PAGE_SIZE,
703};
704
705static struct platform_device dove_xor10_channel = {
706 .name = MV_XOR_NAME,
707 .id = 2,
708 .num_resources = ARRAY_SIZE(dove_xor10_resources),
709 .resource = dove_xor10_resources,
710 .dev = {
711 .dma_mask = &dove_xor1_dmamask,
712 .coherent_dma_mask = DMA_BIT_MASK(64),
713 .platform_data = &dove_xor10_data,
714 },
715};
716
717static struct resource dove_xor11_resources[] = {
718 [0] = {
719 .start = IRQ_DOVE_XOR_11,
720 .end = IRQ_DOVE_XOR_11,
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct mv_xor_platform_data dove_xor11_data = {
726 .shared = &dove_xor1_shared,
727 .hw_id = 1,
728 .pool_size = PAGE_SIZE,
729};
730
731static struct platform_device dove_xor11_channel = {
732 .name = MV_XOR_NAME,
733 .id = 3,
734 .num_resources = ARRAY_SIZE(dove_xor11_resources),
735 .resource = dove_xor11_resources,
736 .dev = {
737 .dma_mask = &dove_xor1_dmamask,
738 .coherent_dma_mask = DMA_BIT_MASK(64),
739 .platform_data = &dove_xor11_data,
740 },
741};
742
743void __init dove_xor1_init(void) 211void __init dove_xor1_init(void)
744{ 212{
745 platform_device_register(&dove_xor1_shared); 213 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
746 214 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
747 /*
748 * two engines can't do memset simultaneously, this limitation
749 * satisfied by removing memset support from one of the engines.
750 */
751 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
752 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
753 platform_device_register(&dove_xor10_channel);
754
755 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
756 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
757 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
758 platform_device_register(&dove_xor11_channel);
759} 215}
760 216
761/***************************************************************************** 217/*****************************************************************************
@@ -833,14 +289,6 @@ void __init dove_init(void)
833#endif 289#endif
834 dove_setup_cpu_mbus(); 290 dove_setup_cpu_mbus();
835 291
836 dove_ge00_shared_data.t_clk = tclk;
837 dove_uart0_data[0].uartclk = tclk;
838 dove_uart1_data[0].uartclk = tclk;
839 dove_uart2_data[0].uartclk = tclk;
840 dove_uart3_data[0].uartclk = tclk;
841 dove_spi0_data.tclk = tclk;
842 dove_spi1_data.tclk = tclk;
843
844 /* internal devices that every board has */ 292 /* internal devices that every board has */
845 dove_rtc_init(); 293 dove_rtc_init();
846 dove_xor0_init(); 294 dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c76346904..51e0e411c9cb 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/io.h> 13#include <linux/io.h>
14 14#include <plat/mpp.h>
15#include <mach/dove.h> 15#include <mach/dove.h>
16
17#include "mpp.h" 16#include "mpp.h"
18 17
19#define MPP_NR_REGS 4
20#define MPP_CTRL(i) ((i) == 3 ? \
21 DOVE_MPP_CTRL4_VIRT_BASE : \
22 DOVE_MPP_VIRT_BASE + (i) * 4)
23#define PMU_SIG_REGS 2
24#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
25
26struct dove_mpp_grp { 18struct dove_mpp_grp {
27 int start; 19 int start;
28 int end; 20 int end;
29}; 21};
30 22
31static struct dove_mpp_grp dove_mpp_grp[] = { 23/* Map a group to a range of GPIO pins in that group */
24static const struct dove_mpp_grp dove_mpp_grp[] = {
32 [MPP_24_39] = { 25 [MPP_24_39] = {
33 .start = 24, 26 .start = 24,
34 .end = 39, 27 .end = 39,
@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
38 .end = 45, 31 .end = 45,
39 }, 32 },
40 [MPP_46_51] = { 33 [MPP_46_51] = {
41 .start = 40, 34 .start = 46,
42 .end = 45, 35 .end = 51,
43 }, 36 },
44 [MPP_58_61] = { 37 [MPP_58_61] = {
45 .start = 58, 38 .start = 58,
@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
51 }, 44 },
52}; 45};
53 46
47/* Enable gpio for a range of pins. mode should be a combination of
48 GPIO_OUTPUT_OK | GPIO_INPUT_OK */
54static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) 49static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
55{ 50{
56 int i; 51 int i;
@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
59 orion_gpio_set_valid(i, gpio_mode); 54 orion_gpio_set_valid(i, gpio_mode);
60} 55}
61 56
57/* Dump all the extra MPP registers. The platform code will dump the
58 registers for pins 0-23. */
62static void dove_mpp_dump_regs(void) 59static void dove_mpp_dump_regs(void)
63{ 60{
64#ifdef DEBUG 61 pr_debug("PMU_CTRL4_CTRL: %08x\n",
65 int i; 62 readl(DOVE_MPP_CTRL4_VIRT_BASE));
66 63
67 pr_debug("MPP_CTRL regs:"); 64 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
68 for (i = 0; i < MPP_NR_REGS; i++) 65 readl(DOVE_PMU_MPP_GENERAL_CTRL));
69 printk(" %08x", readl(MPP_CTRL(i)));
70 printk("\n");
71 66
72 pr_debug("PMU_SIG_CTRL regs:");
73 for (i = 0; i < PMU_SIG_REGS; i++)
74 printk(" %08x", readl(PMU_SIG_CTRL(i)));
75 printk("\n");
76
77 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
78 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
79#endif
80} 68}
81 69
82static void dove_mpp_cfg_nfc(int sel) 70static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
92 80
93static void dove_mpp_cfg_au1(int sel) 81static void dove_mpp_cfg_au1(int sel)
94{ 82{
95 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
96 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
97 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); 85 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
98 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); 86 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
128 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); 116 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
129} 117}
130 118
131static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) 119/* Configure the group registers, enabling GPIO if sel indicates the
132{ 120 pin is to be used for GPIO */
133 int start = dove_mpp_grp[num].start; 121static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
134 int end = dove_mpp_grp[num].end;
135 int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
136
137 *mpp_ctrl &= ~(0x1 << num);
138 *mpp_ctrl |= sel << num;
139
140 dove_mpp_gpio_mode(start, end, gpio_mode);
141}
142
143void __init dove_mpp_conf(unsigned int *mpp_list)
144{ 122{
145 u32 mpp_ctrl[MPP_NR_REGS]; 123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
146 u32 pmu_mpp_ctrl = 0; 124 int gpio_mode;
147 u32 pmu_sig_ctrl[PMU_SIG_REGS];
148 int i;
149
150 for (i = 0; i < MPP_NR_REGS; i++)
151 mpp_ctrl[i] = readl(MPP_CTRL(i));
152
153 for (i = 0; i < PMU_SIG_REGS; i++)
154 pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
155
156 pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
157 125
158 dove_mpp_dump_regs(); 126 for ( ; *mpp_grp_list; mpp_grp_list++) {
159 127 unsigned int num = MPP_NUM(*mpp_grp_list);
160 for ( ; *mpp_list != MPP_END; mpp_list++) { 128 unsigned int sel = MPP_SEL(*mpp_grp_list);
161 unsigned int num = MPP_NUM(*mpp_list);
162 unsigned int sel = MPP_SEL(*mpp_list);
163 int shift, gpio_mode;
164
165 if (num > MPP_MAX) {
166 pr_err("dove: invalid MPP number (%u)\n", num);
167 continue;
168 }
169
170 if (*mpp_list & MPP_NFC_MASK) {
171 dove_mpp_cfg_nfc(sel);
172 continue;
173 }
174 129
175 if (*mpp_list & MPP_AU1_MASK) { 130 if (num > MPP_GRP_MAX) {
176 dove_mpp_cfg_au1(sel); 131 pr_err("dove: invalid MPP GRP number (%u)\n", num);
177 continue; 132 continue;
178 } 133 }
179 134
180 if (*mpp_list & MPP_GRP_MASK) { 135 mpp_ctrl4 &= ~(0x1 << num);
181 dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); 136 mpp_ctrl4 |= sel << num;
182 continue;
183 }
184
185 shift = (num & 7) << 2;
186 if (*mpp_list & MPP_PMU_MASK) {
187 pmu_mpp_ctrl |= (0x1 << num);
188 pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
189 pmu_sig_ctrl[num / 8] |= 0xf << shift;
190 gpio_mode = 0;
191 } else {
192 mpp_ctrl[num / 8] &= ~(0xf << shift);
193 mpp_ctrl[num / 8] |= sel << shift;
194 gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
195 }
196 137
197 orion_gpio_set_valid(num, gpio_mode); 138 gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
139 dove_mpp_gpio_mode(dove_mpp_grp[num].start,
140 dove_mpp_grp[num].end, gpio_mode);
198 } 141 }
142 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
143}
199 144
200 for (i = 0; i < MPP_NR_REGS; i++) 145/* Configure the various MPP pins on Dove */
201 writel(mpp_ctrl[i], MPP_CTRL(i)); 146void __init dove_mpp_conf(unsigned int *mpp_list,
147 unsigned int *mpp_grp_list,
148 unsigned int grp_au1_52_57,
149 unsigned int grp_nfc_64_71)
150{
151 dove_mpp_dump_regs();
202 152
203 for (i = 0; i < PMU_SIG_REGS; i++) 153 /* Use platform code for pins 0-23 */
204 writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); 154 orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
205 155
206 writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); 156 dove_mpp_conf_grp(mpp_grp_list);
157 dove_mpp_cfg_au1(grp_au1_52_57);
158 dove_mpp_cfg_nfc(grp_nfc_64_71);
207 159
208 dove_mpp_dump_regs(); 160 dove_mpp_dump_regs();
209} 161}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b15..fbec7c52bfac 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
1#ifndef __ARCH_DOVE_MPP_CODED_H 1#ifndef __ARCH_DOVE_MPP_CODED_H
2#define __ARCH_DOVE_MPP_CODED_H 2#define __ARCH_DOVE_MPP_CODED_H
3 3
4#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ 4#define MPP(_num, _sel, _in, _out) ( \
5/* MPP/group number */ ((_num) & 0xff) | \ 5 /* MPP number */ ((_num) & 0xff) | \
6/* MPP select value */ (((_mode) & 0xf) << 8) | \ 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7/* MPP PMU */ ((!!(_pmu)) << 12) | \ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8/* group flag */ ((!!(_grp)) << 13) | \ 8 /* may be output signal */ ((!!(_out)) << 13))
9/* AU1 flag */ ((!!(_au1)) << 14) | \ 9
10/* NFCE flag */ ((!!(_nfc)) << 15)) 10#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
11 11#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
12#define MPP_MAX 71 12#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
13 13#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
14#define MPP_NUM(x) ((x) & 0xff) 14
15#define MPP_SEL(x) (((x) >> 8) & 0xf) 15#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
16 16#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
17#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) 17#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
18#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) 18#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
19#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) 19
20#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) 20#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
21 21#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
22#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) 22#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
23 23#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
24#define MPP_PMU_DRIVE_0 0x1 24#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
25#define MPP_PMU_DRIVE_1 0x2 25
26#define MPP_PMU_SDI 0x3 26#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
27#define MPP_PMU_CPU_PWRDWN 0x4 27#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
28#define MPP_PMU_STBY_PWRDWN 0x5 28#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
29#define MPP_PMU_CORE_PWR_GOOD 0x8 29#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
30#define MPP_PMU_BAT_FAULT 0xa 30#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
31#define MPP_PMU_EXT0_WU 0xb 31#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
32#define MPP_PMU_EXT1_WU 0xc 32
33#define MPP_PMU_EXT2_WU 0xd 33#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
34#define MPP_PMU_BLINK 0xe 34#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
35#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) 35#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
36 36#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
37#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) 37
38#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) 38#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
39#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) 39#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
40#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) 40#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
41 41#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
42#define MPP0_GPIO0 MPP_PIN(0, 0x0) 42
43#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) 43#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
44#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) 44#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
45#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) 45#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
46 46#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
47#define MPP1_GPIO1 MPP_PIN(1, 0x0) 47
48#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) 48#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
49#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) 49#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
50#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) 50#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
51 51#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
52#define MPP2_GPIO2 MPP_PIN(2, 0x0) 52
53#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) 53#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
54#define MPP2_UA2_TXD MPP_PIN(2, 0x2) 54#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
55#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) 55
56#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) 56#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
57 57#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
58#define MPP3_GPIO3 MPP_PIN(3, 0x0) 58
59#define MPP3_SATA_ACT MPP_PIN(3, 0x1) 59#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
60#define MPP3_UA2_RXD MPP_PIN(3, 0x2) 60#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
61#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) 61
62#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) 62#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
63#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) 63#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
64 64#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
65#define MPP4_GPIO4 MPP_PIN(4, 0x0) 65#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
66#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) 66#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
67#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) 67#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
68#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) 68
69 69#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
70#define MPP5_GPIO5 MPP_PIN(5, 0x0) 70#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
71#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) 71#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
72#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) 72#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
73#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) 73#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
74 74
75#define MPP6_GPIO6 MPP_PIN(6, 0x0) 75#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
76#define MPP6_UA3_TXD MPP_PIN(6, 0x2) 76#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
77#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) 77#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
78#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) 78#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
79 79#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
80#define MPP7_GPIO7 MPP_PIN(7, 0x0) 80
81#define MPP7_UA3_RXD MPP_PIN(7, 0x2) 81#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
82#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) 82#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
83#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) 83#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
84 84#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
85#define MPP8_GPIO8 MPP_PIN(8, 0x0) 85
86#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) 86#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
87 87#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
88#define MPP9_GPIO9 MPP_PIN(9, 0x0) 88#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
89#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) 89#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
90 90
91#define MPP10_GPIO10 MPP_PIN(10, 0x0) 91#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
92#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) 92#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
93 93#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
94#define MPP11_GPIO11 MPP_PIN(11, 0x0) 94#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
95#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) 95#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
96#define MPP11_SATA_ACT MPP_PIN(11, 0x2) 96
97#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) 97#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
98#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) 98#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
99#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) 99#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
100 100#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
101#define MPP12_GPIO12 MPP_PIN(12, 0x0) 101#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
102#define MPP12_SATA_ACT MPP_PIN(12, 0x1) 102#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
103#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) 103
104#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) 104#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
105#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) 105#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
106 106#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
107#define MPP13_GPIO13 MPP_PIN(13, 0x0) 107#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
108#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) 108#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
109#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) 109
110#define MPP13_SDIO1WP MPP_PIN(13, 0x4) 110#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
111#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) 111#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
112 112#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
113#define MPP14_GPIO14 MPP_PIN(14, 0x0) 113#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
114#define MPP14_UA2_TXD MPP_PIN(14, 0x2) 114
115#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) 115#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
116#define MPP14_SSP_RXD MPP_PIN(14, 0x5) 116#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
117 117#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
118#define MPP15_GPIO15 MPP_PIN(15, 0x0) 118#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
119#define MPP15_UA2_RXD MPP_PIN(15, 0x2) 119#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
120#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) 120#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
121#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) 121
122 122#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
123#define MPP16_GPIO16 MPP_PIN(16, 0x0) 123#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
124#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) 124#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
125#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) 125#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
126#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) 126#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
127#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) 127#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
128 128#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
129#define MPP17_GPIO17 MPP_PIN(17, 0x0) 129
130#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) 130#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
131#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) 131#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
132#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) 132#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
133#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) 133#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
134#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) 134#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
135 135#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
136#define MPP18_GPIO18 MPP_PIN(18, 0x0) 136#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
137#define MPP18_UA3_TXD MPP_PIN(18, 0x2) 137
138#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) 138#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
139#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) 139#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
140#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) 140#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
141 141#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
142#define MPP19_GPIO19 MPP_PIN(19, 0x0) 142#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
143#define MPP19_UA3_RXD MPP_PIN(19, 0x2) 143#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
144#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) 144
145#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) 145#define MPP_MAX 23
146 146
147#define MPP20_GPIO20 MPP_PIN(20, 0x0) 147#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
148#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
149#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
150#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
151#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
152#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
153
154#define MPP21_GPIO21 MPP_PIN(21, 0x0)
155#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
156#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
157#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
158#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
159#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
160#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
161
162#define MPP22_GPIO22 MPP_PIN(22, 0x0)
163#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
164#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
165#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
166#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
167#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
168#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
169
170#define MPP23_GPIO23 MPP_PIN(23, 0x0)
171#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
172#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
173#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
174#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
175#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
176 148
177/* for MPP groups _num is a group index */ 149/* for MPP groups _num is a group index */
178enum dove_mpp_grp_idx { 150enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
181 MPP_46_51 = 1, 153 MPP_46_51 = 1,
182 MPP_58_61 = 5, 154 MPP_58_61 = 5,
183 MPP_62_63 = 4, 155 MPP_62_63 = 4,
156 MPP_GRP_MAX = 5,
184}; 157};
185 158
186#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) 159#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
187#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) 160#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
188 161
189#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) 162#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
190#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) 163#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
191 164
192#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) 165#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
193#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) 166#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
194 167
195#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) 168#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
196#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) 169#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
197 170
198#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) 171#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
199#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) 172#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
200 173
201/* The MPP[64:71] control differs from other groups */ 174/* The MPP[64:71] control differs from other groups */
202#define MPP64_71_GPO MPP_GRP_NFC(0x1) 175#define MPP_GRP_NFC_64_71_GPO 0x1
203#define MPP64_71_NFC MPP_GRP_NFC(0x0) 176#define MPP_GRP_NFC_64_71_NFC 0x0
204 177
205/* 178/*
206 * The MPP[52:57] functionality is encoded by 4 bits in different 179 * The MPP[52:57] functionality is encoded by 4 bits in different
207 * registers. The _num field in this case encodes those bits in 180 * registers. The _num field in this case encodes those bits in
208 * correspodence with Table 135 of 88AP510 Functional specification 181 * correspodence with Table 135 of 88AP510 Functional specification
209 */ 182 */
210#define MPP52_57_AU1 MPP_GRP_AU1(0x0) 183#define MPP_GRP_AU1_52_57_AU1 0x0
211#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) 184#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
212#define MPP52_57_GPIO MPP_GRP_AU1(0xa) 185#define MPP_GRP_AU1_52_57_GPIO 0xa
213#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) 186#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
214#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) 187#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
215#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) 188#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
216#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) 189#define MPP_GRP_AU1_52_57_SSP_TW 0xf
217 190
218void dove_mpp_conf(unsigned int *mpp_list); 191void dove_mpp_conf(unsigned int *mpp_list,
192 unsigned int *mpp_grp_list,
193 unsigned int grp_au1_52_57,
194 unsigned int grp_nfc_64_71);
219 195
220#endif /* __ARCH_DOVE_MPP_CODED_H */ 196#endif /* __ARCH_DOVE_MPP_CODED_H */
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