3 files changed, 107 insertions, 89 deletions
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
 #include <mach/dove.h>
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0000)
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK    0x00000001
 #define  CPU_RESET              0x00000002
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define FIQ_MASK_LOW_OFF        0x0008
@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
-#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE + 0x011c)
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 #endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index c91e3004a47b..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
 */
 #define DOVE_CESA_PHYS_BASE             0xc8000000
-#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_VIRT_BASE             IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE                  SZ_1M
 #define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
@@ -38,15 +38,15 @@
 #define DOVE_BOOTROM_SIZE               SZ_128M
 #define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE       IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE            SZ_1M
 #define DOVE_SB_REGS_PHYS_BASE          0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE               SZ_8M
 #define DOVE_NB_REGS_PHYS_BASE          0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE          IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE               SZ_8M
 #define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
@@ -62,75 +62,75 @@
 */
 /* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x11000)
-#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
-#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
-#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
-#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
-#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
-#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
-#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
-#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
-#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x10600)
-#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x14600)
 /* North-South Bridge */
-#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
-#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
 /* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
 /* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
 /* USB */
-#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x50000)
-#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x51000)
 /* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60800)
-#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
 /* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60900)
-#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
 /* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x70000)
 /* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
 /* CAFE */
-#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
-#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
-#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
 /* SATA */
-#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
 /* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
-#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
 /* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
 /* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
-#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
 #define  DOVE_SD0_GPIO_SEL              (1 << 0)
 /* Power Management */
-#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
 #define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 /* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
 /* AC97 */
-#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
-#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
 /* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
-#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
-#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
 #define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
 #define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
 #define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
-#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
 #define  DOVE_SSP_ON_AU1                (1 << 0)
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
-#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 /* LCD Controller */
-#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x20000)
-#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
 /* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x40000)
 /* Video Engine */
-#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x400000)
 #endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
+#define  CLOCK_GATING_BIT_USB0          0
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
+#define  CLOCK_GATING_BIT_USB1          1
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
+#define  CLOCK_GATING_BIT_GBE           2
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
+#define  CLOCK_GATING_BIT_SATA          3
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
+#define  CLOCK_GATING_BIT_PCIE0         4
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
+#define  CLOCK_GATING_BIT_PCIE1         5
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
+#define  CLOCK_GATING_BIT_SDIO0         8
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
+#define  CLOCK_GATING_BIT_SDIO1         9
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
+#define  CLOCK_GATING_BIT_NAND          10
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
+#define  CLOCK_GATING_BIT_CAMERA        11
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
+#define  CLOCK_GATING_BIT_I2S0          12
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
+#define  CLOCK_GATING_BIT_I2S1          13
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
+#define  CLOCK_GATING_BIT_CRYPTO        15
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
+#define  CLOCK_GATING_BIT_AC97          21
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
+#define  CLOCK_GATING_BIT_PDMA          22
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
+#define  CLOCK_GATING_BIT_XOR0          23
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
+#define  CLOCK_GATING_BIT_XOR1          24
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)

diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h index f953bb54aa9d..99f259e8cf33 100644 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
13		13
14	#include <mach/dove.h>	14	#include <mach/dove.h>
15		15
16	#define CPU_CONFIG (BRIDGE_VIRT_BASE \| 0x0000)	16	#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
17		17
18	#define CPU_CONTROL (BRIDGE_VIRT_BASE \| 0x0104)	18	#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
19	#define CPU_CTRL_PCIE0_LINK 0x00000001	19	#define CPU_CTRL_PCIE0_LINK 0x00000001
20	#define CPU_RESET 0x00000002	20	#define CPU_RESET 0x00000002
21	#define CPU_CTRL_PCIE1_LINK 0x00000008	21	#define CPU_CTRL_PCIE1_LINK 0x00000008
22		22
23	#define RSTOUTn_MASK (BRIDGE_VIRT_BASE \| 0x0108)	23	#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
24	#define SOFT_RESET_OUT_EN 0x00000004	24	#define SOFT_RESET_OUT_EN 0x00000004
25		25
26	#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE \| 0x010c)	26	#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27	#define SOFT_RESET 0x00000001	27	#define SOFT_RESET 0x00000001
28		28
29	#define BRIDGE_INT_TIMER1_CLR (~0x0004)	29	#define BRIDGE_INT_TIMER1_CLR (~0x0004)
30		30
31	#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE \| 0x0200)	31	#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
32	#define IRQ_CAUSE_LOW_OFF 0x0000	32	#define IRQ_CAUSE_LOW_OFF 0x0000
33	#define IRQ_MASK_LOW_OFF 0x0004	33	#define IRQ_MASK_LOW_OFF 0x0004
34	#define FIQ_MASK_LOW_OFF 0x0008	34	#define FIQ_MASK_LOW_OFF 0x0008
@@ -47,9 +47,9 @@
47	#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)	47	#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
48	#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)	48	#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
49		49
50	#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE \| 0x011c)	50	#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
51		51
52	#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE \| 0x0300)	52	#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
53	#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE \| 0x0300)	53	#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
54		54
55	#endif	55	#endif


diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index c91e3004a47b..661725e3115a 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
25	*/	25	*/
26		26
27	#define DOVE_CESA_PHYS_BASE 0xc8000000	27	#define DOVE_CESA_PHYS_BASE 0xc8000000
28	#define DOVE_CESA_VIRT_BASE 0xfdb00000	28	#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
29	#define DOVE_CESA_SIZE SZ_1M	29	#define DOVE_CESA_SIZE SZ_1M
30		30
31	#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000	31	#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
@@ -38,15 +38,15 @@
38	#define DOVE_BOOTROM_SIZE SZ_128M	38	#define DOVE_BOOTROM_SIZE SZ_128M
39		39
40	#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000	40	#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41	#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000	41	#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
42	#define DOVE_SCRATCHPAD_SIZE SZ_1M	42	#define DOVE_SCRATCHPAD_SIZE SZ_1M
43		43
44	#define DOVE_SB_REGS_PHYS_BASE 0xf1000000	44	#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
45	#define DOVE_SB_REGS_VIRT_BASE 0xfde00000	45	#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
46	#define DOVE_SB_REGS_SIZE SZ_8M	46	#define DOVE_SB_REGS_SIZE SZ_8M
47		47
48	#define DOVE_NB_REGS_PHYS_BASE 0xf1800000	48	#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
49	#define DOVE_NB_REGS_VIRT_BASE 0xfe600000	49	#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
50	#define DOVE_NB_REGS_SIZE SZ_8M	50	#define DOVE_NB_REGS_SIZE SZ_8M
51		51
52	#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000	52	#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
@@ -62,75 +62,75 @@
62	*/	62	*/
63		63
64	/* SPI, I2C, UART */	64	/* SPI, I2C, UART */
65	#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x11000)	65	#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
66	#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x12000)	66	#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
67	#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x12000)	67	#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
68	#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x12100)	68	#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
69	#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x12100)	69	#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
70	#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x12200)	70	#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
71	#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x12200)	71	#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
72	#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x12300)	72	#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
73	#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x12300)	73	#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
74	#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x10600)	74	#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
75	#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x14600)	75	#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
76		76
77	/* North-South Bridge */	77	/* North-South Bridge */
78	#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x20000)	78	#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
79	#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x20000)	79	#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80		80
81	/* Cryptographic Engine */	81	/* Cryptographic Engine */
82	#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x30000)	82	#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
83		83
84	/* PCIe 0 */	84	/* PCIe 0 */
85	#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x40000)	85	#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
86		86
87	/* USB */	87	/* USB */
88	#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x50000)	88	#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
89	#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x51000)	89	#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
90		90
91	/* XOR 0 Engine */	91	/* XOR 0 Engine */
92	#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x60800)	92	#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
93	#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x60800)	93	#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
94	#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x60A00)	94	#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
95	#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x60A00)	95	#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
96		96
97	/* XOR 1 Engine */	97	/* XOR 1 Engine */
98	#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x60900)	98	#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
99	#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x60900)	99	#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
100	#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x60B00)	100	#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
101	#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x60B00)	101	#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
102		102
103	/* Gigabit Ethernet */	103	/* Gigabit Ethernet */
104	#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x70000)	104	#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
105		105
106	/* PCIe 1 */	106	/* PCIe 1 */
107	#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0x80000)	107	#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
108		108
109	/* CAFE */	109	/* CAFE */
110	#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x92000)	110	#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
111	#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x90000)	111	#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
112	#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x94000)	112	#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
113	#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0x98000)	113	#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
114		114
115	/* SATA */	115	/* SATA */
116	#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xa0000)	116	#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
117		117
118	/* I2S/SPDIF */	118	/* I2S/SPDIF */
119	#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xb0000)	119	#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
120	#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xb4000)	120	#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
121		121
122	/* NAND Flash Controller */	122	/* NAND Flash Controller */
123	#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xc0000)	123	#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
124		124
125	/* MPP, GPIO, Reset Sampling */	125	/* MPP, GPIO, Reset Sampling */
126	#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xd0200)	126	#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
127	#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)	127	#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
128	#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE \| 0x014)	128	#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
129	#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE \| 0x018)	129	#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
130	#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xd0400)	130	#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
131	#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xd0420)	131	#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
132	#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xe8400)	132	#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
133	#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xe803c)	133	#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
134	#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)	134	#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
135	#define DOVE_NAND_GPIO_EN (1 << 0)	135	#define DOVE_NAND_GPIO_EN (1 << 0)
136	#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)	136	#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
142	#define DOVE_SD0_GPIO_SEL (1 << 0)	142	#define DOVE_SD0_GPIO_SEL (1 << 0)
143		143
144	/* Power Management */	144	/* Power Management */
145	#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xd0000)	145	#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
146	#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)	146	#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
147		147
148	/* Real Time Clock */	148	/* Real Time Clock */
149	#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xd8500)	149	#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
150		150
151	/* AC97 */	151	/* AC97 */
152	#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xe0000)	152	#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
153	#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xe0000)	153	#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
154		154
155	/* Peripheral DMA */	155	/* Peripheral DMA */
156	#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xe4000)	156	#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
157	#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE \| 0xe4000)	157	#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
158		158
159	#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE \| 0xe802C)	159	#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
160	#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)	160	#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
161	#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE \| 0xe8030)	161	#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
162	#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)	162	#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
163	#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)	163	#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
164	#define DOVE_TWSI_OPTION3_GPIO (1 << 22)	164	#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
165	#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE \| 0xec000)	165	#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
166	#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE \| 0xe8034)	166	#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
167	#define DOVE_SSP_ON_AU1 (1 << 0)	167	#define DOVE_SSP_ON_AU1 (1 << 0)
168	#define DOVE_SSP_CLOCK_ENABLE (1 << 1)	168	#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169	#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)	169	#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170	/* Memory Controller */	170	/* Memory Controller */
171	#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE \| 0x00000)	171	#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
172		172
173	/* LCD Controller */	173	/* LCD Controller */
174	#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x10000)	174	#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
175	#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x20000)	175	#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
176	#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x10000)	176	#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
177	#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x30000)	177	#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
178		178
179	/* Graphic Engine */	179	/* Graphic Engine */
180	#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x40000)	180	#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
181		181
182	/* Video Engine */	182	/* Video Engine */
183	#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE \| 0x400000)	183	#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
184		184
185	#endif	185	#endif


diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h index 3ad9f946a9e8..7bcd0dfce4b1 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
13	#include <mach/irqs.h>	13	#include <mach/irqs.h>
14		14
15	#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)	15	#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16	#define CLOCK_GATING_USB0_MASK (1 << 0)	16	#define CLOCK_GATING_BIT_USB0 0
17	#define CLOCK_GATING_USB1_MASK (1 << 1)	17	#define CLOCK_GATING_BIT_USB1 1
18	#define CLOCK_GATING_GBE_MASK (1 << 2)	18	#define CLOCK_GATING_BIT_GBE 2
19	#define CLOCK_GATING_SATA_MASK (1 << 3)	19	#define CLOCK_GATING_BIT_SATA 3
20	#define CLOCK_GATING_PCIE0_MASK (1 << 4)	20	#define CLOCK_GATING_BIT_PCIE0 4
21	#define CLOCK_GATING_PCIE1_MASK (1 << 5)	21	#define CLOCK_GATING_BIT_PCIE1 5
22	#define CLOCK_GATING_SDIO0_MASK (1 << 8)	22	#define CLOCK_GATING_BIT_SDIO0 8
23	#define CLOCK_GATING_SDIO1_MASK (1 << 9)	23	#define CLOCK_GATING_BIT_SDIO1 9
24	#define CLOCK_GATING_NAND_MASK (1 << 10)	24	#define CLOCK_GATING_BIT_NAND 10
25	#define CLOCK_GATING_CAMERA_MASK (1 << 11)	25	#define CLOCK_GATING_BIT_CAMERA 11
26	#define CLOCK_GATING_I2S0_MASK (1 << 12)	26	#define CLOCK_GATING_BIT_I2S0 12
27	#define CLOCK_GATING_I2S1_MASK (1 << 13)	27	#define CLOCK_GATING_BIT_I2S1 13
28	#define CLOCK_GATING_CRYPTO_MASK (1 << 15)	28	#define CLOCK_GATING_BIT_CRYPTO 15
29	#define CLOCK_GATING_AC97_MASK (1 << 21)	29	#define CLOCK_GATING_BIT_AC97 21
30	#define CLOCK_GATING_PDMA_MASK (1 << 22)	30	#define CLOCK_GATING_BIT_PDMA 22
31	#define CLOCK_GATING_XOR0_MASK (1 << 23)	31	#define CLOCK_GATING_BIT_XOR0 23
32	#define CLOCK_GATING_XOR1_MASK (1 << 24)	32	#define CLOCK_GATING_BIT_XOR1 24
33	#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)	33	#define CLOCK_GATING_BIT_GIGA_PHY 30
		34	#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
		35	#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
		36	#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
		37	#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
		38	#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
		39	#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
		40	#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
		41	#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
		42	#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
		43	#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
		44	#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
		45	#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
		46	#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
		47	#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
		48	#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
		49	#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
		50	#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
		51	#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
34		52
35	#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)	53	#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
36	#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)	54	#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)