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-rw-r--r--arch/arm/mach-dove/common.c197
1 files changed, 5 insertions, 192 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e3e043c0004c..6703bf3120b6 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -30,7 +30,6 @@
30#include <mach/bridge-regs.h> 30#include <mach/bridge-regs.h>
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32#include <linux/irq.h> 32#include <linux/irq.h>
33#include <plat/mv_xor.h>
34#include <plat/ehci-orion.h> 33#include <plat/ehci-orion.h>
35#include <plat/time.h> 34#include <plat/time.h>
36#include <plat/common.h> 35#include <plat/common.h>
@@ -278,208 +277,22 @@ struct sys_timer dove_timer = {
278}; 277};
279 278
280/***************************************************************************** 279/*****************************************************************************
281 * XOR
282 ****************************************************************************/
283static struct mv_xor_platform_shared_data dove_xor_shared_data = {
284 .dram = &dove_mbus_dram_info,
285};
286
287/*****************************************************************************
288 * XOR 0 280 * XOR 0
289 ****************************************************************************/ 281 ****************************************************************************/
290static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
291
292static struct resource dove_xor0_shared_resources[] = {
293 {
294 .name = "xor 0 low",
295 .start = DOVE_XOR0_PHYS_BASE,
296 .end = DOVE_XOR0_PHYS_BASE + 0xff,
297 .flags = IORESOURCE_MEM,
298 }, {
299 .name = "xor 0 high",
300 .start = DOVE_XOR0_HIGH_PHYS_BASE,
301 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
302 .flags = IORESOURCE_MEM,
303 },
304};
305
306static struct platform_device dove_xor0_shared = {
307 .name = MV_XOR_SHARED_NAME,
308 .id = 0,
309 .dev = {
310 .platform_data = &dove_xor_shared_data,
311 },
312 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
313 .resource = dove_xor0_shared_resources,
314};
315
316static struct resource dove_xor00_resources[] = {
317 [0] = {
318 .start = IRQ_DOVE_XOR_00,
319 .end = IRQ_DOVE_XOR_00,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct mv_xor_platform_data dove_xor00_data = {
325 .shared = &dove_xor0_shared,
326 .hw_id = 0,
327 .pool_size = PAGE_SIZE,
328};
329
330static struct platform_device dove_xor00_channel = {
331 .name = MV_XOR_NAME,
332 .id = 0,
333 .num_resources = ARRAY_SIZE(dove_xor00_resources),
334 .resource = dove_xor00_resources,
335 .dev = {
336 .dma_mask = &dove_xor0_dmamask,
337 .coherent_dma_mask = DMA_BIT_MASK(64),
338 .platform_data = &dove_xor00_data,
339 },
340};
341
342static struct resource dove_xor01_resources[] = {
343 [0] = {
344 .start = IRQ_DOVE_XOR_01,
345 .end = IRQ_DOVE_XOR_01,
346 .flags = IORESOURCE_IRQ,
347 },
348};
349
350static struct mv_xor_platform_data dove_xor01_data = {
351 .shared = &dove_xor0_shared,
352 .hw_id = 1,
353 .pool_size = PAGE_SIZE,
354};
355
356static struct platform_device dove_xor01_channel = {
357 .name = MV_XOR_NAME,
358 .id = 1,
359 .num_resources = ARRAY_SIZE(dove_xor01_resources),
360 .resource = dove_xor01_resources,
361 .dev = {
362 .dma_mask = &dove_xor0_dmamask,
363 .coherent_dma_mask = DMA_BIT_MASK(64),
364 .platform_data = &dove_xor01_data,
365 },
366};
367
368void __init dove_xor0_init(void) 282void __init dove_xor0_init(void)
369{ 283{
370 platform_device_register(&dove_xor0_shared); 284 orion_xor0_init(&dove_mbus_dram_info,
371 285 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
372 /* 286 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
373 * two engines can't do memset simultaneously, this limitation
374 * satisfied by removing memset support from one of the engines.
375 */
376 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
377 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
378 platform_device_register(&dove_xor00_channel);
379
380 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
381 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
382 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
383 platform_device_register(&dove_xor01_channel);
384} 287}
385 288
386/***************************************************************************** 289/*****************************************************************************
387 * XOR 1 290 * XOR 1
388 ****************************************************************************/ 291 ****************************************************************************/
389static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
390
391static struct resource dove_xor1_shared_resources[] = {
392 {
393 .name = "xor 0 low",
394 .start = DOVE_XOR1_PHYS_BASE,
395 .end = DOVE_XOR1_PHYS_BASE + 0xff,
396 .flags = IORESOURCE_MEM,
397 }, {
398 .name = "xor 0 high",
399 .start = DOVE_XOR1_HIGH_PHYS_BASE,
400 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
401 .flags = IORESOURCE_MEM,
402 },
403};
404
405static struct platform_device dove_xor1_shared = {
406 .name = MV_XOR_SHARED_NAME,
407 .id = 1,
408 .dev = {
409 .platform_data = &dove_xor_shared_data,
410 },
411 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
412 .resource = dove_xor1_shared_resources,
413};
414
415static struct resource dove_xor10_resources[] = {
416 [0] = {
417 .start = IRQ_DOVE_XOR_10,
418 .end = IRQ_DOVE_XOR_10,
419 .flags = IORESOURCE_IRQ,
420 },
421};
422
423static struct mv_xor_platform_data dove_xor10_data = {
424 .shared = &dove_xor1_shared,
425 .hw_id = 0,
426 .pool_size = PAGE_SIZE,
427};
428
429static struct platform_device dove_xor10_channel = {
430 .name = MV_XOR_NAME,
431 .id = 2,
432 .num_resources = ARRAY_SIZE(dove_xor10_resources),
433 .resource = dove_xor10_resources,
434 .dev = {
435 .dma_mask = &dove_xor1_dmamask,
436 .coherent_dma_mask = DMA_BIT_MASK(64),
437 .platform_data = &dove_xor10_data,
438 },
439};
440
441static struct resource dove_xor11_resources[] = {
442 [0] = {
443 .start = IRQ_DOVE_XOR_11,
444 .end = IRQ_DOVE_XOR_11,
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct mv_xor_platform_data dove_xor11_data = {
450 .shared = &dove_xor1_shared,
451 .hw_id = 1,
452 .pool_size = PAGE_SIZE,
453};
454
455static struct platform_device dove_xor11_channel = {
456 .name = MV_XOR_NAME,
457 .id = 3,
458 .num_resources = ARRAY_SIZE(dove_xor11_resources),
459 .resource = dove_xor11_resources,
460 .dev = {
461 .dma_mask = &dove_xor1_dmamask,
462 .coherent_dma_mask = DMA_BIT_MASK(64),
463 .platform_data = &dove_xor11_data,
464 },
465};
466
467void __init dove_xor1_init(void) 292void __init dove_xor1_init(void)
468{ 293{
469 platform_device_register(&dove_xor1_shared); 294 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
470 295 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
471 /*
472 * two engines can't do memset simultaneously, this limitation
473 * satisfied by removing memset support from one of the engines.
474 */
475 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
476 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
477 platform_device_register(&dove_xor10_channel);
478
479 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
480 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
481 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
482 platform_device_register(&dove_xor11_channel);
483} 296}
484 297
485/***************************************************************************** 298/*****************************************************************************
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