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-rw-r--r--arch/arm/mach-dove/common.c777
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diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
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1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/serial_8250.h>
17#include <linux/clk.h>
18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h>
23#include <linux/gpio.h>
24#include <asm/page.h>
25#include <asm/setup.h>
26#include <asm/timex.h>
27#include <asm/mach/map.h>
28#include <asm/mach/time.h>
29#include <asm/mach/pci.h>
30#include <mach/dove.h>
31#include <mach/bridge-regs.h>
32#include <asm/mach/arch.h>
33#include <linux/irq.h>
34#include <plat/mv_xor.h>
35#include <plat/ehci-orion.h>
36#include <plat/time.h>
37#include "common.h"
38
39/*****************************************************************************
40 * I/O Address Mapping
41 ****************************************************************************/
42static struct map_desc dove_io_desc[] __initdata = {
43 {
44 .virtual = DOVE_SB_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
46 .length = DOVE_SB_REGS_SIZE,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = DOVE_NB_REGS_VIRT_BASE,
50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
51 .length = DOVE_NB_REGS_SIZE,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
55 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
56 .length = DOVE_PCIE0_IO_SIZE,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
60 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
61 .length = DOVE_PCIE1_IO_SIZE,
62 .type = MT_DEVICE,
63 },
64};
65
66void __init dove_map_io(void)
67{
68 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
69}
70
71/*****************************************************************************
72 * EHCI
73 ****************************************************************************/
74static struct orion_ehci_data dove_ehci_data = {
75 .dram = &dove_mbus_dram_info,
76 .phy_version = EHCI_PHY_NA,
77};
78
79static u64 ehci_dmamask = DMA_BIT_MASK(32);
80
81/*****************************************************************************
82 * EHCI0
83 ****************************************************************************/
84static struct resource dove_ehci0_resources[] = {
85 {
86 .start = DOVE_USB0_PHYS_BASE,
87 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = IRQ_DOVE_USB0,
91 .end = IRQ_DOVE_USB0,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device dove_ehci0 = {
97 .name = "orion-ehci",
98 .id = 0,
99 .dev = {
100 .dma_mask = &ehci_dmamask,
101 .coherent_dma_mask = DMA_BIT_MASK(32),
102 .platform_data = &dove_ehci_data,
103 },
104 .resource = dove_ehci0_resources,
105 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
106};
107
108void __init dove_ehci0_init(void)
109{
110 platform_device_register(&dove_ehci0);
111}
112
113/*****************************************************************************
114 * EHCI1
115 ****************************************************************************/
116static struct resource dove_ehci1_resources[] = {
117 {
118 .start = DOVE_USB1_PHYS_BASE,
119 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
120 .flags = IORESOURCE_MEM,
121 }, {
122 .start = IRQ_DOVE_USB1,
123 .end = IRQ_DOVE_USB1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct platform_device dove_ehci1 = {
129 .name = "orion-ehci",
130 .id = 1,
131 .dev = {
132 .dma_mask = &ehci_dmamask,
133 .coherent_dma_mask = DMA_BIT_MASK(32),
134 .platform_data = &dove_ehci_data,
135 },
136 .resource = dove_ehci1_resources,
137 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
138};
139
140void __init dove_ehci1_init(void)
141{
142 platform_device_register(&dove_ehci1);
143}
144
145/*****************************************************************************
146 * GE00
147 ****************************************************************************/
148struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
149 .t_clk = 0,
150 .dram = &dove_mbus_dram_info,
151};
152
153static struct resource dove_ge00_shared_resources[] = {
154 {
155 .name = "ge00 base",
156 .start = DOVE_GE00_PHYS_BASE + 0x2000,
157 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
158 .flags = IORESOURCE_MEM,
159 },
160};
161
162static struct platform_device dove_ge00_shared = {
163 .name = MV643XX_ETH_SHARED_NAME,
164 .id = 0,
165 .dev = {
166 .platform_data = &dove_ge00_shared_data,
167 },
168 .num_resources = 1,
169 .resource = dove_ge00_shared_resources,
170};
171
172static struct resource dove_ge00_resources[] = {
173 {
174 .name = "ge00 irq",
175 .start = IRQ_DOVE_GE00_SUM,
176 .end = IRQ_DOVE_GE00_SUM,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device dove_ge00 = {
182 .name = MV643XX_ETH_NAME,
183 .id = 0,
184 .num_resources = 1,
185 .resource = dove_ge00_resources,
186 .dev = {
187 .coherent_dma_mask = 0xffffffff,
188 },
189};
190
191void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
192{
193 eth_data->shared = &dove_ge00_shared;
194 dove_ge00.dev.platform_data = eth_data;
195
196 platform_device_register(&dove_ge00_shared);
197 platform_device_register(&dove_ge00);
198}
199
200/*****************************************************************************
201 * SoC RTC
202 ****************************************************************************/
203static struct resource dove_rtc_resource[] = {
204 {
205 .start = DOVE_RTC_PHYS_BASE,
206 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
207 .flags = IORESOURCE_MEM,
208 }, {
209 .start = IRQ_DOVE_RTC,
210 .flags = IORESOURCE_IRQ,
211 }
212};
213
214void __init dove_rtc_init(void)
215{
216 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
217}
218
219/*****************************************************************************
220 * SATA
221 ****************************************************************************/
222static struct resource dove_sata_resources[] = {
223 {
224 .name = "sata base",
225 .start = DOVE_SATA_PHYS_BASE,
226 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
227 .flags = IORESOURCE_MEM,
228 }, {
229 .name = "sata irq",
230 .start = IRQ_DOVE_SATA,
231 .end = IRQ_DOVE_SATA,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct platform_device dove_sata = {
237 .name = "sata_mv",
238 .id = 0,
239 .dev = {
240 .coherent_dma_mask = DMA_BIT_MASK(32),
241 },
242 .num_resources = ARRAY_SIZE(dove_sata_resources),
243 .resource = dove_sata_resources,
244};
245
246void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
247{
248 sata_data->dram = &dove_mbus_dram_info;
249 dove_sata.dev.platform_data = sata_data;
250 platform_device_register(&dove_sata);
251}
252
253/*****************************************************************************
254 * UART0
255 ****************************************************************************/
256static struct plat_serial8250_port dove_uart0_data[] = {
257 {
258 .mapbase = DOVE_UART0_PHYS_BASE,
259 .membase = (char *)DOVE_UART0_VIRT_BASE,
260 .irq = IRQ_DOVE_UART_0,
261 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
262 .iotype = UPIO_MEM,
263 .regshift = 2,
264 .uartclk = 0,
265 }, {
266 },
267};
268
269static struct resource dove_uart0_resources[] = {
270 {
271 .start = DOVE_UART0_PHYS_BASE,
272 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
273 .flags = IORESOURCE_MEM,
274 }, {
275 .start = IRQ_DOVE_UART_0,
276 .end = IRQ_DOVE_UART_0,
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct platform_device dove_uart0 = {
282 .name = "serial8250",
283 .id = 0,
284 .dev = {
285 .platform_data = dove_uart0_data,
286 },
287 .resource = dove_uart0_resources,
288 .num_resources = ARRAY_SIZE(dove_uart0_resources),
289};
290
291void __init dove_uart0_init(void)
292{
293 platform_device_register(&dove_uart0);
294}
295
296/*****************************************************************************
297 * UART1
298 ****************************************************************************/
299static struct plat_serial8250_port dove_uart1_data[] = {
300 {
301 .mapbase = DOVE_UART1_PHYS_BASE,
302 .membase = (char *)DOVE_UART1_VIRT_BASE,
303 .irq = IRQ_DOVE_UART_1,
304 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
305 .iotype = UPIO_MEM,
306 .regshift = 2,
307 .uartclk = 0,
308 }, {
309 },
310};
311
312static struct resource dove_uart1_resources[] = {
313 {
314 .start = DOVE_UART1_PHYS_BASE,
315 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
316 .flags = IORESOURCE_MEM,
317 }, {
318 .start = IRQ_DOVE_UART_1,
319 .end = IRQ_DOVE_UART_1,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct platform_device dove_uart1 = {
325 .name = "serial8250",
326 .id = 1,
327 .dev = {
328 .platform_data = dove_uart1_data,
329 },
330 .resource = dove_uart1_resources,
331 .num_resources = ARRAY_SIZE(dove_uart1_resources),
332};
333
334void __init dove_uart1_init(void)
335{
336 platform_device_register(&dove_uart1);
337}
338
339/*****************************************************************************
340 * UART2
341 ****************************************************************************/
342static struct plat_serial8250_port dove_uart2_data[] = {
343 {
344 .mapbase = DOVE_UART2_PHYS_BASE,
345 .membase = (char *)DOVE_UART2_VIRT_BASE,
346 .irq = IRQ_DOVE_UART_2,
347 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
348 .iotype = UPIO_MEM,
349 .regshift = 2,
350 .uartclk = 0,
351 }, {
352 },
353};
354
355static struct resource dove_uart2_resources[] = {
356 {
357 .start = DOVE_UART2_PHYS_BASE,
358 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
359 .flags = IORESOURCE_MEM,
360 }, {
361 .start = IRQ_DOVE_UART_2,
362 .end = IRQ_DOVE_UART_2,
363 .flags = IORESOURCE_IRQ,
364 },
365};
366
367static struct platform_device dove_uart2 = {
368 .name = "serial8250",
369 .id = 2,
370 .dev = {
371 .platform_data = dove_uart2_data,
372 },
373 .resource = dove_uart2_resources,
374 .num_resources = ARRAY_SIZE(dove_uart2_resources),
375};
376
377void __init dove_uart2_init(void)
378{
379 platform_device_register(&dove_uart2);
380}
381
382/*****************************************************************************
383 * UART3
384 ****************************************************************************/
385static struct plat_serial8250_port dove_uart3_data[] = {
386 {
387 .mapbase = DOVE_UART3_PHYS_BASE,
388 .membase = (char *)DOVE_UART3_VIRT_BASE,
389 .irq = IRQ_DOVE_UART_3,
390 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
391 .iotype = UPIO_MEM,
392 .regshift = 2,
393 .uartclk = 0,
394 }, {
395 },
396};
397
398static struct resource dove_uart3_resources[] = {
399 {
400 .start = DOVE_UART3_PHYS_BASE,
401 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
402 .flags = IORESOURCE_MEM,
403 }, {
404 .start = IRQ_DOVE_UART_3,
405 .end = IRQ_DOVE_UART_3,
406 .flags = IORESOURCE_IRQ,
407 },
408};
409
410static struct platform_device dove_uart3 = {
411 .name = "serial8250",
412 .id = 3,
413 .dev = {
414 .platform_data = dove_uart3_data,
415 },
416 .resource = dove_uart3_resources,
417 .num_resources = ARRAY_SIZE(dove_uart3_resources),
418};
419
420void __init dove_uart3_init(void)
421{
422 platform_device_register(&dove_uart3);
423}
424
425/*****************************************************************************
426 * SPI0
427 ****************************************************************************/
428static struct orion_spi_info dove_spi0_data = {
429 .tclk = 0,
430};
431
432static struct resource dove_spi0_resources[] = {
433 {
434 .start = DOVE_SPI0_PHYS_BASE,
435 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
436 .flags = IORESOURCE_MEM,
437 }, {
438 .start = IRQ_DOVE_SPI0,
439 .end = IRQ_DOVE_SPI0,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device dove_spi0 = {
445 .name = "orion_spi",
446 .id = 0,
447 .resource = dove_spi0_resources,
448 .dev = {
449 .platform_data = &dove_spi0_data,
450 },
451 .num_resources = ARRAY_SIZE(dove_spi0_resources),
452};
453
454void __init dove_spi0_init(void)
455{
456 platform_device_register(&dove_spi0);
457}
458
459/*****************************************************************************
460 * SPI1
461 ****************************************************************************/
462static struct orion_spi_info dove_spi1_data = {
463 .tclk = 0,
464};
465
466static struct resource dove_spi1_resources[] = {
467 {
468 .start = DOVE_SPI1_PHYS_BASE,
469 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
470 .flags = IORESOURCE_MEM,
471 }, {
472 .start = IRQ_DOVE_SPI1,
473 .end = IRQ_DOVE_SPI1,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct platform_device dove_spi1 = {
479 .name = "orion_spi",
480 .id = 1,
481 .resource = dove_spi1_resources,
482 .dev = {
483 .platform_data = &dove_spi1_data,
484 },
485 .num_resources = ARRAY_SIZE(dove_spi1_resources),
486};
487
488void __init dove_spi1_init(void)
489{
490 platform_device_register(&dove_spi1);
491}
492
493/*****************************************************************************
494 * I2C
495 ****************************************************************************/
496static struct mv64xxx_i2c_pdata dove_i2c_data = {
497 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
498 .freq_n = 3,
499 .timeout = 1000, /* Default timeout of 1 second */
500};
501
502static struct resource dove_i2c_resources[] = {
503 {
504 .name = "i2c base",
505 .start = DOVE_I2C_PHYS_BASE,
506 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
507 .flags = IORESOURCE_MEM,
508 }, {
509 .name = "i2c irq",
510 .start = IRQ_DOVE_I2C,
511 .end = IRQ_DOVE_I2C,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516static struct platform_device dove_i2c = {
517 .name = MV64XXX_I2C_CTLR_NAME,
518 .id = 0,
519 .num_resources = ARRAY_SIZE(dove_i2c_resources),
520 .resource = dove_i2c_resources,
521 .dev = {
522 .platform_data = &dove_i2c_data,
523 },
524};
525
526void __init dove_i2c_init(void)
527{
528 platform_device_register(&dove_i2c);
529}
530
531/*****************************************************************************
532 * Time handling
533 ****************************************************************************/
534static int get_tclk(void)
535{
536 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
537 return 166666667;
538}
539
540static void dove_timer_init(void)
541{
542 orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
543}
544
545struct sys_timer dove_timer = {
546 .init = dove_timer_init,
547};
548
549/*****************************************************************************
550 * XOR
551 ****************************************************************************/
552static struct mv_xor_platform_shared_data dove_xor_shared_data = {
553 .dram = &dove_mbus_dram_info,
554};
555
556/*****************************************************************************
557 * XOR 0
558 ****************************************************************************/
559static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
560
561static struct resource dove_xor0_shared_resources[] = {
562 {
563 .name = "xor 0 low",
564 .start = DOVE_XOR0_PHYS_BASE,
565 .end = DOVE_XOR0_PHYS_BASE + 0xff,
566 .flags = IORESOURCE_MEM,
567 }, {
568 .name = "xor 0 high",
569 .start = DOVE_XOR0_HIGH_PHYS_BASE,
570 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
571 .flags = IORESOURCE_MEM,
572 },
573};
574
575static struct platform_device dove_xor0_shared = {
576 .name = MV_XOR_SHARED_NAME,
577 .id = 0,
578 .dev = {
579 .platform_data = &dove_xor_shared_data,
580 },
581 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
582 .resource = dove_xor0_shared_resources,
583};
584
585static struct resource dove_xor00_resources[] = {
586 [0] = {
587 .start = IRQ_DOVE_XOR_00,
588 .end = IRQ_DOVE_XOR_00,
589 .flags = IORESOURCE_IRQ,
590 },
591};
592
593static struct mv_xor_platform_data dove_xor00_data = {
594 .shared = &dove_xor0_shared,
595 .hw_id = 0,
596 .pool_size = PAGE_SIZE,
597};
598
599static struct platform_device dove_xor00_channel = {
600 .name = MV_XOR_NAME,
601 .id = 0,
602 .num_resources = ARRAY_SIZE(dove_xor00_resources),
603 .resource = dove_xor00_resources,
604 .dev = {
605 .dma_mask = &dove_xor0_dmamask,
606 .coherent_dma_mask = DMA_BIT_MASK(64),
607 .platform_data = (void *)&dove_xor00_data,
608 },
609};
610
611static struct resource dove_xor01_resources[] = {
612 [0] = {
613 .start = IRQ_DOVE_XOR_01,
614 .end = IRQ_DOVE_XOR_01,
615 .flags = IORESOURCE_IRQ,
616 },
617};
618
619static struct mv_xor_platform_data dove_xor01_data = {
620 .shared = &dove_xor0_shared,
621 .hw_id = 1,
622 .pool_size = PAGE_SIZE,
623};
624
625static struct platform_device dove_xor01_channel = {
626 .name = MV_XOR_NAME,
627 .id = 1,
628 .num_resources = ARRAY_SIZE(dove_xor01_resources),
629 .resource = dove_xor01_resources,
630 .dev = {
631 .dma_mask = &dove_xor0_dmamask,
632 .coherent_dma_mask = DMA_BIT_MASK(64),
633 .platform_data = (void *)&dove_xor01_data,
634 },
635};
636
637void __init dove_xor0_init(void)
638{
639 platform_device_register(&dove_xor0_shared);
640
641 /*
642 * two engines can't do memset simultaneously, this limitation
643 * satisfied by removing memset support from one of the engines.
644 */
645 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
646 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
647 platform_device_register(&dove_xor00_channel);
648
649 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
650 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
651 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
652 platform_device_register(&dove_xor01_channel);
653}
654
655/*****************************************************************************
656 * XOR 1
657 ****************************************************************************/
658static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
659
660static struct resource dove_xor1_shared_resources[] = {
661 {
662 .name = "xor 0 low",
663 .start = DOVE_XOR1_PHYS_BASE,
664 .end = DOVE_XOR1_PHYS_BASE + 0xff,
665 .flags = IORESOURCE_MEM,
666 }, {
667 .name = "xor 0 high",
668 .start = DOVE_XOR1_HIGH_PHYS_BASE,
669 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
670 .flags = IORESOURCE_MEM,
671 },
672};
673
674static struct platform_device dove_xor1_shared = {
675 .name = MV_XOR_SHARED_NAME,
676 .id = 1,
677 .dev = {
678 .platform_data = &dove_xor_shared_data,
679 },
680 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
681 .resource = dove_xor1_shared_resources,
682};
683
684static struct resource dove_xor10_resources[] = {
685 [0] = {
686 .start = IRQ_DOVE_XOR_10,
687 .end = IRQ_DOVE_XOR_10,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692static struct mv_xor_platform_data dove_xor10_data = {
693 .shared = &dove_xor1_shared,
694 .hw_id = 0,
695 .pool_size = PAGE_SIZE,
696};
697
698static struct platform_device dove_xor10_channel = {
699 .name = MV_XOR_NAME,
700 .id = 2,
701 .num_resources = ARRAY_SIZE(dove_xor10_resources),
702 .resource = dove_xor10_resources,
703 .dev = {
704 .dma_mask = &dove_xor1_dmamask,
705 .coherent_dma_mask = DMA_BIT_MASK(64),
706 .platform_data = (void *)&dove_xor10_data,
707 },
708};
709
710static struct resource dove_xor11_resources[] = {
711 [0] = {
712 .start = IRQ_DOVE_XOR_11,
713 .end = IRQ_DOVE_XOR_11,
714 .flags = IORESOURCE_IRQ,
715 },
716};
717
718static struct mv_xor_platform_data dove_xor11_data = {
719 .shared = &dove_xor1_shared,
720 .hw_id = 1,
721 .pool_size = PAGE_SIZE,
722};
723
724static struct platform_device dove_xor11_channel = {
725 .name = MV_XOR_NAME,
726 .id = 3,
727 .num_resources = ARRAY_SIZE(dove_xor11_resources),
728 .resource = dove_xor11_resources,
729 .dev = {
730 .dma_mask = &dove_xor1_dmamask,
731 .coherent_dma_mask = DMA_BIT_MASK(64),
732 .platform_data = (void *)&dove_xor11_data,
733 },
734};
735
736void __init dove_xor1_init(void)
737{
738 platform_device_register(&dove_xor1_shared);
739
740 /*
741 * two engines can't do memset simultaneously, this limitation
742 * satisfied by removing memset support from one of the engines.
743 */
744 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
745 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
746 platform_device_register(&dove_xor10_channel);
747
748 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
749 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
750 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
751 platform_device_register(&dove_xor11_channel);
752}
753
754void __init dove_init(void)
755{
756 int tclk;
757
758 tclk = get_tclk();
759
760 printk(KERN_INFO "Dove 88AP510 SoC, ");
761 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
762
763 dove_setup_cpu_mbus();
764
765 dove_ge00_shared_data.t_clk = tclk;
766 dove_uart0_data[0].uartclk = tclk;
767 dove_uart1_data[0].uartclk = tclk;
768 dove_uart2_data[0].uartclk = tclk;
769 dove_uart3_data[0].uartclk = tclk;
770 dove_spi0_data.tclk = tclk;
771 dove_spi1_data.tclk = tclk;
772
773 /* internal devices that every board has */
774 dove_rtc_init();
775 dove_xor0_init();
776 dove_xor1_init();
777}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:14:48 -0500