1 files changed, 48 insertions, 73 deletions

diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 00be4fc26dd7..98b8c83b09ab 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
@@ -34,98 +35,72 @@
 #define ATTR_PCIE_MEM           0xe8
 #define ATTR_SCRATCHPAD         0x0
 
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN_CTRL(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
-#define WIN_BASE(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
-#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
-#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
-
-struct mbus_dram_target_info dove_mbus_dram_info;
-
 static inline void __iomem *ddr_map_sc(int i)
 {
         return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
 }
 
-static int cpu_win_can_remap(int win)
-{
-        if (win < 4)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, WIN_BASE(win));
-        writel(ctrl, WIN_CTRL(win));
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, WIN_REMAP_LO(win));
-                writel(0, WIN_REMAP_HI(win));
-        }
-}
-
-void __init dove_setup_cpu_mbus(void)
-{
-        int i;
-        int cs;
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
+        .remappable_wins = 4,
+        .bridge_virt_base = BRIDGE_VIRT_BASE,
+};
 
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
         /*
-         * First, disable and clear windows.
+         * Windows for PCIe IO+MEM space.
          */
-        for (i = 0; i < 8; i++) {
-                writel(0, WIN_BASE(i));
-                writel(0, WIN_CTRL(i));
-                if (cpu_win_can_remap(i)) {
-                        writel(0, WIN_REMAP_LO(i));
-                        writel(0, WIN_REMAP_HI(i));
-                }
-        }
-
+        { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
+          TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
+        },
+        { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
+          TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
+        },
+        { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
+          TARGET_PCIE0, ATTR_PCIE_MEM, -1
+        },
+        { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
+          TARGET_PCIE1, ATTR_PCIE_MEM, -1
+        },
         /*
-         * Setup windows for PCIe IO+MEM space.
+         * Window for CESA engine.
          */
-        setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
-        setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
-                      TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
-        setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
-                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
-
+        { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
+          TARGET_CESA, ATTR_CESA, -1
+        },
         /*
-         * Setup window for CESA engine.
+         * Window to the BootROM for Standby and Sleep Resume
          */
-        setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
-                      TARGET_CESA, ATTR_CESA, -1);
-
+        { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
+          TARGET_BOOTROM, ATTR_BOOTROM, -1
+        },
         /*
-         * Setup the Window to the BootROM for Standby and Sleep Resume
+         * Window to the PMU Scratch Pad space
          */
-        setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
-                      TARGET_BOOTROM, ATTR_BOOTROM, -1);
+        { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
+          TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
+
+void __init dove_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
 
         /*
-         * Setup the Window to the PMU Scratch Pad space
+         * Disable, clear and configure windows.
          */
-        setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
-                      TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
+        orion_config_wins(&addr_map_cfg, addr_map_info);
 
         /*
          * Setup MBUS dram target info.
          */
-        dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
         for (i = 0, cs = 0; i < 2; i++) {
                 u32 map = readl(ddr_map_sc(i));
@@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
                 if (map & 1) {
                         struct mbus_dram_window *w;
 
-                        w = &dove_mbus_dram_info.cs[cs++];
+                        w = &orion_mbus_dram_info.cs[cs++];
                         w->cs_index = i;
                         w->mbus_attr = 0; /* CS address decoding done inside */
                                           /* the DDR controller, no need to  */
@@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
                         w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
                 }
         }
-        dove_mbus_dram_info.num_cs = cs;
+        orion_mbus_dram_info.num_cs = cs;
 }