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-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c7
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c17
-rw-r--r--arch/arm/mach-davinci/clock.c46
-rw-r--r--arch/arm/mach-davinci/clock.h3
-rw-r--r--arch/arm/mach-davinci/da850.c10
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c126
-rw-r--r--arch/arm/mach-davinci/dm646x.c4
-rw-r--r--arch/arm/mach-davinci/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h151
-rw-r--r--arch/arm/mach-davinci/psc.c14
12 files changed, 287 insertions, 110 deletions
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 29671ef07152..bd5394537c88 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1117,6 +1117,8 @@ static __init int da850_evm_init_cpufreq(void)
1117static __init int da850_evm_init_cpufreq(void) { return 0; } 1117static __init int da850_evm_init_cpufreq(void) { return 0; }
1118#endif 1118#endif
1119 1119
1120#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
1121
1120static __init void da850_evm_init(void) 1122static __init void da850_evm_init(void)
1121{ 1123{
1122 int ret; 1124 int ret;
@@ -1237,6 +1239,11 @@ static __init void da850_evm_init(void)
1237 if (ret) 1239 if (ret)
1238 pr_warning("da850_evm_init: spi 1 registration failed: %d\n", 1240 pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
1239 ret); 1241 ret);
1242
1243 ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
1244 if (ret)
1245 pr_warning("da850_evm_init: sata registration failed: %d\n",
1246 ret);
1240} 1247}
1241 1248
1242#ifdef CONFIG_SERIAL_8250_CONSOLE 1249#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6d03643b9bd1..993a3146fd35 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -719,9 +719,15 @@ static void __init cdce_clk_init(void)
719 } 719 }
720} 720}
721 721
722#define DM6467T_EVM_REF_FREQ 33000000
723
722static void __init davinci_map_io(void) 724static void __init davinci_map_io(void)
723{ 725{
724 dm646x_init(); 726 dm646x_init();
727
728 if (machine_is_davinci_dm6467tevm())
729 davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
730
725 cdce_clk_init(); 731 cdce_clk_init();
726} 732}
727 733
@@ -785,17 +791,6 @@ static __init void evm_init(void)
785 soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; 791 soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
786} 792}
787 793
788#define DM646X_EVM_REF_FREQ 27000000
789#define DM6467T_EVM_REF_FREQ 33000000
790
791void __init dm646x_board_setup_refclk(struct clk *clk)
792{
793 if (machine_is_davinci_dm6467tevm())
794 clk->rate = DM6467T_EVM_REF_FREQ;
795 else
796 clk->rate = DM646X_EVM_REF_FREQ;
797}
798
799MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 794MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
800 .boot_params = (0x80000100), 795 .boot_params = (0x80000100),
801 .map_io = davinci_map_io, 796 .map_io = davinci_map_io,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index e4e3af179f02..00861139101d 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk)
44 __clk_enable(clk->parent); 44 __clk_enable(clk->parent);
45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
47 PSC_STATE_ENABLE); 47 true, clk->flags);
48} 48}
49 49
50static void __clk_disable(struct clk *clk) 50static void __clk_disable(struct clk *clk)
@@ -54,8 +54,7 @@ static void __clk_disable(struct clk *clk)
54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && 54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
55 (clk->flags & CLK_PSC)) 55 (clk->flags & CLK_PSC))
56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
57 (clk->flags & PSC_SWRSTDISABLE) ? 57 false, clk->flags);
58 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
59 if (clk->parent) 58 if (clk->parent)
60 __clk_disable(clk->parent); 59 __clk_disable(clk->parent);
61} 60}
@@ -239,8 +238,7 @@ static int __init clk_disable_unused(void)
239 pr_debug("Clocks: disable unused %s\n", ck->name); 238 pr_debug("Clocks: disable unused %s\n", ck->name);
240 239
241 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 240 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
242 (ck->flags & PSC_SWRSTDISABLE) ? 241 false, ck->flags);
243 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
244 } 242 }
245 spin_unlock_irq(&clockfw_lock); 243 spin_unlock_irq(&clockfw_lock);
246 244
@@ -368,6 +366,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk)
368 return clk->parent->rate; 366 return clk->parent->rate;
369} 367}
370 368
369int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
370{
371 clk->rate = rate;
372 return 0;
373}
374
371static unsigned long clk_pllclk_recalc(struct clk *clk) 375static unsigned long clk_pllclk_recalc(struct clk *clk)
372{ 376{
373 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; 377 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
@@ -506,6 +510,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
506} 510}
507EXPORT_SYMBOL(davinci_set_pllrate); 511EXPORT_SYMBOL(davinci_set_pllrate);
508 512
513/**
514 * davinci_set_refclk_rate() - Set the reference clock rate
515 * @rate: The new rate.
516 *
517 * Sets the reference clock rate to a given value. This will most likely
518 * result in the entire clock tree getting updated.
519 *
520 * This is used to support boards which use a reference clock different
521 * than that used by default in <soc>.c file. The reference clock rate
522 * should be updated early in the boot process; ideally soon after the
523 * clock tree has been initialized once with the default reference clock
524 * rate (davinci_common_init()).
525 *
526 * Returns 0 on success, error otherwise.
527 */
528int davinci_set_refclk_rate(unsigned long rate)
529{
530 struct clk *refclk;
531
532 refclk = clk_get(NULL, "ref");
533 if (IS_ERR(refclk)) {
534 pr_err("%s: failed to get reference clock.\n", __func__);
535 return PTR_ERR(refclk);
536 }
537
538 clk_set_rate(refclk, rate);
539
540 clk_put(refclk);
541
542 return 0;
543}
544
509int __init davinci_clk_init(struct clk_lookup *clocks) 545int __init davinci_clk_init(struct clk_lookup *clocks)
510 { 546 {
511 struct clk_lookup *c; 547 struct clk_lookup *c;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 0dd22031ec62..a705f367a84d 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -111,6 +111,7 @@ struct clk {
111#define CLK_PLL BIT(4) /* PLL-derived clock */ 111#define CLK_PLL BIT(4) /* PLL-derived clock */
112#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 112#define PRE_PLL BIT(5) /* source is before PLL mult/div */
113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ 113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
114#define PSC_FORCE BIT(7) /* Force module state transtition */
114 115
115#define CLK(dev, con, ck) \ 116#define CLK(dev, con, ck) \
116 { \ 117 { \
@@ -123,6 +124,8 @@ int davinci_clk_init(struct clk_lookup *clocks);
123int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 124int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
124 unsigned int mult, unsigned int postdiv); 125 unsigned int mult, unsigned int postdiv);
125int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); 126int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
127int davinci_set_refclk_rate(unsigned long rate);
128int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
126 129
127extern struct platform_device davinci_wdt_device; 130extern struct platform_device davinci_wdt_device;
128extern void davinci_watchdog_reset(struct platform_device *); 131extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 133aac405853..935dbed5c541 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -58,6 +58,7 @@ static struct pll_data pll0_data = {
58static struct clk ref_clk = { 58static struct clk ref_clk = {
59 .name = "ref_clk", 59 .name = "ref_clk",
60 .rate = DA850_REF_FREQ, 60 .rate = DA850_REF_FREQ,
61 .set_rate = davinci_simple_set_rate,
61}; 62};
62 63
63static struct clk pll0_clk = { 64static struct clk pll0_clk = {
@@ -373,6 +374,14 @@ static struct clk spi1_clk = {
373 .flags = DA850_CLK_ASYNC3, 374 .flags = DA850_CLK_ASYNC3,
374}; 375};
375 376
377static struct clk sata_clk = {
378 .name = "sata",
379 .parent = &pll0_sysclk2,
380 .lpsc = DA850_LPSC1_SATA,
381 .gpsc = 1,
382 .flags = PSC_FORCE,
383};
384
376static struct clk_lookup da850_clks[] = { 385static struct clk_lookup da850_clks[] = {
377 CLK(NULL, "ref", &ref_clk), 386 CLK(NULL, "ref", &ref_clk),
378 CLK(NULL, "pll0", &pll0_clk), 387 CLK(NULL, "pll0", &pll0_clk),
@@ -419,6 +428,7 @@ static struct clk_lookup da850_clks[] = {
419 CLK(NULL, "usb20", &usb20_clk), 428 CLK(NULL, "usb20", &usb20_clk),
420 CLK("spi_davinci.0", NULL, &spi0_clk), 429 CLK("spi_davinci.0", NULL, &spi0_clk),
421 CLK("spi_davinci.1", NULL, &spi1_clk), 430 CLK("spi_davinci.1", NULL, &spi1_clk),
431 CLK("ahci", NULL, &sata_clk),
422 CLK(NULL, NULL, NULL), 432 CLK(NULL, NULL, NULL),
423}; 433};
424 434
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc4e98ea7543..2f7e719636f1 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -14,6 +14,8 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
17 19
18#include <mach/cputype.h> 20#include <mach/cputype.h>
19#include <mach/common.h> 21#include <mach/common.h>
@@ -33,6 +35,7 @@
33#define DA8XX_SPI0_BASE 0x01c41000 35#define DA8XX_SPI0_BASE 0x01c41000
34#define DA830_SPI1_BASE 0x01e12000 36#define DA830_SPI1_BASE 0x01e12000
35#define DA8XX_LCD_CNTRL_BASE 0x01e13000 37#define DA8XX_LCD_CNTRL_BASE 0x01e13000
38#define DA850_SATA_BASE 0x01e18000
36#define DA850_MMCSD1_BASE 0x01e1b000 39#define DA850_MMCSD1_BASE 0x01e1b000
37#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 40#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
38#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 41#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
@@ -842,3 +845,126 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
842 845
843 return platform_device_register(&da8xx_spi_device[instance]); 846 return platform_device_register(&da8xx_spi_device[instance]);
844} 847}
848
849#ifdef CONFIG_ARCH_DAVINCI_DA850
850
851static struct resource da850_sata_resources[] = {
852 {
853 .start = DA850_SATA_BASE,
854 .end = DA850_SATA_BASE + 0x1fff,
855 .flags = IORESOURCE_MEM,
856 },
857 {
858 .start = IRQ_DA850_SATAINT,
859 .flags = IORESOURCE_IRQ,
860 },
861};
862
863/* SATA PHY Control Register offset from AHCI base */
864#define SATA_P0PHYCR_REG 0x178
865
866#define SATA_PHY_MPY(x) ((x) << 0)
867#define SATA_PHY_LOS(x) ((x) << 6)
868#define SATA_PHY_RXCDR(x) ((x) << 10)
869#define SATA_PHY_RXEQ(x) ((x) << 13)
870#define SATA_PHY_TXSWING(x) ((x) << 19)
871#define SATA_PHY_ENPLL(x) ((x) << 31)
872
873static struct clk *da850_sata_clk;
874static unsigned long da850_sata_refclkpn;
875
876/* Supported DA850 SATA crystal frequencies */
877#define KHZ_TO_HZ(freq) ((freq) * 1000)
878static unsigned long da850_sata_xtal[] = {
879 KHZ_TO_HZ(300000),
880 KHZ_TO_HZ(250000),
881 0, /* Reserved */
882 KHZ_TO_HZ(187500),
883 KHZ_TO_HZ(150000),
884 KHZ_TO_HZ(125000),
885 KHZ_TO_HZ(120000),
886 KHZ_TO_HZ(100000),
887 KHZ_TO_HZ(75000),
888 KHZ_TO_HZ(60000),
889};
890
891static int da850_sata_init(struct device *dev, void __iomem *addr)
892{
893 int i, ret;
894 unsigned int val;
895
896 da850_sata_clk = clk_get(dev, NULL);
897 if (IS_ERR(da850_sata_clk))
898 return PTR_ERR(da850_sata_clk);
899
900 ret = clk_enable(da850_sata_clk);
901 if (ret)
902 goto err0;
903
904 /* Enable SATA clock receiver */
905 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
906 val &= ~BIT(0);
907 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
908
909 /* Get the multiplier needed for 1.5GHz PLL output */
910 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
911 if (da850_sata_xtal[i] == da850_sata_refclkpn)
912 break;
913
914 if (i == ARRAY_SIZE(da850_sata_xtal)) {
915 ret = -EINVAL;
916 goto err1;
917 }
918
919 val = SATA_PHY_MPY(i + 1) |
920 SATA_PHY_LOS(1) |
921 SATA_PHY_RXCDR(4) |
922 SATA_PHY_RXEQ(1) |
923 SATA_PHY_TXSWING(3) |
924 SATA_PHY_ENPLL(1);
925
926 __raw_writel(val, addr + SATA_P0PHYCR_REG);
927
928 return 0;
929
930err1:
931 clk_disable(da850_sata_clk);
932err0:
933 clk_put(da850_sata_clk);
934 return ret;
935}
936
937static void da850_sata_exit(struct device *dev)
938{
939 clk_disable(da850_sata_clk);
940 clk_put(da850_sata_clk);
941}
942
943static struct ahci_platform_data da850_sata_pdata = {
944 .init = da850_sata_init,
945 .exit = da850_sata_exit,
946};
947
948static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
949
950static struct platform_device da850_sata_device = {
951 .name = "ahci",
952 .id = -1,
953 .dev = {
954 .platform_data = &da850_sata_pdata,
955 .dma_mask = &da850_sata_dmamask,
956 .coherent_dma_mask = DMA_BIT_MASK(32),
957 },
958 .num_resources = ARRAY_SIZE(da850_sata_resources),
959 .resource = da850_sata_resources,
960};
961
962int __init da850_register_sata(unsigned long refclkpn)
963{
964 da850_sata_refclkpn = refclkpn;
965 if (!da850_sata_refclkpn)
966 return -EINVAL;
967
968 return platform_device_register(&da850_sata_device);
969}
970#endif
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e00d61e2efbe..1802e711a2b8 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -43,6 +43,7 @@
43/* 43/*
44 * Device specific clocks 44 * Device specific clocks
45 */ 45 */
46#define DM646X_REF_FREQ 27000000
46#define DM646X_AUX_FREQ 24000000 47#define DM646X_AUX_FREQ 24000000
47 48
48static struct pll_data pll1_data = { 49static struct pll_data pll1_data = {
@@ -57,6 +58,8 @@ static struct pll_data pll2_data = {
57 58
58static struct clk ref_clk = { 59static struct clk ref_clk = {
59 .name = "ref_clk", 60 .name = "ref_clk",
61 .rate = DM646X_REF_FREQ,
62 .set_rate = davinci_simple_set_rate,
60}; 63};
61 64
62static struct clk aux_clkin = { 65static struct clk aux_clkin = {
@@ -902,7 +905,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
902 905
903void __init dm646x_init(void) 906void __init dm646x_init(void)
904{ 907{
905 dm646x_board_setup_refclk(&ref_clk);
906 davinci_common_init(&davinci_soc_info_dm646x); 908 davinci_common_init(&davinci_soc_info_dm646x);
907} 909}
908 910
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
deleted file mode 100644
index 14a504887189..000000000000
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4struct clk;
5
6static inline int __clk_get(struct clk *clk)
7{
8 return 1;
9}
10
11static inline void __clk_put(struct clk *clk)
12{
13}
14
15#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ad64da713fc8..eaca7d8b9d68 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed;
57#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) 57#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
58#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) 58#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
59#define DA8XX_DEEPSLEEP_REG 0x8 59#define DA8XX_DEEPSLEEP_REG 0x8
60#define DA8XX_PWRDN_REG 0x18
60 61
61#define DA8XX_PSC0_BASE 0x01c10000 62#define DA8XX_PSC0_BASE 0x01c10000
62#define DA8XX_PLL0_BASE 0x01c11000 63#define DA8XX_PLL0_BASE 0x01c11000
@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk);
89int da8xx_register_cpuidle(void); 90int da8xx_register_cpuidle(void);
90void __iomem * __init da8xx_get_mem_ctlr(void); 91void __iomem * __init da8xx_get_mem_ctlr(void);
91int da850_register_pm(struct platform_device *pdev); 92int da850_register_pm(struct platform_device *pdev);
93int __init da850_register_sata(unsigned long refclkpn);
92 94
93extern struct platform_device da8xx_serial_device; 95extern struct platform_device da8xx_serial_device;
94extern struct emac_platform_data da8xx_emac_pdata; 96extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 7a27f3f13913..2a00fe5ac253 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -15,7 +15,6 @@
15#include <mach/asp.h> 15#include <mach/asp.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/videodev2.h> 17#include <linux/videodev2.h>
18#include <linux/clk.h>
19#include <linux/davinci_emac.h> 18#include <linux/davinci_emac.h>
20 19
21#define DM646X_EMAC_BASE (0x01C80000) 20#define DM646X_EMAC_BASE (0x01C80000)
@@ -31,7 +30,6 @@
31void __init dm646x_init(void); 30void __init dm646x_init(void);
32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 31void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk);
35int __init dm646x_init_edma(struct edma_rsv_info *rsv); 33int __init dm646x_init_edma(struct edma_rsv_info *rsv);
36 34
37void dm646x_video_init(void); 35void dm646x_video_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index a47e6f29206e..47fd0bc3d3e7 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -30,47 +30,47 @@
30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
31 31
32/* Power and Sleep Controller (PSC) Domains */ 32/* Power and Sleep Controller (PSC) Domains */
33#define DAVINCI_GPSC_ARMDOMAIN 0 33#define DAVINCI_GPSC_ARMDOMAIN 0
34#define DAVINCI_GPSC_DSPDOMAIN 1 34#define DAVINCI_GPSC_DSPDOMAIN 1
35 35
36#define DAVINCI_LPSC_VPSSMSTR 0 36#define DAVINCI_LPSC_VPSSMSTR 0
37#define DAVINCI_LPSC_VPSSSLV 1 37#define DAVINCI_LPSC_VPSSSLV 1
38#define DAVINCI_LPSC_TPCC 2 38#define DAVINCI_LPSC_TPCC 2
39#define DAVINCI_LPSC_TPTC0 3 39#define DAVINCI_LPSC_TPTC0 3
40#define DAVINCI_LPSC_TPTC1 4 40#define DAVINCI_LPSC_TPTC1 4
41#define DAVINCI_LPSC_EMAC 5 41#define DAVINCI_LPSC_EMAC 5
42#define DAVINCI_LPSC_EMAC_WRAPPER 6 42#define DAVINCI_LPSC_EMAC_WRAPPER 6
43#define DAVINCI_LPSC_USB 9 43#define DAVINCI_LPSC_USB 9
44#define DAVINCI_LPSC_ATA 10 44#define DAVINCI_LPSC_ATA 10
45#define DAVINCI_LPSC_VLYNQ 11 45#define DAVINCI_LPSC_VLYNQ 11
46#define DAVINCI_LPSC_UHPI 12 46#define DAVINCI_LPSC_UHPI 12
47#define DAVINCI_LPSC_DDR_EMIF 13 47#define DAVINCI_LPSC_DDR_EMIF 13
48#define DAVINCI_LPSC_AEMIF 14 48#define DAVINCI_LPSC_AEMIF 14
49#define DAVINCI_LPSC_MMC_SD 15 49#define DAVINCI_LPSC_MMC_SD 15
50#define DAVINCI_LPSC_McBSP 17 50#define DAVINCI_LPSC_McBSP 17
51#define DAVINCI_LPSC_I2C 18 51#define DAVINCI_LPSC_I2C 18
52#define DAVINCI_LPSC_UART0 19 52#define DAVINCI_LPSC_UART0 19
53#define DAVINCI_LPSC_UART1 20 53#define DAVINCI_LPSC_UART1 20
54#define DAVINCI_LPSC_UART2 21 54#define DAVINCI_LPSC_UART2 21
55#define DAVINCI_LPSC_SPI 22 55#define DAVINCI_LPSC_SPI 22
56#define DAVINCI_LPSC_PWM0 23 56#define DAVINCI_LPSC_PWM0 23
57#define DAVINCI_LPSC_PWM1 24 57#define DAVINCI_LPSC_PWM1 24
58#define DAVINCI_LPSC_PWM2 25 58#define DAVINCI_LPSC_PWM2 25
59#define DAVINCI_LPSC_GPIO 26 59#define DAVINCI_LPSC_GPIO 26
60#define DAVINCI_LPSC_TIMER0 27 60#define DAVINCI_LPSC_TIMER0 27
61#define DAVINCI_LPSC_TIMER1 28 61#define DAVINCI_LPSC_TIMER1 28
62#define DAVINCI_LPSC_TIMER2 29 62#define DAVINCI_LPSC_TIMER2 29
63#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 63#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
64#define DAVINCI_LPSC_ARM 31 64#define DAVINCI_LPSC_ARM 31
65#define DAVINCI_LPSC_SCR2 32 65#define DAVINCI_LPSC_SCR2 32
66#define DAVINCI_LPSC_SCR3 33 66#define DAVINCI_LPSC_SCR3 33
67#define DAVINCI_LPSC_SCR4 34 67#define DAVINCI_LPSC_SCR4 34
68#define DAVINCI_LPSC_CROSSBAR 35 68#define DAVINCI_LPSC_CROSSBAR 35
69#define DAVINCI_LPSC_CFG27 36 69#define DAVINCI_LPSC_CFG27 36
70#define DAVINCI_LPSC_CFG3 37 70#define DAVINCI_LPSC_CFG3 37
71#define DAVINCI_LPSC_CFG5 38 71#define DAVINCI_LPSC_CFG5 38
72#define DAVINCI_LPSC_GEM 39 72#define DAVINCI_LPSC_GEM 39
73#define DAVINCI_LPSC_IMCOP 40 73#define DAVINCI_LPSC_IMCOP 40
74 74
75#define DM355_LPSC_TIMER3 5 75#define DM355_LPSC_TIMER3 5
76#define DM355_LPSC_SPI1 6 76#define DM355_LPSC_SPI1 6
@@ -102,39 +102,39 @@
102/* 102/*
103 * LPSC Assignments 103 * LPSC Assignments
104 */ 104 */
105#define DM646X_LPSC_ARM 0 105#define DM646X_LPSC_ARM 0
106#define DM646X_LPSC_C64X_CPU 1 106#define DM646X_LPSC_C64X_CPU 1
107#define DM646X_LPSC_HDVICP0 2 107#define DM646X_LPSC_HDVICP0 2
108#define DM646X_LPSC_HDVICP1 3 108#define DM646X_LPSC_HDVICP1 3
109#define DM646X_LPSC_TPCC 4 109#define DM646X_LPSC_TPCC 4
110#define DM646X_LPSC_TPTC0 5 110#define DM646X_LPSC_TPTC0 5
111#define DM646X_LPSC_TPTC1 6 111#define DM646X_LPSC_TPTC1 6
112#define DM646X_LPSC_TPTC2 7 112#define DM646X_LPSC_TPTC2 7
113#define DM646X_LPSC_TPTC3 8 113#define DM646X_LPSC_TPTC3 8
114#define DM646X_LPSC_PCI 13 114#define DM646X_LPSC_PCI 13
115#define DM646X_LPSC_EMAC 14 115#define DM646X_LPSC_EMAC 14
116#define DM646X_LPSC_VDCE 15 116#define DM646X_LPSC_VDCE 15
117#define DM646X_LPSC_VPSSMSTR 16 117#define DM646X_LPSC_VPSSMSTR 16
118#define DM646X_LPSC_VPSSSLV 17 118#define DM646X_LPSC_VPSSSLV 17
119#define DM646X_LPSC_TSIF0 18 119#define DM646X_LPSC_TSIF0 18
120#define DM646X_LPSC_TSIF1 19 120#define DM646X_LPSC_TSIF1 19
121#define DM646X_LPSC_DDR_EMIF 20 121#define DM646X_LPSC_DDR_EMIF 20
122#define DM646X_LPSC_AEMIF 21 122#define DM646X_LPSC_AEMIF 21
123#define DM646X_LPSC_McASP0 22 123#define DM646X_LPSC_McASP0 22
124#define DM646X_LPSC_McASP1 23 124#define DM646X_LPSC_McASP1 23
125#define DM646X_LPSC_CRGEN0 24 125#define DM646X_LPSC_CRGEN0 24
126#define DM646X_LPSC_CRGEN1 25 126#define DM646X_LPSC_CRGEN1 25
127#define DM646X_LPSC_UART0 26 127#define DM646X_LPSC_UART0 26
128#define DM646X_LPSC_UART1 27 128#define DM646X_LPSC_UART1 27
129#define DM646X_LPSC_UART2 28 129#define DM646X_LPSC_UART2 28
130#define DM646X_LPSC_PWM0 29 130#define DM646X_LPSC_PWM0 29
131#define DM646X_LPSC_PWM1 30 131#define DM646X_LPSC_PWM1 30
132#define DM646X_LPSC_I2C 31 132#define DM646X_LPSC_I2C 31
133#define DM646X_LPSC_SPI 32 133#define DM646X_LPSC_SPI 32
134#define DM646X_LPSC_GPIO 33 134#define DM646X_LPSC_GPIO 33
135#define DM646X_LPSC_TIMER0 34 135#define DM646X_LPSC_TIMER0 34
136#define DM646X_LPSC_TIMER1 35 136#define DM646X_LPSC_TIMER1 35
137#define DM646X_LPSC_ARM_INTC 45 137#define DM646X_LPSC_ARM_INTC 45
138 138
139/* PSC0 defines */ 139/* PSC0 defines */
140#define DA8XX_LPSC0_TPCC 0 140#define DA8XX_LPSC0_TPCC 0
@@ -243,13 +243,14 @@
243#define PSC_STATE_DISABLE 2 243#define PSC_STATE_DISABLE 2
244#define PSC_STATE_ENABLE 3 244#define PSC_STATE_ENABLE 3
245 245
246#define MDSTAT_STATE_MASK 0x1f 246#define MDSTAT_STATE_MASK 0x1f
247#define MDCTL_FORCE BIT(31)
247 248
248#ifndef __ASSEMBLER__ 249#ifndef __ASSEMBLER__
249 250
250extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 251extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
251extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 252extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
252 unsigned int id, u32 next_state); 253 unsigned int id, bool enable, u32 flags);
253 254
254#endif 255#endif
255 256
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index a41580400701..1fb6bdff38c1 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -25,6 +25,8 @@
25#include <mach/cputype.h> 25#include <mach/cputype.h>
26#include <mach/psc.h> 26#include <mach/psc.h>
27 27
28#include "clock.h"
29
28/* Return nonzero iff the domain's clock is active */ 30/* Return nonzero iff the domain's clock is active */
29int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) 31int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
30{ 32{
@@ -48,11 +50,12 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
48 50
49/* Enable or disable a PSC domain */ 51/* Enable or disable a PSC domain */
50void davinci_psc_config(unsigned int domain, unsigned int ctlr, 52void davinci_psc_config(unsigned int domain, unsigned int ctlr,
51 unsigned int id, u32 next_state) 53 unsigned int id, bool enable, u32 flags)
52{ 54{
53 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; 55 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
54 void __iomem *psc_base; 56 void __iomem *psc_base;
55 struct davinci_soc_info *soc_info = &davinci_soc_info; 57 struct davinci_soc_info *soc_info = &davinci_soc_info;
58 u32 next_state = PSC_STATE_ENABLE;
56 59
57 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { 60 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
58 pr_warning("PSC: Bad psc data: 0x%x[%d]\n", 61 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
@@ -62,9 +65,18 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
62 65
63 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); 66 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
64 67
68 if (!enable) {
69 if (flags & PSC_SWRSTDISABLE)
70 next_state = PSC_STATE_SWRSTDISABLE;
71 else
72 next_state = PSC_STATE_DISABLE;
73 }
74
65 mdctl = __raw_readl(psc_base + MDCTL + 4 * id); 75 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
66 mdctl &= ~MDSTAT_STATE_MASK; 76 mdctl &= ~MDSTAT_STATE_MASK;
67 mdctl |= next_state; 77 mdctl |= next_state;
78 if (flags & PSC_FORCE)
79 mdctl |= MDCTL_FORCE;
68 __raw_writel(mdctl, psc_base + MDCTL + 4 * id); 80 __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
69 81
70 pdstat = __raw_readl(psc_base + PDSTAT); 82 pdstat = __raw_readl(psc_base + PDSTAT);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 16:26:28 -0500