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-rw-r--r--arch/arm/mach-davinci/Kconfig12
-rw-r--r--arch/arm/mach-davinci/Makefile3
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c32
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c52
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c35
-rw-r--r--arch/arm/mach-davinci/board-tnetv107x-evm.c174
-rw-r--r--arch/arm/mach-davinci/da830.c5
-rw-r--r--arch/arm/mach-davinci/da850.c25
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c50
-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c320
-rw-r--r--arch/arm/mach-davinci/dm355.c22
-rw-r--r--arch/arm/mach-davinci/dm365.c28
-rw-r--r--arch/arm/mach-davinci/dm644x.c22
-rw-r--r--arch/arm/mach-davinci/dm646x.c30
-rw-r--r--arch/arm/mach-davinci/dma.c62
-rw-r--r--arch/arm/mach-davinci/gpio-tnetv107x.c205
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S50
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h11
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h22
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h21
-rw-r--r--arch/arm/mach-davinci/include/mach/tnetv107x.h55
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h87
-rw-r--r--arch/arm/mach-davinci/tnetv107x.c753
25 files changed, 1933 insertions, 147 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0316e201ada0..71f90f864748 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
50 select AINTC 50 select AINTC
51 select ARCH_DAVINCI_DMx 51 select ARCH_DAVINCI_DMx
52 52
53config ARCH_DAVINCI_TNETV107X
54 select CPU_V6
55 select CP_INTC
56 bool "TNETV107X based system"
57
53comment "DaVinci Board Type" 58comment "DaVinci Board Type"
54 59
55config MACH_DAVINCI_EVM 60config MACH_DAVINCI_EVM
@@ -173,6 +178,13 @@ config DA850_UI_RMII
173 178
174endchoice 179endchoice
175 180
181config MACH_TNETV107X
182 bool "TI TNETV107X Reference Platform"
183 default ARCH_DAVINCI_TNETV107X
184 depends on ARCH_DAVINCI_TNETV107X
185 help
186 Say Y here to select the TI TNETV107X Evaluation Module.
187
176config DAVINCI_MUX 188config DAVINCI_MUX
177 bool "DAVINCI multiplexing support" 189 bool "DAVINCI multiplexing support"
178 depends on ARCH_DAVINCI 190 depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6aac880eb794..eab4c0fd667a 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
16obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o 16obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
17obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o 17obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o
18obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o 18obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o
19obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o
20obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
19 21
20obj-$(CONFIG_AINTC) += irq.o 22obj-$(CONFIG_AINTC) += irq.o
21obj-$(CONFIG_CP_INTC) += cp_intc.o 23obj-$(CONFIG_CP_INTC) += cp_intc.o
@@ -30,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
30obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
31obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 33obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
32obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 34obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
35obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o
33 36
34# Power Management 37# Power Management
35obj-$(CONFIG_CPU_FREQ) += cpufreq.o 38obj-$(CONFIG_CPU_FREQ) += cpufreq.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index bc384d3561da..c3994f341e49 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -494,12 +494,42 @@ static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
494 .bus_delay = 0, /* usec */ 494 .bus_delay = 0, /* usec */
495}; 495};
496 496
497/*
498 * The following EDMA channels/slots are not being used by drivers (for
499 * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
500 * they are being reserved for codecs on the DSP side.
501 */
502static const s16 da830_dma_rsv_chans[][2] = {
503 /* (offset, number) */
504 { 8, 2},
505 {12, 2},
506 {24, 4},
507 {30, 2},
508 {-1, -1}
509};
510
511static const s16 da830_dma_rsv_slots[][2] = {
512 /* (offset, number) */
513 { 8, 2},
514 {12, 2},
515 {24, 4},
516 {30, 26},
517 {-1, -1}
518};
519
520static struct edma_rsv_info da830_edma_rsv[] = {
521 {
522 .rsv_chans = da830_dma_rsv_chans,
523 .rsv_slots = da830_dma_rsv_slots,
524 },
525};
526
497static __init void da830_evm_init(void) 527static __init void da830_evm_init(void)
498{ 528{
499 struct davinci_soc_info *soc_info = &davinci_soc_info; 529 struct davinci_soc_info *soc_info = &davinci_soc_info;
500 int ret; 530 int ret;
501 531
502 ret = da8xx_register_edma(); 532 ret = da830_register_edma(da830_edma_rsv);
503 if (ret) 533 if (ret)
504 pr_warning("da830_evm_init: edma registration failed: %d\n", 534 pr_warning("da830_evm_init: edma registration failed: %d\n",
505 ret); 535 ret);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index e8c819090268..fdc2cc500fc6 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -637,6 +637,56 @@ static int __init da850_evm_config_emac(void)
637} 637}
638device_initcall(da850_evm_config_emac); 638device_initcall(da850_evm_config_emac);
639 639
640/*
641 * The following EDMA channels/slots are not being used by drivers (for
642 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
643 * they are being reserved for codecs on the DSP side.
644 */
645static const s16 da850_dma0_rsv_chans[][2] = {
646 /* (offset, number) */
647 { 8, 6},
648 {24, 4},
649 {30, 2},
650 {-1, -1}
651};
652
653static const s16 da850_dma0_rsv_slots[][2] = {
654 /* (offset, number) */
655 { 8, 6},
656 {24, 4},
657 {30, 50},
658 {-1, -1}
659};
660
661static const s16 da850_dma1_rsv_chans[][2] = {
662 /* (offset, number) */
663 { 0, 28},
664 {30, 2},
665 {-1, -1}
666};
667
668static const s16 da850_dma1_rsv_slots[][2] = {
669 /* (offset, number) */
670 { 0, 28},
671 {30, 90},
672 {-1, -1}
673};
674
675static struct edma_rsv_info da850_edma_cc0_rsv = {
676 .rsv_chans = da850_dma0_rsv_chans,
677 .rsv_slots = da850_dma0_rsv_slots,
678};
679
680static struct edma_rsv_info da850_edma_cc1_rsv = {
681 .rsv_chans = da850_dma1_rsv_chans,
682 .rsv_slots = da850_dma1_rsv_slots,
683};
684
685static struct edma_rsv_info *da850_edma_rsv[2] = {
686 &da850_edma_cc0_rsv,
687 &da850_edma_cc1_rsv,
688};
689
640static __init void da850_evm_init(void) 690static __init void da850_evm_init(void)
641{ 691{
642 int ret; 692 int ret;
@@ -646,7 +696,7 @@ static __init void da850_evm_init(void)
646 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n", 696 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
647 ret); 697 ret);
648 698
649 ret = da8xx_register_edma(); 699 ret = da850_register_edma(da850_edma_rsv);
650 if (ret) 700 if (ret)
651 pr_warning("da850_evm_init: edma registration failed: %d\n", 701 pr_warning("da850_evm_init: edma registration failed: %d\n",
652 ret); 702 ret);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 87521f2d69c7..4502f346b2b0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -721,6 +721,39 @@ static struct davinci_uart_config uart_config __initdata = {
721#define DM646X_EVM_PHY_MASK (0x2) 721#define DM646X_EVM_PHY_MASK (0x2)
722#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 722#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
723 723
724/*
725 * The following EDMA channels/slots are not being used by drivers (for
726 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
727 * reserved for codecs on the DSP side.
728 */
729static const s16 dm646x_dma_rsv_chans[][2] = {
730 /* (offset, number) */
731 { 0, 4},
732 {13, 3},
733 {24, 4},
734 {30, 2},
735 {54, 3},
736 {-1, -1}
737};
738
739static const s16 dm646x_dma_rsv_slots[][2] = {
740 /* (offset, number) */
741 { 0, 4},
742 {13, 3},
743 {24, 4},
744 {30, 2},
745 {54, 3},
746 {128, 384},
747 {-1, -1}
748};
749
750static struct edma_rsv_info dm646x_edma_rsv[] = {
751 {
752 .rsv_chans = dm646x_dma_rsv_chans,
753 .rsv_slots = dm646x_dma_rsv_slots,
754 },
755};
756
724static __init void evm_init(void) 757static __init void evm_init(void)
725{ 758{
726 struct davinci_soc_info *soc_info = &davinci_soc_info; 759 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -732,6 +765,8 @@ static __init void evm_init(void)
732 765
733 platform_device_register(&davinci_nand_device); 766 platform_device_register(&davinci_nand_device);
734 767
768 dm646x_init_edma(dm646x_edma_rsv);
769
735 if (HAS_ATA) 770 if (HAS_ATA)
736 davinci_init_ide(); 771 davinci_init_ide();
737 772
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
new file mode 100644
index 000000000000..fe2a9d9c8bb7
--- /dev/null
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -0,0 +1,174 @@
1/*
2 * Texas Instruments TNETV107X EVM Board Support
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/interrupt.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/ratelimit.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <asm/mach/arch.h>
27#include <asm/mach-types.h>
28
29#include <mach/irqs.h>
30#include <mach/edma.h>
31#include <mach/mux.h>
32#include <mach/cp_intc.h>
33#include <mach/tnetv107x.h>
34
35#define EVM_MMC_WP_GPIO 21
36#define EVM_MMC_CD_GPIO 24
37
38static int initialize_gpio(int gpio, char *desc)
39{
40 int ret;
41
42 ret = gpio_request(gpio, desc);
43 if (ret < 0) {
44 pr_err_ratelimited("cannot open %s gpio\n", desc);
45 return -ENOSYS;
46 }
47 gpio_direction_input(gpio);
48 return gpio;
49}
50
51static int mmc_get_cd(int index)
52{
53 static int gpio;
54
55 if (!gpio)
56 gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
57
58 if (gpio < 0)
59 return gpio;
60
61 return gpio_get_value(gpio) ? 0 : 1;
62}
63
64static int mmc_get_ro(int index)
65{
66 static int gpio;
67
68 if (!gpio)
69 gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
70
71 if (gpio < 0)
72 return gpio;
73
74 return gpio_get_value(gpio) ? 1 : 0;
75}
76
77static struct davinci_mmc_config mmc_config = {
78 .get_cd = mmc_get_cd,
79 .get_ro = mmc_get_ro,
80 .wires = 4,
81 .max_freq = 50000000,
82 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
83 .version = MMC_CTLR_VERSION_1,
84};
85
86static const short sdio1_pins[] __initdata = {
87 TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1,
88 TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1,
89 TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1,
90 TNETV107X_GPIO21, TNETV107X_GPIO24,
91 -1
92};
93
94static const short uart1_pins[] __initdata = {
95 TNETV107X_UART1_RD, TNETV107X_UART1_TD,
96 -1
97};
98
99static struct mtd_partition nand_partitions[] = {
100 /* bootloader (U-Boot, etc) in first 12 sectors */
101 {
102 .name = "bootloader",
103 .offset = 0,
104 .size = (12*SZ_128K),
105 .mask_flags = MTD_WRITEABLE, /* force read-only */
106 },
107 /* bootloader params in the next sector */
108 {
109 .name = "params",
110 .offset = MTDPART_OFS_NXTBLK,
111 .size = SZ_128K,
112 .mask_flags = MTD_WRITEABLE, /* force read-only */
113 },
114 /* kernel */
115 {
116 .name = "kernel",
117 .offset = MTDPART_OFS_NXTBLK,
118 .size = SZ_4M,
119 .mask_flags = 0,
120 },
121 /* file system */
122 {
123 .name = "filesystem",
124 .offset = MTDPART_OFS_NXTBLK,
125 .size = MTDPART_SIZ_FULL,
126 .mask_flags = 0,
127 }
128};
129
130static struct davinci_nand_pdata nand_config = {
131 .mask_cle = 0x4000,
132 .mask_ale = 0x2000,
133 .parts = nand_partitions,
134 .nr_parts = ARRAY_SIZE(nand_partitions),
135 .ecc_mode = NAND_ECC_HW,
136 .options = NAND_USE_FLASH_BBT,
137 .ecc_bits = 1,
138};
139
140static struct davinci_uart_config serial_config __initconst = {
141 .enabled_uarts = BIT(1),
142};
143
144static struct tnetv107x_device_info evm_device_info __initconst = {
145 .serial_config = &serial_config,
146 .mmc_config[1] = &mmc_config, /* controller 1 */
147 .nand_config[0] = &nand_config, /* chip select 0 */
148};
149
150static __init void tnetv107x_evm_board_init(void)
151{
152 davinci_cfg_reg_list(sdio1_pins);
153 davinci_cfg_reg_list(uart1_pins);
154
155 tnetv107x_devices_init(&evm_device_info);
156}
157
158#ifdef CONFIG_SERIAL_8250_CONSOLE
159static int __init tnetv107x_evm_console_init(void)
160{
161 return add_preferred_console("ttyS", 0, "115200");
162}
163console_initcall(tnetv107x_evm_console_init);
164#endif
165
166MACHINE_START(TNETV107X, "TNETV107X EVM")
167 .phys_io = TNETV107X_IO_BASE,
168 .io_pg_offst = (TNETV107X_IO_VIRT >> 18) & 0xfffc,
169 .boot_params = (TNETV107X_DDR_BASE + 0x100),
170 .map_io = tnetv107x_init,
171 .init_irq = cp_intc_init,
172 .timer = &davinci_timer,
173 .init_machine = tnetv107x_evm_board_init,
174MACHINE_END
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 23e9eda5a377..ec23ab473620 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1024,7 +1024,6 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
1024 [IRQ_DA8XX_EVTOUT4] = 7, 1024 [IRQ_DA8XX_EVTOUT4] = 7,
1025 [IRQ_DA8XX_EVTOUT5] = 7, 1025 [IRQ_DA8XX_EVTOUT5] = 7,
1026 [IRQ_DA8XX_EVTOUT6] = 7, 1026 [IRQ_DA8XX_EVTOUT6] = 7,
1027 [IRQ_DA8XX_EVTOUT6] = 7,
1028 [IRQ_DA8XX_EVTOUT7] = 7, 1027 [IRQ_DA8XX_EVTOUT7] = 7,
1029 [IRQ_DA8XX_CCINT0] = 7, 1028 [IRQ_DA8XX_CCINT0] = 7,
1030 [IRQ_DA8XX_CCERRINT] = 7, 1029 [IRQ_DA8XX_CCERRINT] = 7,
@@ -1042,11 +1041,7 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
1042 [IRQ_DA8XX_TINT34_1] = 7, 1041 [IRQ_DA8XX_TINT34_1] = 7,
1043 [IRQ_DA8XX_UARTINT0] = 7, 1042 [IRQ_DA8XX_UARTINT0] = 7,
1044 [IRQ_DA8XX_KEYMGRINT] = 7, 1043 [IRQ_DA8XX_KEYMGRINT] = 7,
1045 [IRQ_DA8XX_SECINT] = 7,
1046 [IRQ_DA8XX_SECKEYERR] = 7,
1047 [IRQ_DA830_MPUERR] = 7, 1044 [IRQ_DA830_MPUERR] = 7,
1048 [IRQ_DA830_IOPUERR] = 7,
1049 [IRQ_DA830_BOOTCFGERR] = 7,
1050 [IRQ_DA8XX_CHIPINT0] = 7, 1045 [IRQ_DA8XX_CHIPINT0] = 7,
1051 [IRQ_DA8XX_CHIPINT1] = 7, 1046 [IRQ_DA8XX_CHIPINT1] = 7,
1052 [IRQ_DA8XX_CHIPINT2] = 7, 1047 [IRQ_DA8XX_CHIPINT2] = 7,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 6b8331bf8cf3..68ed58a48252 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -643,7 +643,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
643 [IRQ_DA8XX_EVTOUT4] = 7, 643 [IRQ_DA8XX_EVTOUT4] = 7,
644 [IRQ_DA8XX_EVTOUT5] = 7, 644 [IRQ_DA8XX_EVTOUT5] = 7,
645 [IRQ_DA8XX_EVTOUT6] = 7, 645 [IRQ_DA8XX_EVTOUT6] = 7,
646 [IRQ_DA8XX_EVTOUT6] = 7,
647 [IRQ_DA8XX_EVTOUT7] = 7, 646 [IRQ_DA8XX_EVTOUT7] = 7,
648 [IRQ_DA8XX_CCINT0] = 7, 647 [IRQ_DA8XX_CCINT0] = 7,
649 [IRQ_DA8XX_CCERRINT] = 7, 648 [IRQ_DA8XX_CCERRINT] = 7,
@@ -661,27 +660,7 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
661 [IRQ_DA8XX_TINT34_1] = 7, 660 [IRQ_DA8XX_TINT34_1] = 7,
662 [IRQ_DA8XX_UARTINT0] = 7, 661 [IRQ_DA8XX_UARTINT0] = 7,
663 [IRQ_DA8XX_KEYMGRINT] = 7, 662 [IRQ_DA8XX_KEYMGRINT] = 7,
664 [IRQ_DA8XX_SECINT] = 7,
665 [IRQ_DA8XX_SECKEYERR] = 7,
666 [IRQ_DA850_MPUADDRERR0] = 7, 663 [IRQ_DA850_MPUADDRERR0] = 7,
667 [IRQ_DA850_MPUPROTERR0] = 7,
668 [IRQ_DA850_IOPUADDRERR0] = 7,
669 [IRQ_DA850_IOPUPROTERR0] = 7,
670 [IRQ_DA850_IOPUADDRERR1] = 7,
671 [IRQ_DA850_IOPUPROTERR1] = 7,
672 [IRQ_DA850_IOPUADDRERR2] = 7,
673 [IRQ_DA850_IOPUPROTERR2] = 7,
674 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
675 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
676 [IRQ_DA850_MPUADDRERR1] = 7,
677 [IRQ_DA850_MPUPROTERR1] = 7,
678 [IRQ_DA850_IOPUADDRERR3] = 7,
679 [IRQ_DA850_IOPUPROTERR3] = 7,
680 [IRQ_DA850_IOPUADDRERR4] = 7,
681 [IRQ_DA850_IOPUPROTERR4] = 7,
682 [IRQ_DA850_IOPUADDRERR5] = 7,
683 [IRQ_DA850_IOPUPROTERR5] = 7,
684 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
685 [IRQ_DA8XX_CHIPINT0] = 7, 664 [IRQ_DA8XX_CHIPINT0] = 7,
686 [IRQ_DA8XX_CHIPINT1] = 7, 665 [IRQ_DA8XX_CHIPINT1] = 7,
687 [IRQ_DA8XX_CHIPINT2] = 7, 666 [IRQ_DA8XX_CHIPINT2] = 7,
@@ -722,8 +701,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
722 [IRQ_DA8XX_EHRPWM1] = 7, 701 [IRQ_DA8XX_EHRPWM1] = 7,
723 [IRQ_DA8XX_EHRPWM1TZ] = 7, 702 [IRQ_DA8XX_EHRPWM1TZ] = 7,
724 [IRQ_DA850_SATAINT] = 7, 703 [IRQ_DA850_SATAINT] = 7,
725 [IRQ_DA850_TINT12_2] = 7,
726 [IRQ_DA850_TINT34_2] = 7,
727 [IRQ_DA850_TINTALL_2] = 7, 704 [IRQ_DA850_TINTALL_2] = 7,
728 [IRQ_DA8XX_ECAP0] = 7, 705 [IRQ_DA8XX_ECAP0] = 7,
729 [IRQ_DA8XX_ECAP1] = 7, 706 [IRQ_DA8XX_ECAP1] = 7,
@@ -751,8 +728,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
751 [IRQ_DA850_CCINT1] = 7, 728 [IRQ_DA850_CCINT1] = 7,
752 [IRQ_DA850_CCERRINT1] = 7, 729 [IRQ_DA850_CCERRINT1] = 7,
753 [IRQ_DA850_TCERRINT2] = 7, 730 [IRQ_DA850_TCERRINT2] = 7,
754 [IRQ_DA850_TINT12_3] = 7,
755 [IRQ_DA850_TINT34_3] = 7,
756 [IRQ_DA850_TINTALL_3] = 7, 731 [IRQ_DA850_TINTALL_3] = 7,
757 [IRQ_DA850_MCBSP0RINT] = 7, 732 [IRQ_DA850_MCBSP0RINT] = 7,
758 [IRQ_DA850_MCBSP0XINT] = 7, 733 [IRQ_DA850_MCBSP0XINT] = 7,
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 8cda729be273..52bc7b1c6ca3 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -111,19 +111,21 @@ static const s8 da850_queue_priority_mapping[][2] = {
111 {-1, -1} 111 {-1, -1}
112}; 112};
113 113
114static struct edma_soc_info da830_edma_info[] = { 114static struct edma_soc_info da830_edma_cc0_info = {
115 { 115 .n_channel = 32,
116 .n_channel = 32, 116 .n_region = 4,
117 .n_region = 4, 117 .n_slot = 128,
118 .n_slot = 128, 118 .n_tc = 2,
119 .n_tc = 2, 119 .n_cc = 1,
120 .n_cc = 1, 120 .queue_tc_mapping = da8xx_queue_tc_mapping,
121 .queue_tc_mapping = da8xx_queue_tc_mapping, 121 .queue_priority_mapping = da8xx_queue_priority_mapping,
122 .queue_priority_mapping = da8xx_queue_priority_mapping, 122};
123 }, 123
124static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
125 &da830_edma_cc0_info,
124}; 126};
125 127
126static struct edma_soc_info da850_edma_info[] = { 128static struct edma_soc_info da850_edma_cc_info[] = {
127 { 129 {
128 .n_channel = 32, 130 .n_channel = 32,
129 .n_region = 4, 131 .n_region = 4,
@@ -144,6 +146,11 @@ static struct edma_soc_info da850_edma_info[] = {
144 }, 146 },
145}; 147};
146 148
149static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
150 &da850_edma_cc_info[0],
151 &da850_edma_cc_info[1],
152};
153
147static struct resource da830_edma_resources[] = { 154static struct resource da830_edma_resources[] = {
148 { 155 {
149 .name = "edma_cc0", 156 .name = "edma_cc0",
@@ -248,18 +255,21 @@ static struct platform_device da850_edma_device = {
248 .resource = da850_edma_resources, 255 .resource = da850_edma_resources,
249}; 256};
250 257
251int __init da8xx_register_edma(void) 258int __init da830_register_edma(struct edma_rsv_info *rsv)
252{ 259{
253 struct platform_device *pdev; 260 da830_edma_cc0_info.rsv = rsv;
254 261
255 if (cpu_is_davinci_da830()) 262 return platform_device_register(&da830_edma_device);
256 pdev = &da830_edma_device; 263}
257 else if (cpu_is_davinci_da850())
258 pdev = &da850_edma_device;
259 else
260 return -ENODEV;
261 264
262 return platform_device_register(pdev); 265int __init da850_register_edma(struct edma_rsv_info *rsv[2])
266{
267 if (rsv) {
268 da850_edma_cc_info[0].rsv = rsv[0];
269 da850_edma_cc_info[1].rsv = rsv[1];
270 }
271
272 return platform_device_register(&da850_edma_device);
263} 273}
264 274
265static struct resource da8xx_i2c_resources0[] = { 275static struct resource da8xx_i2c_resources0[] = {
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
new file mode 100644
index 000000000000..2718a3a90dff
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -0,0 +1,320 @@
1/*
2 * Texas Instruments TNETV107X SoC devices
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/clk.h>
20#include <linux/slab.h>
21
22#include <mach/common.h>
23#include <mach/irqs.h>
24#include <mach/edma.h>
25#include <mach/tnetv107x.h>
26
27#include "clock.h"
28
29/* Base addresses for on-chip devices */
30#define TNETV107X_TPCC_BASE 0x01c00000
31#define TNETV107X_TPTC0_BASE 0x01c10000
32#define TNETV107X_TPTC1_BASE 0x01c10400
33#define TNETV107X_WDOG_BASE 0x08086700
34#define TNETV107X_SDIO0_BASE 0x08088700
35#define TNETV107X_SDIO1_BASE 0x08088800
36#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
37#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
38#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
39#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
40#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
41
42/* TNETV107X specific EDMA3 information */
43#define EDMA_TNETV107X_NUM_DMACH 64
44#define EDMA_TNETV107X_NUM_TCC 64
45#define EDMA_TNETV107X_NUM_PARAMENTRY 128
46#define EDMA_TNETV107X_NUM_EVQUE 2
47#define EDMA_TNETV107X_NUM_TC 2
48#define EDMA_TNETV107X_CHMAP_EXIST 0
49#define EDMA_TNETV107X_NUM_REGIONS 4
50#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u
51#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu
52
53#define TNETV107X_DMACH_SDIO0_RX 26
54#define TNETV107X_DMACH_SDIO0_TX 27
55#define TNETV107X_DMACH_SDIO1_RX 28
56#define TNETV107X_DMACH_SDIO1_TX 29
57
58static const s8 edma_tc_mapping[][2] = {
59 /* event queue no TC no */
60 { 0, 0 },
61 { 1, 1 },
62 { -1, -1 }
63};
64
65static const s8 edma_priority_mapping[][2] = {
66 /* event queue no Prio */
67 { 0, 3 },
68 { 1, 7 },
69 { -1, -1 }
70};
71
72static struct edma_soc_info edma_cc0_info = {
73 .n_channel = EDMA_TNETV107X_NUM_DMACH,
74 .n_region = EDMA_TNETV107X_NUM_REGIONS,
75 .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY,
76 .n_tc = EDMA_TNETV107X_NUM_TC,
77 .n_cc = 1,
78 .queue_tc_mapping = edma_tc_mapping,
79 .queue_priority_mapping = edma_priority_mapping,
80};
81
82static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
83 &edma_cc0_info,
84};
85
86static struct resource edma_resources[] = {
87 {
88 .name = "edma_cc0",
89 .start = TNETV107X_TPCC_BASE,
90 .end = TNETV107X_TPCC_BASE + SZ_32K - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 {
94 .name = "edma_tc0",
95 .start = TNETV107X_TPTC0_BASE,
96 .end = TNETV107X_TPTC0_BASE + SZ_1K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99 {
100 .name = "edma_tc1",
101 .start = TNETV107X_TPTC1_BASE,
102 .end = TNETV107X_TPTC1_BASE + SZ_1K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 {
106 .name = "edma0",
107 .start = IRQ_TNETV107X_TPCC,
108 .flags = IORESOURCE_IRQ,
109 },
110 {
111 .name = "edma0_err",
112 .start = IRQ_TNETV107X_TPCC_ERR,
113 .flags = IORESOURCE_IRQ,
114 },
115};
116
117static struct platform_device edma_device = {
118 .name = "edma",
119 .id = -1,
120 .num_resources = ARRAY_SIZE(edma_resources),
121 .resource = edma_resources,
122 .dev.platform_data = tnetv107x_edma_info,
123};
124
125static struct plat_serial8250_port serial_data[] = {
126 {
127 .mapbase = TNETV107X_UART0_BASE,
128 .irq = IRQ_TNETV107X_UART0,
129 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
130 UPF_FIXED_TYPE | UPF_IOREMAP,
131 .type = PORT_AR7,
132 .iotype = UPIO_MEM32,
133 .regshift = 2,
134 },
135 {
136 .mapbase = TNETV107X_UART1_BASE,
137 .irq = IRQ_TNETV107X_UART1,
138 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
139 UPF_FIXED_TYPE | UPF_IOREMAP,
140 .type = PORT_AR7,
141 .iotype = UPIO_MEM32,
142 .regshift = 2,
143 },
144 {
145 .mapbase = TNETV107X_UART2_BASE,
146 .irq = IRQ_TNETV107X_UART2,
147 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
148 UPF_FIXED_TYPE | UPF_IOREMAP,
149 .type = PORT_AR7,
150 .iotype = UPIO_MEM32,
151 .regshift = 2,
152 },
153 {
154 .flags = 0,
155 },
156};
157
158struct platform_device tnetv107x_serial_device = {
159 .name = "serial8250",
160 .id = PLAT8250_DEV_PLATFORM,
161 .dev.platform_data = serial_data,
162};
163
164static struct resource mmc0_resources[] = {
165 { /* Memory mapped registers */
166 .start = TNETV107X_SDIO0_BASE,
167 .end = TNETV107X_SDIO0_BASE + 0x0ff,
168 .flags = IORESOURCE_MEM
169 },
170 { /* MMC interrupt */
171 .start = IRQ_TNETV107X_MMC0,
172 .flags = IORESOURCE_IRQ
173 },
174 { /* SDIO interrupt */
175 .start = IRQ_TNETV107X_SDIO0,
176 .flags = IORESOURCE_IRQ
177 },
178 { /* DMA RX */
179 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
180 .flags = IORESOURCE_DMA
181 },
182 { /* DMA TX */
183 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
184 .flags = IORESOURCE_DMA
185 },
186};
187
188static struct resource mmc1_resources[] = {
189 { /* Memory mapped registers */
190 .start = TNETV107X_SDIO1_BASE,
191 .end = TNETV107X_SDIO1_BASE + 0x0ff,
192 .flags = IORESOURCE_MEM
193 },
194 { /* MMC interrupt */
195 .start = IRQ_TNETV107X_MMC1,
196 .flags = IORESOURCE_IRQ
197 },
198 { /* SDIO interrupt */
199 .start = IRQ_TNETV107X_SDIO1,
200 .flags = IORESOURCE_IRQ
201 },
202 { /* DMA RX */
203 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
204 .flags = IORESOURCE_DMA
205 },
206 { /* DMA TX */
207 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
208 .flags = IORESOURCE_DMA
209 },
210};
211
212static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
213static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
214
215static struct platform_device mmc_devices[2] = {
216 {
217 .name = "davinci_mmc",
218 .id = 0,
219 .dev = {
220 .dma_mask = &mmc0_dma_mask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
222 },
223 .num_resources = ARRAY_SIZE(mmc0_resources),
224 .resource = mmc0_resources
225 },
226 {
227 .name = "davinci_mmc",
228 .id = 1,
229 .dev = {
230 .dma_mask = &mmc1_dma_mask,
231 .coherent_dma_mask = DMA_BIT_MASK(32),
232 },
233 .num_resources = ARRAY_SIZE(mmc1_resources),
234 .resource = mmc1_resources
235 },
236};
237
238static const u32 emif_windows[] = {
239 TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
240 TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
241};
242
243static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
244
245static struct resource wdt_resources[] = {
246 {
247 .start = TNETV107X_WDOG_BASE,
248 .end = TNETV107X_WDOG_BASE + SZ_4K - 1,
249 .flags = IORESOURCE_MEM,
250 },
251};
252
253struct platform_device tnetv107x_wdt_device = {
254 .name = "tnetv107x_wdt",
255 .id = 0,
256 .num_resources = ARRAY_SIZE(wdt_resources),
257 .resource = wdt_resources,
258};
259
260static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
261{
262 struct resource res[2];
263 struct platform_device *pdev;
264 u32 range;
265 int ret;
266
267 /* Figure out the resource range from the ale/cle masks */
268 range = max(data->mask_cle, data->mask_ale);
269 range = PAGE_ALIGN(range + 4) - 1;
270
271 if (range >= emif_window_sizes[chipsel])
272 return -EINVAL;
273
274 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
275 if (!pdev)
276 return -ENOMEM;
277
278 pdev->name = "davinci_nand";
279 pdev->id = chipsel;
280 pdev->dev.platform_data = data;
281
282 memset(res, 0, sizeof(res));
283
284 res[0].start = emif_windows[chipsel];
285 res[0].end = res[0].start + range;
286 res[0].flags = IORESOURCE_MEM;
287
288 res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
289 res[1].end = res[1].start + SZ_4K - 1;
290 res[1].flags = IORESOURCE_MEM;
291
292 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
293 if (ret < 0) {
294 kfree(pdev);
295 return ret;
296 }
297
298 return platform_device_register(pdev);
299}
300
301void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
302{
303 int i;
304
305 platform_device_register(&edma_device);
306 platform_device_register(&tnetv107x_wdt_device);
307
308 if (info->serial_config)
309 davinci_serial_init(info->serial_config);
310
311 for (i = 0; i < 2; i++)
312 if (info->mmc_config[i]) {
313 mmc_devices[i].dev.platform_data = info->mmc_config[i];
314 platform_device_register(&mmc_devices[i]);
315 }
316
317 for (i = 0; i < 4; i++)
318 if (info->nand_config[i])
319 nand_init(i, info->nand_config[i]);
320}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 383478116ef5..3d996b659ff4 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -591,16 +591,18 @@ queue_priority_mapping[][2] = {
591 {-1, -1}, 591 {-1, -1},
592}; 592};
593 593
594static struct edma_soc_info dm355_edma_info[] = { 594static struct edma_soc_info edma_cc0_info = {
595 { 595 .n_channel = 64,
596 .n_channel = 64, 596 .n_region = 4,
597 .n_region = 4, 597 .n_slot = 128,
598 .n_slot = 128, 598 .n_tc = 2,
599 .n_tc = 2, 599 .n_cc = 1,
600 .n_cc = 1, 600 .queue_tc_mapping = queue_tc_mapping,
601 .queue_tc_mapping = queue_tc_mapping, 601 .queue_priority_mapping = queue_priority_mapping,
602 .queue_priority_mapping = queue_priority_mapping, 602};
603 }, 603
604static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
605 &edma_cc0_info,
604}; 606};
605 607
606static struct resource edma_resources[] = { 608static struct resource edma_resources[] = {
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a146849d78f0..6b6f4c643709 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -822,17 +822,19 @@ dm365_queue_priority_mapping[][2] = {
822 {-1, -1}, 822 {-1, -1},
823}; 823};
824 824
825static struct edma_soc_info dm365_edma_info[] = { 825static struct edma_soc_info edma_cc0_info = {
826 { 826 .n_channel = 64,
827 .n_channel = 64, 827 .n_region = 4,
828 .n_region = 4, 828 .n_slot = 256,
829 .n_slot = 256, 829 .n_tc = 4,
830 .n_tc = 4, 830 .n_cc = 1,
831 .n_cc = 1, 831 .queue_tc_mapping = dm365_queue_tc_mapping,
832 .queue_tc_mapping = dm365_queue_tc_mapping, 832 .queue_priority_mapping = dm365_queue_priority_mapping,
833 .queue_priority_mapping = dm365_queue_priority_mapping, 833 .default_queue = EVENTQ_3,
834 .default_queue = EVENTQ_3, 834};
835 }, 835
836static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
837 &edma_cc0_info,
836}; 838};
837 839
838static struct resource edma_resources[] = { 840static struct resource edma_resources[] = {
@@ -1020,6 +1022,8 @@ static struct davinci_timer_info dm365_timer_info = {
1020 .clocksource_id = T0_TOP, 1022 .clocksource_id = T0_TOP,
1021}; 1023};
1022 1024
1025#define DM365_UART1_BASE (IO_PHYS + 0x106000)
1026
1023static struct plat_serial8250_port dm365_serial_platform_data[] = { 1027static struct plat_serial8250_port dm365_serial_platform_data[] = {
1024 { 1028 {
1025 .mapbase = DAVINCI_UART0_BASE, 1029 .mapbase = DAVINCI_UART0_BASE,
@@ -1030,7 +1034,7 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
1030 .regshift = 2, 1034 .regshift = 2,
1031 }, 1035 },
1032 { 1036 {
1033 .mapbase = DAVINCI_UART1_BASE, 1037 .mapbase = DM365_UART1_BASE,
1034 .irq = IRQ_UARTINT1, 1038 .irq = IRQ_UARTINT1,
1035 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 1039 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1036 UPF_IOREMAP, 1040 UPF_IOREMAP,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 7ad15208b841..40fec315c99a 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -492,16 +492,18 @@ queue_priority_mapping[][2] = {
492 {-1, -1}, 492 {-1, -1},
493}; 493};
494 494
495static struct edma_soc_info dm644x_edma_info[] = { 495static struct edma_soc_info edma_cc0_info = {
496 { 496 .n_channel = 64,
497 .n_channel = 64, 497 .n_region = 4,
498 .n_region = 4, 498 .n_slot = 128,
499 .n_slot = 128, 499 .n_tc = 2,
500 .n_tc = 2, 500 .n_cc = 1,
501 .n_cc = 1, 501 .queue_tc_mapping = queue_tc_mapping,
502 .queue_tc_mapping = queue_tc_mapping, 502 .queue_priority_mapping = queue_priority_mapping,
503 .queue_priority_mapping = queue_priority_mapping, 503};
504 }, 504
505static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
506 &edma_cc0_info,
505}; 507};
506 508
507static struct resource edma_resources[] = { 509static struct resource edma_resources[] = {
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 94045656cff6..e4a3df1872ac 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -529,16 +529,18 @@ dm646x_queue_priority_mapping[][2] = {
529 {-1, -1}, 529 {-1, -1},
530}; 530};
531 531
532static struct edma_soc_info dm646x_edma_info[] = { 532static struct edma_soc_info edma_cc0_info = {
533 { 533 .n_channel = 64,
534 .n_channel = 64, 534 .n_region = 6, /* 0-1, 4-7 */
535 .n_region = 6, /* 0-1, 4-7 */ 535 .n_slot = 512,
536 .n_slot = 512, 536 .n_tc = 4,
537 .n_tc = 4, 537 .n_cc = 1,
538 .n_cc = 1, 538 .queue_tc_mapping = dm646x_queue_tc_mapping,
539 .queue_tc_mapping = dm646x_queue_tc_mapping, 539 .queue_priority_mapping = dm646x_queue_priority_mapping,
540 .queue_priority_mapping = dm646x_queue_priority_mapping, 540};
541 }, 541
542static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
543 &edma_cc0_info,
542}; 544};
543 545
544static struct resource edma_resources[] = { 546static struct resource edma_resources[] = {
@@ -877,6 +879,13 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
877 platform_device_register(&vpif_capture_dev); 879 platform_device_register(&vpif_capture_dev);
878} 880}
879 881
882int __init dm646x_init_edma(struct edma_rsv_info *rsv)
883{
884 edma_cc0_info.rsv = rsv;
885
886 return platform_device_register(&dm646x_edma_device);
887}
888
880void __init dm646x_init(void) 889void __init dm646x_init(void)
881{ 890{
882 dm646x_board_setup_refclk(&ref_clk); 891 dm646x_board_setup_refclk(&ref_clk);
@@ -888,7 +897,6 @@ static int __init dm646x_init_devices(void)
888 if (!cpu_is_davinci_dm646x()) 897 if (!cpu_is_davinci_dm646x())
889 return 0; 898 return 0;
890 899
891 platform_device_register(&dm646x_edma_device);
892 platform_device_register(&dm646x_emac_device); 900 platform_device_register(&dm646x_emac_device);
893 return 0; 901 return 0;
894} 902}
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index d33827aadda7..2ede598b77dd 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -99,8 +99,6 @@
99 99
100#define EDMA_MAX_DMACH 64 100#define EDMA_MAX_DMACH 64
101#define EDMA_MAX_PARAMENTRY 512 101#define EDMA_MAX_PARAMENTRY 512
102#define EDMA_MAX_CC 2
103
104 102
105/*****************************************************************************/ 103/*****************************************************************************/
106 104
@@ -207,6 +205,18 @@ static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
207 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); 205 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
208} 206}
209 207
208static inline void set_bits(int offset, int len, unsigned long *p)
209{
210 for (; len > 0; len--)
211 set_bit(offset + (len - 1), p);
212}
213
214static inline void clear_bits(int offset, int len, unsigned long *p)
215{
216 for (; len > 0; len--)
217 clear_bit(offset + (len - 1), p);
218}
219
210/*****************************************************************************/ 220/*****************************************************************************/
211 221
212/* actual number of DMA channels and slots on this silicon */ 222/* actual number of DMA channels and slots on this silicon */
@@ -1376,11 +1386,13 @@ EXPORT_SYMBOL(edma_clear_event);
1376 1386
1377static int __init edma_probe(struct platform_device *pdev) 1387static int __init edma_probe(struct platform_device *pdev)
1378{ 1388{
1379 struct edma_soc_info *info = pdev->dev.platform_data; 1389 struct edma_soc_info **info = pdev->dev.platform_data;
1380 const s8 (*queue_priority_mapping)[2]; 1390 const s8 (*queue_priority_mapping)[2];
1381 const s8 (*queue_tc_mapping)[2]; 1391 const s8 (*queue_tc_mapping)[2];
1382 int i, j, found = 0; 1392 int i, j, off, ln, found = 0;
1383 int status = -1; 1393 int status = -1;
1394 const s16 (*rsv_chans)[2];
1395 const s16 (*rsv_slots)[2];
1384 int irq[EDMA_MAX_CC] = {0, 0}; 1396 int irq[EDMA_MAX_CC] = {0, 0};
1385 int err_irq[EDMA_MAX_CC] = {0, 0}; 1397 int err_irq[EDMA_MAX_CC] = {0, 0};
1386 struct resource *r[EDMA_MAX_CC] = {NULL}; 1398 struct resource *r[EDMA_MAX_CC] = {NULL};
@@ -1395,7 +1407,7 @@ static int __init edma_probe(struct platform_device *pdev)
1395 sprintf(res_name, "edma_cc%d", j); 1407 sprintf(res_name, "edma_cc%d", j);
1396 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1408 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1397 res_name); 1409 res_name);
1398 if (!r[j]) { 1410 if (!r[j] || !info[j]) {
1399 if (found) 1411 if (found)
1400 break; 1412 break;
1401 else 1413 else
@@ -1426,13 +1438,14 @@ static int __init edma_probe(struct platform_device *pdev)
1426 } 1438 }
1427 memset(edma_cc[j], 0, sizeof(struct edma)); 1439 memset(edma_cc[j], 0, sizeof(struct edma));
1428 1440
1429 edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel, 1441 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1430 EDMA_MAX_DMACH); 1442 EDMA_MAX_DMACH);
1431 edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot, 1443 edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1432 EDMA_MAX_PARAMENTRY); 1444 EDMA_MAX_PARAMENTRY);
1433 edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC); 1445 edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1446 EDMA_MAX_CC);
1434 1447
1435 edma_cc[j]->default_queue = info[j].default_queue; 1448 edma_cc[j]->default_queue = info[j]->default_queue;
1436 if (!edma_cc[j]->default_queue) 1449 if (!edma_cc[j]->default_queue)
1437 edma_cc[j]->default_queue = EVENTQ_1; 1450 edma_cc[j]->default_queue = EVENTQ_1;
1438 1451
@@ -1447,6 +1460,31 @@ static int __init edma_probe(struct platform_device *pdev)
1447 memset(edma_cc[j]->edma_unused, 0xff, 1460 memset(edma_cc[j]->edma_unused, 0xff,
1448 sizeof(edma_cc[j]->edma_unused)); 1461 sizeof(edma_cc[j]->edma_unused));
1449 1462
1463 if (info[j]->rsv) {
1464
1465 /* Clear the reserved channels in unused list */
1466 rsv_chans = info[j]->rsv->rsv_chans;
1467 if (rsv_chans) {
1468 for (i = 0; rsv_chans[i][0] != -1; i++) {
1469 off = rsv_chans[i][0];
1470 ln = rsv_chans[i][1];
1471 clear_bits(off, ln,
1472 edma_cc[j]->edma_unused);
1473 }
1474 }
1475
1476 /* Set the reserved slots in inuse list */
1477 rsv_slots = info[j]->rsv->rsv_slots;
1478 if (rsv_slots) {
1479 for (i = 0; rsv_slots[i][0] != -1; i++) {
1480 off = rsv_slots[i][0];
1481 ln = rsv_slots[i][1];
1482 set_bits(off, ln,
1483 edma_cc[j]->edma_inuse);
1484 }
1485 }
1486 }
1487
1450 sprintf(irq_name, "edma%d", j); 1488 sprintf(irq_name, "edma%d", j);
1451 irq[j] = platform_get_irq_byname(pdev, irq_name); 1489 irq[j] = platform_get_irq_byname(pdev, irq_name);
1452 edma_cc[j]->irq_res_start = irq[j]; 1490 edma_cc[j]->irq_res_start = irq[j];
@@ -1476,8 +1514,8 @@ static int __init edma_probe(struct platform_device *pdev)
1476 for (i = 0; i < edma_cc[j]->num_channels; i++) 1514 for (i = 0; i < edma_cc[j]->num_channels; i++)
1477 map_dmach_queue(j, i, EVENTQ_1); 1515 map_dmach_queue(j, i, EVENTQ_1);
1478 1516
1479 queue_tc_mapping = info[j].queue_tc_mapping; 1517 queue_tc_mapping = info[j]->queue_tc_mapping;
1480 queue_priority_mapping = info[j].queue_priority_mapping; 1518 queue_priority_mapping = info[j]->queue_priority_mapping;
1481 1519
1482 /* Event queue to TC mapping */ 1520 /* Event queue to TC mapping */
1483 for (i = 0; queue_tc_mapping[i][0] != -1; i++) 1521 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
@@ -1496,7 +1534,7 @@ static int __init edma_probe(struct platform_device *pdev)
1496 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) 1534 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1497 map_dmach_param(j); 1535 map_dmach_param(j);
1498 1536
1499 for (i = 0; i < info[j].n_region; i++) { 1537 for (i = 0; i < info[j]->n_region; i++) {
1500 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); 1538 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1501 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); 1539 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1502 edma_write_array(j, EDMA_QRAE, i, 0x0); 1540 edma_write_array(j, EDMA_QRAE, i, 0x0);
diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c
new file mode 100644
index 000000000000..d10298620e2c
--- /dev/null
+++ b/arch/arm/mach-davinci/gpio-tnetv107x.c
@@ -0,0 +1,205 @@
1/*
2 * Texas Instruments TNETV107X GPIO Controller
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18
19#include <mach/common.h>
20#include <mach/tnetv107x.h>
21
22struct tnetv107x_gpio_regs {
23 u32 idver;
24 u32 data_in[3];
25 u32 data_out[3];
26 u32 direction[3];
27 u32 enable[3];
28};
29
30#define gpio_reg_index(gpio) ((gpio) >> 5)
31#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f)
32
33#define gpio_reg_rmw(reg, mask, val) \
34 __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
35
36#define gpio_reg_set_bit(reg, gpio) \
37 gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
38
39#define gpio_reg_clear_bit(reg, gpio) \
40 gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
41
42#define gpio_reg_get_bit(reg, gpio) \
43 (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
44
45#define chip2controller(chip) \
46 container_of(chip, struct davinci_gpio_controller, chip)
47
48#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
49
50static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
51
52static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
53{
54 struct davinci_gpio_controller *ctlr = chip2controller(chip);
55 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
56 unsigned gpio = chip->base + offset;
57 unsigned long flags;
58
59 spin_lock_irqsave(&ctlr->lock, flags);
60
61 gpio_reg_set_bit(&regs->enable, gpio);
62
63 spin_unlock_irqrestore(&ctlr->lock, flags);
64
65 return 0;
66}
67
68static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
69{
70 struct davinci_gpio_controller *ctlr = chip2controller(chip);
71 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
72 unsigned gpio = chip->base + offset;
73 unsigned long flags;
74
75 spin_lock_irqsave(&ctlr->lock, flags);
76
77 gpio_reg_clear_bit(&regs->enable, gpio);
78
79 spin_unlock_irqrestore(&ctlr->lock, flags);
80}
81
82static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
83{
84 struct davinci_gpio_controller *ctlr = chip2controller(chip);
85 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
86 unsigned gpio = chip->base + offset;
87 unsigned long flags;
88
89 spin_lock_irqsave(&ctlr->lock, flags);
90
91 gpio_reg_set_bit(&regs->direction, gpio);
92
93 spin_unlock_irqrestore(&ctlr->lock, flags);
94
95 return 0;
96}
97
98static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
99 unsigned offset, int value)
100{
101 struct davinci_gpio_controller *ctlr = chip2controller(chip);
102 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
103 unsigned gpio = chip->base + offset;
104 unsigned long flags;
105
106 spin_lock_irqsave(&ctlr->lock, flags);
107
108 if (value)
109 gpio_reg_set_bit(&regs->data_out, gpio);
110 else
111 gpio_reg_clear_bit(&regs->data_out, gpio);
112
113 gpio_reg_clear_bit(&regs->direction, gpio);
114
115 spin_unlock_irqrestore(&ctlr->lock, flags);
116
117 return 0;
118}
119
120static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
121{
122 struct davinci_gpio_controller *ctlr = chip2controller(chip);
123 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
124 unsigned gpio = chip->base + offset;
125 int ret;
126
127 ret = gpio_reg_get_bit(&regs->data_in, gpio);
128
129 return ret ? 1 : 0;
130}
131
132static void tnetv107x_gpio_set(struct gpio_chip *chip,
133 unsigned offset, int value)
134{
135 struct davinci_gpio_controller *ctlr = chip2controller(chip);
136 struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
137 unsigned gpio = chip->base + offset;
138 unsigned long flags;
139
140 spin_lock_irqsave(&ctlr->lock, flags);
141
142 if (value)
143 gpio_reg_set_bit(&regs->data_out, gpio);
144 else
145 gpio_reg_clear_bit(&regs->data_out, gpio);
146
147 spin_unlock_irqrestore(&ctlr->lock, flags);
148}
149
150static int __init tnetv107x_gpio_setup(void)
151{
152 int i, base;
153 unsigned ngpio;
154 struct davinci_soc_info *soc_info = &davinci_soc_info;
155 struct tnetv107x_gpio_regs *regs;
156 struct davinci_gpio_controller *ctlr;
157
158 if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
159 return 0;
160
161 ngpio = soc_info->gpio_num;
162 if (ngpio == 0) {
163 pr_err("GPIO setup: how many GPIOs?\n");
164 return -EINVAL;
165 }
166
167 if (WARN_ON(TNETV107X_N_GPIO < ngpio))
168 ngpio = TNETV107X_N_GPIO;
169
170 regs = ioremap(soc_info->gpio_base, SZ_4K);
171 if (WARN_ON(!regs))
172 return -EINVAL;
173
174 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
175 ctlr = &chips[i];
176
177 ctlr->chip.label = "tnetv107x";
178 ctlr->chip.can_sleep = 0;
179 ctlr->chip.base = base;
180 ctlr->chip.ngpio = ngpio - base;
181 if (ctlr->chip.ngpio > 32)
182 ctlr->chip.ngpio = 32;
183
184 ctlr->chip.request = tnetv107x_gpio_request;
185 ctlr->chip.free = tnetv107x_gpio_free;
186 ctlr->chip.direction_input = tnetv107x_gpio_dir_in;
187 ctlr->chip.get = tnetv107x_gpio_get;
188 ctlr->chip.direction_output = tnetv107x_gpio_dir_out;
189 ctlr->chip.set = tnetv107x_gpio_set;
190
191 spin_lock_init(&ctlr->lock);
192
193 ctlr->regs = regs;
194 ctlr->set_data = &regs->data_out[i];
195 ctlr->clr_data = &regs->data_out[i];
196 ctlr->in_data = &regs->data_in[i];
197
198 gpiochip_add(&ctlr->chip);
199 }
200
201 soc_info->gpio_ctlrs = chips;
202 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
203 return 0;
204}
205pure_initcall(tnetv107x_gpio_setup);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 1b31a9aa8fba..3c07059f526e 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -67,7 +67,8 @@ extern void __iomem *da8xx_syscfg1_base;
67void __init da830_init(void); 67void __init da830_init(void);
68void __init da850_init(void); 68void __init da850_init(void);
69 69
70int da8xx_register_edma(void); 70int da830_register_edma(struct edma_rsv_info *rsv);
71int da850_register_edma(struct edma_rsv_info *rsv[2]);
71int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 72int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
72int da8xx_register_watchdog(void); 73int da8xx_register_watchdog(void);
73int da8xx_register_usb20(unsigned mA, unsigned potpgt); 74int da8xx_register_usb20(unsigned mA, unsigned potpgt);
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 3cd93a801d9b..f761dfdb8689 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -17,22 +17,50 @@
17 */ 17 */
18 18
19#include <linux/serial_reg.h> 19#include <linux/serial_reg.h>
20
21#include <asm/memory.h>
22
23#include <mach/serial.h>
24
20#define UART_SHIFT 2 25#define UART_SHIFT 2
21 26
27 .pushsection .data
28davinci_uart_phys: .word 0
29davinci_uart_virt: .word 0
30 .popsection
31
22 .macro addruart, rx, tmp 32 .macro addruart, rx, tmp
33
34 /* Use davinci_uart_phys/virt if already configured */
3510: mrc p15, 0, \rx, c1, c0
36 tst \rx, #1 @ MMU enabled?
37 ldreq \rx, =__virt_to_phys(davinci_uart_phys)
38 ldrne \rx, =davinci_uart_virt
39 ldr \rx, [\rx]
40 cmp \rx, #0 @ is port configured?
41 bne 99f @ already configured
42
23 mrc p15, 0, \rx, c1, c0 43 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1 @ MMU enabled? 44 tst \rx, #1 @ MMU enabled?
25 moveq \rx, #0x01000000 @ physical base address 45
26 movne \rx, #0xfe000000 @ virtual base 46 /* Copy uart phys address from decompressor uart info */
27#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) 47 ldreq \tmp, =__virt_to_phys(davinci_uart_phys)
28#error Cannot enable DaVinci and DA8XX platforms concurrently 48 ldrne \tmp, =davinci_uart_phys
29#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ 49 ldreq \rx, =DAVINCI_UART_INFO
30 defined(CONFIG_MACH_DAVINCI_DA850_EVM) 50 ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO)
31 orr \rx, \rx, #0x00d00000 @ physical base address 51 ldr \rx, [\rx, #0]
32 orr \rx, \rx, #0x0000d000 @ of UART 2 52 str \rx, [\tmp]
33#else 53
34 orr \rx, \rx, #0x00c20000 @ UART 0 54 /* Copy uart virt address from decompressor uart info */
35#endif 55 ldreq \tmp, =__virt_to_phys(davinci_uart_virt)
56 ldrne \tmp, =davinci_uart_virt
57 ldreq \rx, =DAVINCI_UART_INFO
58 ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO)
59 ldr \rx, [\rx, #4]
60 str \rx, [\tmp]
61
62 b 10b
6399:
36 .endm 64 .endm
37 65
38 .macro senduart,rd,rx 66 .macro senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index add6f794a362..0a27ee9a70e1 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -32,6 +32,7 @@ void __init dm646x_init(void);
32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk); 34void __init dm646x_board_setup_refclk(struct clk *clk);
35int __init dm646x_init_edma(struct edma_rsv_info *rsv);
35 36
36void dm646x_video_init(void); 37void dm646x_video_init(void);
37 38
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index ced3092af5ba..dc10ef6cf572 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -230,6 +230,8 @@ enum sync_dimension {
230#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 230#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
231#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 231#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
232 232
233#define EDMA_MAX_CC 2
234
233/* alloc/free DMA channels and their dedicated parameter RAM slots */ 235/* alloc/free DMA channels and their dedicated parameter RAM slots */
234int edma_alloc_channel(int channel, 236int edma_alloc_channel(int channel,
235 void (*callback)(unsigned channel, u16 ch_status, void *data), 237 void (*callback)(unsigned channel, u16 ch_status, void *data),
@@ -269,6 +271,12 @@ void edma_clear_event(unsigned channel);
269void edma_pause(unsigned channel); 271void edma_pause(unsigned channel);
270void edma_resume(unsigned channel); 272void edma_resume(unsigned channel);
271 273
274struct edma_rsv_info {
275
276 const s16 (*rsv_chans)[2];
277 const s16 (*rsv_slots)[2];
278};
279
272/* platform_data for EDMA driver */ 280/* platform_data for EDMA driver */
273struct edma_soc_info { 281struct edma_soc_info {
274 282
@@ -280,6 +288,9 @@ struct edma_soc_info {
280 unsigned n_cc; 288 unsigned n_cc;
281 enum dma_event_q default_queue; 289 enum dma_event_q default_queue;
282 290
291 /* Resource reservation for other cores */
292 struct edma_rsv_info *rsv;
293
283 const s8 (*queue_tc_mapping)[2]; 294 const s8 (*queue_tc_mapping)[2];
284 const s8 (*queue_priority_mapping)[2]; 295 const s8 (*queue_priority_mapping)[2];
285}; 296};
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 504cc180a60b..fbece126c2bf 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -25,6 +25,7 @@
25 25
26enum davinci_gpio_type { 26enum davinci_gpio_type {
27 GPIO_TYPE_DAVINCI = 0, 27 GPIO_TYPE_DAVINCI = 0,
28 GPIO_TYPE_TNETV107X,
28}; 29};
29 30
30/* 31/*
@@ -87,9 +88,13 @@ static inline u32 __gpio_mask(unsigned gpio)
87 return 1 << (gpio % 32); 88 return 1 << (gpio % 32);
88} 89}
89 90
90/* The get/set/clear functions will inline when called with constant 91/*
92 * The get/set/clear functions will inline when called with constant
91 * parameters referencing built-in GPIOs, for low-overhead bitbanging. 93 * parameters referencing built-in GPIOs, for low-overhead bitbanging.
92 * 94 *
95 * gpio_set_value() will inline only on traditional Davinci style controllers
96 * with distinct set/clear registers.
97 *
93 * Otherwise, calls with variable parameters or referencing external 98 * Otherwise, calls with variable parameters or referencing external
94 * GPIOs (e.g. on GPIO expander chips) use outlined functions. 99 * GPIOs (e.g. on GPIO expander chips) use outlined functions.
95 */ 100 */
@@ -100,12 +105,15 @@ static inline void gpio_set_value(unsigned gpio, int value)
100 u32 mask; 105 u32 mask;
101 106
102 ctlr = __gpio_to_controller(gpio); 107 ctlr = __gpio_to_controller(gpio);
103 mask = __gpio_mask(gpio); 108
104 if (value) 109 if (ctlr->set_data != ctlr->clr_data) {
105 __raw_writel(mask, ctlr->set_data); 110 mask = __gpio_mask(gpio);
106 else 111 if (value)
107 __raw_writel(mask, ctlr->clr_data); 112 __raw_writel(mask, ctlr->set_data);
108 return; 113 else
114 __raw_writel(mask, ctlr->clr_data);
115 return;
116 }
109 } 117 }
110 118
111 __gpio_set_value(gpio, value); 119 __gpio_set_value(gpio, value);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index f6c4f34909a2..8051110b8ac3 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,8 +11,19 @@
11#ifndef __ASM_ARCH_SERIAL_H 11#ifndef __ASM_ARCH_SERIAL_H
12#define __ASM_ARCH_SERIAL_H 12#define __ASM_ARCH_SERIAL_H
13 13
14#include <asm/memory.h>
15
14#include <mach/hardware.h> 16#include <mach/hardware.h>
15 17
18/*
19 * Stolen area that contains debug uart physical and virtual addresses. These
20 * addresses are filled in by the uncompress.h code, and are used by the debug
21 * macros in debug-macro.S.
22 *
23 * This area sits just below the page tables (see arch/arm/kernel/head.S).
24 */
25#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8)
26
16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 27#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 28#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 29#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
@@ -21,16 +32,26 @@
21#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) 32#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
22#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) 33#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
23 34
35#define TNETV107X_UART0_BASE 0x08108100
36#define TNETV107X_UART1_BASE 0x08088400
37#define TNETV107X_UART2_BASE 0x08108300
38
39#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
40#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
41#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
42
24/* DaVinci UART register offsets */ 43/* DaVinci UART register offsets */
25#define UART_DAVINCI_PWREMU 0x0c 44#define UART_DAVINCI_PWREMU 0x0c
26#define UART_DM646X_SCR 0x10 45#define UART_DM646X_SCR 0x10
27#define UART_DM646X_SCR_TX_WATERMARK 0x08 46#define UART_DM646X_SCR_TX_WATERMARK 0x08
28 47
48#ifndef __ASSEMBLY__
29struct davinci_uart_config { 49struct davinci_uart_config {
30 /* Bit field of UARTs present; bit 0 --> UART1 */ 50 /* Bit field of UARTs present; bit 0 --> UART1 */
31 unsigned int enabled_uarts; 51 unsigned int enabled_uarts;
32}; 52};
33 53
34extern int davinci_serial_init(struct davinci_uart_config *); 54extern int davinci_serial_init(struct davinci_uart_config *);
55#endif
35 56
36#endif /* __ASM_ARCH_SERIAL_H */ 57#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
new file mode 100644
index 000000000000..c72064733123
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -0,0 +1,55 @@
1/*
2 * Texas Instruments TNETV107X SoC Specific Defines
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
16#define __ASM_ARCH_DAVINCI_TNETV107X_H
17
18#include <asm/sizes.h>
19
20#define TNETV107X_DDR_BASE 0x80000000
21
22/*
23 * Fixed mapping for early init starts here. If low-level debug is enabled,
24 * this area also gets mapped via io_pg_offset and io_phys by the boot code.
25 * To fit in with the io_pg_offset calculation, the io base address selected
26 * here _must_ be a multiple of 2^20.
27 */
28#define TNETV107X_IO_BASE 0x08000000
29#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
30
31#define TNETV107X_N_GPIO 65
32
33#ifndef __ASSEMBLY__
34
35#include <linux/serial_8250.h>
36#include <mach/mmc.h>
37#include <mach/nand.h>
38#include <mach/serial.h>
39
40struct tnetv107x_device_info {
41 struct davinci_uart_config *serial_config;
42 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
43 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
44};
45
46extern struct platform_device tnetv107x_wdt_device;
47extern struct platform_device tnetv107x_serial_device;
48
49extern void __init tnetv107x_init(void);
50extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
51extern void __init tnetv107x_irq_init(void);
52
53#endif
54
55#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 33796b4db17f..15a6192ad6eb 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -1,8 +1,17 @@
1/* 1/*
2 * Serial port stubs for kernel decompress status messages 2 * Serial port stubs for kernel decompress status messages
3 * 3 *
4 * Author: Anant Gole 4 * Initially based on:
5 * (C) Copyright (C) 2006, Texas Instruments, Inc 5 * arch/arm/plat-omap/include/mach/uncompress.h
6 *
7 * Original copyrights follow.
8 *
9 * Copyright (C) 2000 RidgeRun, Inc.
10 * Author: Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Rewritten by:
13 * Author: <source@mvista.com>
14 * 2004 (c) MontaVista Software, Inc.
6 * 15 *
7 * This file is licensed under the terms of the GNU General Public License 16 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 17 * version 2. This program is licensed "as is" without any warranty of any
@@ -11,30 +20,17 @@
11 20
12#include <linux/types.h> 21#include <linux/types.h>
13#include <linux/serial_reg.h> 22#include <linux/serial_reg.h>
14#include <mach/serial.h>
15 23
16#include <asm/mach-types.h> 24#include <asm/mach-types.h>
17 25
18extern unsigned int __machine_arch_type; 26#include <mach/serial.h>
19 27
20static u32 *uart; 28static u32 *uart;
21 29static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
22static u32 *get_uart_base(void)
23{
24 if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
25 __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
26 return (u32 *)DA8XX_UART2_BASE;
27 else
28 return (u32 *)DAVINCI_UART0_BASE;
29}
30 30
31/* PORT_16C550A, in polled non-fifo mode */ 31/* PORT_16C550A, in polled non-fifo mode */
32
33static void putc(char c) 32static void putc(char c)
34{ 33{
35 if (!uart)
36 uart = get_uart_base();
37
38 while (!(uart[UART_LSR] & UART_LSR_THRE)) 34 while (!(uart[UART_LSR] & UART_LSR_THRE))
39 barrier(); 35 barrier();
40 uart[UART_TX] = c; 36 uart[UART_TX] = c;
@@ -42,12 +38,61 @@ static void putc(char c)
42 38
43static inline void flush(void) 39static inline void flush(void)
44{ 40{
45 if (!uart)
46 uart = get_uart_base();
47
48 while (!(uart[UART_LSR] & UART_LSR_THRE)) 41 while (!(uart[UART_LSR] & UART_LSR_THRE))
49 barrier(); 42 barrier();
50} 43}
51 44
52#define arch_decomp_setup() 45static inline void set_uart_info(u32 phys, void * __iomem virt)
46{
47 uart = (u32 *)phys;
48 uart_info[0] = phys;
49 uart_info[1] = (u32)virt;
50}
51
52#define _DEBUG_LL_ENTRY(machine, phys, virt) \
53 if (machine_is_##machine()) { \
54 set_uart_info(phys, virt); \
55 break; \
56 }
57
58#define DEBUG_LL_DAVINCI(machine, port) \
59 _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE, \
60 IO_ADDRESS(DAVINCI_UART##port##_BASE))
61
62#define DEBUG_LL_DA8XX(machine, port) \
63 _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE, \
64 IO_ADDRESS(DA8XX_UART##port##_BASE))
65
66#define DEBUG_LL_TNETV107X(machine, port) \
67 _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE, \
68 TNETV107X_UART##port##_VIRT)
69
70static inline void __arch_decomp_setup(unsigned long arch_id)
71{
72 /*
73 * Initialize the port based on the machine ID from the bootloader.
74 * Note that we're using macros here instead of switch statement
75 * as machine_is functions are optimized out for the boards that
76 * are not selected.
77 */
78 do {
79 /* Davinci boards */
80 DEBUG_LL_DAVINCI(davinci_evm, 0);
81 DEBUG_LL_DAVINCI(sffsdr, 0);
82 DEBUG_LL_DAVINCI(neuros_osd2, 0);
83 DEBUG_LL_DAVINCI(davinci_dm355_evm, 0);
84 DEBUG_LL_DAVINCI(dm355_leopard, 0);
85 DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0);
86 DEBUG_LL_DAVINCI(davinci_dm365_evm, 0);
87
88 /* DA8xx boards */
89 DEBUG_LL_DA8XX(davinci_da830_evm, 2);
90 DEBUG_LL_DA8XX(davinci_da850_evm, 2);
91
92 /* TNETV107x boards */
93 DEBUG_LL_TNETV107X(tnetv107x, 1);
94 } while (0);
95}
96
97#define arch_decomp_setup() __arch_decomp_setup(arch_id)
53#define arch_decomp_wdog() 98#define arch_decomp_wdog()
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 000000000000..864e60482c53
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,753 @@
1/*
2 * Texas Instruments TNETV107X SoC Support
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach/map.h>
23
24#include <mach/common.h>
25#include <mach/time.h>
26#include <mach/cputype.h>
27#include <mach/psc.h>
28#include <mach/cp_intc.h>
29#include <mach/irqs.h>
30#include <mach/gpio.h>
31#include <mach/hardware.h>
32#include <mach/tnetv107x.h>
33
34#include "clock.h"
35#include "mux.h"
36
37/* Base addresses for on-chip devices */
38#define TNETV107X_INTC_BASE 0x03000000
39#define TNETV107X_TIMER0_BASE 0x08086500
40#define TNETV107X_TIMER1_BASE 0x08086600
41#define TNETV107X_CHIP_CFG_BASE 0x08087000
42#define TNETV107X_GPIO_BASE 0x08088000
43#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000
44#define TNETV107X_PSC_BASE 0x0808b000
45
46/* Reference clock frequencies */
47#define OSC_FREQ_ONCHIP (24000 * 1000)
48#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000)
49#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000)
50#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000)
51
52#define N_PLLS 3
53
54/* Clock Control Registers */
55struct clk_ctrl_regs {
56 u32 pll_bypass;
57 u32 _reserved0;
58 u32 gem_lrst;
59 u32 _reserved1;
60 u32 pll_unlock_stat;
61 u32 sys_unlock;
62 u32 eth_unlock;
63 u32 tdm_unlock;
64};
65
66/* SSPLL Registers */
67struct sspll_regs {
68 u32 modes;
69 u32 post_div;
70 u32 pre_div;
71 u32 mult_factor;
72 u32 divider_range;
73 u32 bw_divider;
74 u32 spr_amount;
75 u32 spr_rate_div;
76 u32 diag;
77};
78
79/* Watchdog Timer Registers */
80struct wdt_regs {
81 u32 kick_lock;
82 u32 kick;
83 u32 change_lock;
84 u32 change ;
85 u32 disable_lock;
86 u32 disable;
87 u32 prescale_lock;
88 u32 prescale;
89};
90
91static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
92
93static struct sspll_regs __iomem *sspll_regs[N_PLLS];
94static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
95
96/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
97static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
98
99/* offchip (external) reference clock frequencies */
100static u32 pll_ext_freq[] = {
101 OSC_FREQ_OFFCHIP_SYS,
102 OSC_FREQ_OFFCHIP_TDM,
103 OSC_FREQ_OFFCHIP_ETH
104};
105
106/* PSC control registers */
107static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
108
109/* Host map for interrupt controller */
110static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
111
112static unsigned long clk_sspll_recalc(struct clk *clk);
113
114/* Level 1 - the PLLs */
115#define define_pll_clk(cname, pll, divmask, base) \
116 static struct pll_data pll_##cname##_data = { \
117 .num = pll, \
118 .div_ratio_mask = divmask, \
119 .phys_base = base + \
120 TNETV107X_CLOCK_CONTROL_BASE, \
121 }; \
122 static struct clk pll_##cname##_clk = { \
123 .name = "pll_" #cname "_clk", \
124 .pll_data = &pll_##cname##_data, \
125 .flags = CLK_PLL, \
126 .recalc = clk_sspll_recalc, \
127 }
128
129define_pll_clk(sys, 0, 0x1ff, 0x600);
130define_pll_clk(tdm, 1, 0x0ff, 0x200);
131define_pll_clk(eth, 2, 0x0ff, 0x400);
132
133/* Level 2 - divided outputs from the PLLs */
134#define define_pll_div_clk(pll, cname, div) \
135 static struct clk pll##_##cname##_clk = { \
136 .name = #pll "_" #cname "_clk",\
137 .parent = &pll_##pll##_clk, \
138 .flags = CLK_PLL, \
139 .div_reg = PLLDIV##div, \
140 }
141
142define_pll_div_clk(sys, arm1176, 1);
143define_pll_div_clk(sys, dsp, 2);
144define_pll_div_clk(sys, ddr, 3);
145define_pll_div_clk(sys, full, 4);
146define_pll_div_clk(sys, lcd, 5);
147define_pll_div_clk(sys, vlynq_ref, 6);
148define_pll_div_clk(sys, tsc, 7);
149define_pll_div_clk(sys, half, 8);
150
151define_pll_div_clk(eth, 5mhz, 1);
152define_pll_div_clk(eth, 50mhz, 2);
153define_pll_div_clk(eth, 125mhz, 3);
154define_pll_div_clk(eth, 250mhz, 4);
155define_pll_div_clk(eth, 25mhz, 5);
156
157define_pll_div_clk(tdm, 0, 1);
158define_pll_div_clk(tdm, extra, 2);
159define_pll_div_clk(tdm, 1, 3);
160
161
162/* Level 3 - LPSC gated clocks */
163#define __lpsc_clk(cname, _parent, mod, flg) \
164 static struct clk clk_##cname = { \
165 .name = #cname, \
166 .parent = &_parent, \
167 .lpsc = TNETV107X_LPSC_##mod,\
168 .flags = flg, \
169 }
170
171#define lpsc_clk_enabled(cname, parent, mod) \
172 __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
173
174#define lpsc_clk(cname, parent, mod) \
175 __lpsc_clk(cname, parent, mod, 0)
176
177lpsc_clk_enabled(arm, sys_arm1176_clk, ARM);
178lpsc_clk_enabled(gem, sys_dsp_clk, GEM);
179lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY);
180lpsc_clk_enabled(tpcc, sys_full_clk, TPCC);
181lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0);
182lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1);
183lpsc_clk_enabled(ram, sys_full_clk, RAM);
184lpsc_clk_enabled(aemif, sys_full_clk, AEMIF);
185lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG);
186lpsc_clk_enabled(rom, sys_half_clk, ROM);
187lpsc_clk_enabled(secctl, sys_half_clk, SECCTL);
188lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR);
189lpsc_clk_enabled(gpio, sys_half_clk, GPIO);
190lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS);
191lpsc_clk_enabled(system, sys_half_clk, SYSTEM);
192lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST);
193lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST);
194lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM);
195
196lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE);
197lpsc_clk(ethss, eth_125mhz_clk, ETHSS);
198lpsc_clk(tsc, sys_tsc_clk, TSC);
199lpsc_clk(uart0, sys_half_clk, UART0);
200lpsc_clk(uart1, sys_half_clk, UART1);
201lpsc_clk(uart2, sys_half_clk, UART2);
202lpsc_clk(pktsec, sys_half_clk, PKTSEC);
203lpsc_clk(keypad, sys_half_clk, KEYPAD);
204lpsc_clk(mdio, sys_half_clk, MDIO);
205lpsc_clk(sdio0, sys_half_clk, SDIO0);
206lpsc_clk(sdio1, sys_half_clk, SDIO1);
207lpsc_clk(timer0, sys_half_clk, TIMER0);
208lpsc_clk(timer1, sys_half_clk, TIMER1);
209lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP);
210lpsc_clk(ssp, sys_half_clk, SSP);
211lpsc_clk(tdm0, tdm_0_clk, TDM0);
212lpsc_clk(tdm1, tdm_1_clk, TDM1);
213lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ);
214lpsc_clk(mcdma, sys_half_clk, MCDMA);
215lpsc_clk(usb0, sys_half_clk, USB0);
216lpsc_clk(usb1, sys_half_clk, USB1);
217lpsc_clk(usbss, sys_half_clk, USBSS);
218lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII);
219lpsc_clk(imcop, sys_dsp_clk, IMCOP);
220lpsc_clk(spare, sys_half_clk, SPARE);
221
222/* LCD needs a full power down to clear controller state */
223__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
224
225
226/* Level 4 - leaf clocks for LPSC modules shared across drivers */
227static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
228static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
229
230static struct clk_lookup clks[] = {
231 CLK(NULL, "pll_sys_clk", &pll_sys_clk),
232 CLK(NULL, "pll_eth_clk", &pll_eth_clk),
233 CLK(NULL, "pll_tdm_clk", &pll_tdm_clk),
234 CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk),
235 CLK(NULL, "sys_dsp_clk", &sys_dsp_clk),
236 CLK(NULL, "sys_ddr_clk", &sys_ddr_clk),
237 CLK(NULL, "sys_full_clk", &sys_full_clk),
238 CLK(NULL, "sys_lcd_clk", &sys_lcd_clk),
239 CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk),
240 CLK(NULL, "sys_tsc_clk", &sys_tsc_clk),
241 CLK(NULL, "sys_half_clk", &sys_half_clk),
242 CLK(NULL, "eth_5mhz_clk", &eth_5mhz_clk),
243 CLK(NULL, "eth_50mhz_clk", &eth_50mhz_clk),
244 CLK(NULL, "eth_125mhz_clk", &eth_125mhz_clk),
245 CLK(NULL, "eth_250mhz_clk", &eth_250mhz_clk),
246 CLK(NULL, "eth_25mhz_clk", &eth_25mhz_clk),
247 CLK(NULL, "tdm_0_clk", &tdm_0_clk),
248 CLK(NULL, "tdm_extra_clk", &tdm_extra_clk),
249 CLK(NULL, "tdm_1_clk", &tdm_1_clk),
250 CLK(NULL, "clk_arm", &clk_arm),
251 CLK(NULL, "clk_gem", &clk_gem),
252 CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy),
253 CLK(NULL, "clk_tpcc", &clk_tpcc),
254 CLK(NULL, "clk_tptc0", &clk_tptc0),
255 CLK(NULL, "clk_tptc1", &clk_tptc1),
256 CLK(NULL, "clk_ram", &clk_ram),
257 CLK(NULL, "clk_mbx_lite", &clk_mbx_lite),
258 CLK("tnetv107x-fb.0", NULL, &clk_lcd),
259 CLK(NULL, "clk_ethss", &clk_ethss),
260 CLK(NULL, "aemif", &clk_aemif),
261 CLK(NULL, "clk_chipcfg", &clk_chipcfg),
262 CLK("tnetv107x-ts.0", NULL, &clk_tsc),
263 CLK(NULL, "clk_rom", &clk_rom),
264 CLK(NULL, "uart2", &clk_uart2),
265 CLK(NULL, "clk_pktsec", &clk_pktsec),
266 CLK("tnetv107x-rng.0", NULL, &clk_rng),
267 CLK("tnetv107x-pka.0", NULL, &clk_pka),
268 CLK(NULL, "clk_secctl", &clk_secctl),
269 CLK(NULL, "clk_keymgr", &clk_keymgr),
270 CLK("tnetv107x-keypad.0", NULL, &clk_keypad),
271 CLK(NULL, "clk_gpio", &clk_gpio),
272 CLK(NULL, "clk_mdio", &clk_mdio),
273 CLK("davinci_mmc.0", NULL, &clk_sdio0),
274 CLK(NULL, "uart0", &clk_uart0),
275 CLK(NULL, "uart1", &clk_uart1),
276 CLK(NULL, "timer0", &clk_timer0),
277 CLK(NULL, "timer1", &clk_timer1),
278 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
279 CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
280 CLK("ti-ssp.0", NULL, &clk_ssp),
281 CLK(NULL, "clk_tdm0", &clk_tdm0),
282 CLK(NULL, "clk_vlynq", &clk_vlynq),
283 CLK(NULL, "clk_mcdma", &clk_mcdma),
284 CLK(NULL, "clk_usb0", &clk_usb0),
285 CLK(NULL, "clk_tdm1", &clk_tdm1),
286 CLK(NULL, "clk_debugss", &clk_debugss),
287 CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii),
288 CLK(NULL, "clk_system", &clk_system),
289 CLK(NULL, "clk_imcop", &clk_imcop),
290 CLK(NULL, "clk_spare", &clk_spare),
291 CLK("davinci_mmc.1", NULL, &clk_sdio1),
292 CLK(NULL, "clk_usb1", &clk_usb1),
293 CLK(NULL, "clk_usbss", &clk_usbss),
294 CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
295 CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
296 CLK(NULL, NULL, NULL),
297};
298
299static const struct mux_config pins[] = {
300#ifdef CONFIG_DAVINCI_MUX
301 MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false)
302 MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false)
303 MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false)
304 MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false)
305 MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false)
306 MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false)
307 MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false)
308 MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false)
309 MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false)
310 MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false)
311 MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false)
312 MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false)
313 MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false)
314 MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false)
315 MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false)
316 MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false)
317 MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false)
318 MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false)
319 MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false)
320 MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false)
321 MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false)
322 MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false)
323 MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false)
324 MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false)
325 MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false)
326 MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false)
327 MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false)
328 MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false)
329 MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false)
330 MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false)
331 MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false)
332 MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false)
333 MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false)
334 MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false)
335 MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false)
336 MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false)
337 MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false)
338 MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false)
339 MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false)
340 MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false)
341 MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false)
342 MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false)
343 MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false)
344 MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false)
345 MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false)
346 MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false)
347 MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false)
348 MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false)
349 MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false)
350 MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false)
351 MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false)
352 MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false)
353 MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false)
354 MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false)
355 MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false)
356 MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false)
357 MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false)
358 MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false)
359 MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false)
360 MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false)
361 MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false)
362 MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false)
363 MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false)
364 MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false)
365 MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false)
366 MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false)
367 MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false)
368 MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false)
369 MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false)
370 MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false)
371 MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false)
372 MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false)
373 MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false)
374 MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false)
375 MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false)
376 MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false)
377 MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false)
378 MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false)
379 MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false)
380 MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false)
381 MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false)
382 MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false)
383 MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false)
384 MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false)
385 MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false)
386 MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false)
387 MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false)
388 MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false)
389 MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false)
390 MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false)
391 MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false)
392 MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false)
393 MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false)
394 MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false)
395 MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false)
396 MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false)
397 MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false)
398 MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false)
399 MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false)
400 MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false)
401 MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false)
402 MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false)
403 MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false)
404 MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false)
405 MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false)
406 MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false)
407 MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false)
408 MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false)
409 MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false)
410 MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false)
411 MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false)
412 MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false)
413 MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false)
414 MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false)
415 MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false)
416 MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false)
417 MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false)
418 MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false)
419 MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false)
420 MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false)
421 MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false)
422 MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false)
423 MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false)
424 MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false)
425 MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false)
426 MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false)
427 MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false)
428 MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false)
429 MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false)
430 MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false)
431 MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false)
432 MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false)
433 MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false)
434 MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false)
435 MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false)
436 MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false)
437 MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false)
438 MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false)
439 MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false)
440 MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false)
441 MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false)
442 MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false)
443 MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false)
444 MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false)
445 MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false)
446 MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false)
447 MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false)
448 MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false)
449 MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false)
450 MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false)
451 MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false)
452 MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false)
453 MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false)
454 MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false)
455 MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false)
456 MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false)
457 MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false)
458 MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false)
459 MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false)
460 MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false)
461 MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false)
462 MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false)
463 MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false)
464 MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false)
465 MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false)
466 MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false)
467 MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false)
468 MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false)
469 MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false)
470 MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false)
471 MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false)
472 MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false)
473 MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false)
474 MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false)
475 MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false)
476 MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false)
477 MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false)
478 MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false)
479 MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false)
480 MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false)
481 MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false)
482 MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false)
483 MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false)
484 MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false)
485 MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false)
486 MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false)
487 MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false)
488 MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false)
489 MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false)
490 MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false)
491 MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false)
492 MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false)
493 MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false)
494 MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false)
495 MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false)
496 MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false)
497 MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false)
498 MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false)
499 MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false)
500 MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false)
501 MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false)
502 MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false)
503 MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false)
504 MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false)
505 MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false)
506 MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false)
507 MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false)
508 MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false)
509 MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false)
510 MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false)
511 MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false)
512 MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false)
513 MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false)
514 MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false)
515 MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false)
516 MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false)
517 MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false)
518 MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false)
519 MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false)
520 MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false)
521 MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false)
522 MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false)
523 MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false)
524 MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false)
525 MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false)
526 MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false)
527 MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false)
528 MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false)
529 MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false)
530 MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false)
531 MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false)
532 MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false)
533 MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false)
534 MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false)
535 MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false)
536 MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false)
537 MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false)
538 MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false)
539 MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false)
540 MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false)
541 MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false)
542 MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false)
543 MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false)
544 MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false)
545 MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false)
546 MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false)
547 MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false)
548 MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false)
549 MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false)
550 MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false)
551 MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false)
552 MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false)
553 MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false)
554 MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false)
555 MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false)
556 MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false)
557 MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false)
558 MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false)
559 MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false)
560 MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false)
561 MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false)
562 MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false)
563 MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false)
564 MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false)
565 MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false)
566 MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false)
567#endif
568};
569
570/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
571static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
572 /* fill in default priority 7 */
573 [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7,
574 /* now override as needed, e.g. [xxx] = 5 */
575};
576
577/* Contents of JTAG ID register used to identify exact cpu type */
578static struct davinci_id ids[] = {
579 {
580 .variant = 0x0,
581 .part_no = 0xb8a1,
582 .manufacturer = 0x017,
583 .cpu_id = DAVINCI_CPU_ID_TNETV107X,
584 .name = "tnetv107x rev1.0",
585 },
586};
587
588static struct davinci_timer_instance timer_instance[2] = {
589 {
590 .base = TNETV107X_TIMER0_BASE,
591 .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12,
592 .top_irq = IRQ_TNETV107X_TIMER_0_TINT34,
593 },
594 {
595 .base = TNETV107X_TIMER1_BASE,
596 .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12,
597 .top_irq = IRQ_TNETV107X_TIMER_1_TINT34,
598 },
599};
600
601static struct davinci_timer_info timer_info = {
602 .timers = timer_instance,
603 .clockevent_id = T0_BOT,
604 .clocksource_id = T0_TOP,
605};
606
607/*
608 * TNETV107X platforms do not use the static mappings from Davinci
609 * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
610 * and changing IO_PHYS would break away from existing Davinci SOCs.
611 *
612 * The primary impact of the current model is that IO_ADDRESS() is not to be
613 * used to map registers on TNETV107X.
614 *
615 * 1. The first chunk is for INTC: This needs to be mapped in via iotable
616 * because ioremap() does not seem to be operational at the time when
617 * irqs are initialized. Without this, consistent dma init bombs.
618 *
619 * 2. The second chunk maps in register areas that need to be populated into
620 * davinci_soc_info. Note that alignment restrictions come into play if
621 * low-level debug is enabled (see note in <mach/tnetv107x.h>).
622 */
623static struct map_desc io_desc[] = {
624 { /* INTC */
625 .virtual = IO_VIRT,
626 .pfn = __phys_to_pfn(TNETV107X_INTC_BASE),
627 .length = SZ_16K,
628 .type = MT_DEVICE
629 },
630 { /* Most of the rest */
631 .virtual = TNETV107X_IO_VIRT,
632 .pfn = __phys_to_pfn(TNETV107X_IO_BASE),
633 .length = IO_SIZE - SZ_1M,
634 .type = MT_DEVICE
635 },
636};
637
638static unsigned long clk_sspll_recalc(struct clk *clk)
639{
640 int pll;
641 unsigned long mult = 0, prediv = 1, postdiv = 1;
642 unsigned long ref = OSC_FREQ_ONCHIP, ret;
643 u32 tmp;
644
645 if (WARN_ON(!clk->pll_data))
646 return clk->rate;
647
648 if (!clk_ctrl_regs) {
649 void __iomem *tmp;
650
651 tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
652
653 if (WARN(!tmp, "failed ioremap for clock control regs\n"))
654 return clk->parent ? clk->parent->rate : 0;
655
656 for (pll = 0; pll < N_PLLS; pll++)
657 sspll_regs[pll] = tmp + sspll_regs_base[pll];
658
659 clk_ctrl_regs = tmp;
660 }
661
662 pll = clk->pll_data->num;
663
664 tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
665 if (!(tmp & bypass_mask[pll])) {
666 mult = __raw_readl(&sspll_regs[pll]->mult_factor);
667 prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1;
668 postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1;
669 }
670
671 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
672 if (tmp & PLLCTL_CLKMODE)
673 ref = pll_ext_freq[pll];
674
675 clk->pll_data->input_rate = ref;
676
677 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
678 if (!(tmp & PLLCTL_PLLEN))
679 return ref;
680
681 ret = ref;
682 if (mult)
683 ret += ((unsigned long long)ref * mult) / 256;
684
685 ret /= (prediv * postdiv);
686
687 return ret;
688}
689
690static void tnetv107x_watchdog_reset(struct platform_device *pdev)
691{
692 struct wdt_regs __iomem *regs;
693
694 regs = ioremap(pdev->resource[0].start, SZ_4K);
695
696 /* disable watchdog */
697 __raw_writel(0x7777, &regs->disable_lock);
698 __raw_writel(0xcccc, &regs->disable_lock);
699 __raw_writel(0xdddd, &regs->disable_lock);
700 __raw_writel(0, &regs->disable);
701
702 /* program prescale */
703 __raw_writel(0x5a5a, &regs->prescale_lock);
704 __raw_writel(0xa5a5, &regs->prescale_lock);
705 __raw_writel(0, &regs->prescale);
706
707 /* program countdown */
708 __raw_writel(0x6666, &regs->change_lock);
709 __raw_writel(0xbbbb, &regs->change_lock);
710 __raw_writel(1, &regs->change);
711
712 /* enable watchdog */
713 __raw_writel(0x7777, &regs->disable_lock);
714 __raw_writel(0xcccc, &regs->disable_lock);
715 __raw_writel(0xdddd, &regs->disable_lock);
716 __raw_writel(1, &regs->disable);
717
718 /* kick */
719 __raw_writel(0x5555, &regs->kick_lock);
720 __raw_writel(0xaaaa, &regs->kick_lock);
721 __raw_writel(1, &regs->kick);
722}
723
724static struct davinci_soc_info tnetv107x_soc_info = {
725 .io_desc = io_desc,
726 .io_desc_num = ARRAY_SIZE(io_desc),
727 .ids = ids,
728 .ids_num = ARRAY_SIZE(ids),
729 .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018,
730 .cpu_clks = clks,
731 .psc_bases = psc_regs,
732 .psc_bases_num = ARRAY_SIZE(psc_regs),
733 .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150,
734 .pinmux_pins = pins,
735 .pinmux_pins_num = ARRAY_SIZE(pins),
736 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
737 .intc_base = TNETV107X_INTC_BASE,
738 .intc_irq_prios = irq_prios,
739 .intc_irq_num = TNETV107X_N_CP_INTC_IRQ,
740 .intc_host_map = intc_host_map,
741 .gpio_base = TNETV107X_GPIO_BASE,
742 .gpio_type = GPIO_TYPE_TNETV107X,
743 .gpio_num = TNETV107X_N_GPIO,
744 .timer_info = &timer_info,
745 .serial_dev = &tnetv107x_serial_device,
746 .reset = tnetv107x_watchdog_reset,
747 .reset_device = &tnetv107x_wdt_device,
748};
749
750void __init tnetv107x_init(void)
751{
752 davinci_common_init(&tnetv107x_soc_info);
753}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 15:47:10 -0500