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-rw-r--r--arch/arm/mach-davinci/Kconfig47
-rw-r--r--arch/arm/mach-davinci/Makefile9
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c (renamed from arch/arm/mach-davinci/board-evm.c)322
-rw-r--r--arch/arm/mach-davinci/clock.c385
-rw-r--r--arch/arm/mach-davinci/clock.h87
-rw-r--r--arch/arm/mach-davinci/devices.c7
-rw-r--r--arch/arm/mach-davinci/dm644x.c461
-rw-r--r--arch/arm/mach-davinci/dma.c1135
-rw-r--r--arch/arm/mach-davinci/gpio.c82
-rw-r--r--arch/arm/mach-davinci/id.c35
-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/clkdev.h13
-rw-r--r--arch/arm/mach-davinci/include/mach/clock.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h49
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h37
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h228
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h51
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h103
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h220
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h53
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h21
-rw-r--r--arch/arm/mach-davinci/io.c23
-rw-r--r--arch/arm/mach-davinci/irq.c156
-rw-r--r--arch/arm/mach-davinci/mux.c100
-rw-r--r--arch/arm/mach-davinci/mux.h51
-rw-r--r--arch/arm/mach-davinci/psc.c98
-rw-r--r--arch/arm/mach-davinci/serial.c95
-rw-r--r--arch/arm/mach-davinci/time.c103
-rw-r--r--arch/arm/mach-davinci/usb.c2
32 files changed, 3537 insertions, 510 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index bac988e7a4c3..a9c78bc72b84 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,19 +4,56 @@ menu "TI DaVinci Implementations"
4 4
5comment "DaVinci Core Type" 5comment "DaVinci Core Type"
6 6
7config ARCH_DAVINCI644x 7config ARCH_DAVINCI_DM644x
8 default y
9 bool "DaVinci 644x based system" 8 bool "DaVinci 644x based system"
10 9
11comment "DaVinci Board Type" 10comment "DaVinci Board Type"
12 11
13config MACH_DAVINCI_EVM 12config MACH_DAVINCI_EVM
14 bool "TI DaVinci EVM" 13 bool "TI DM644x EVM"
15 default y 14 default y
16 depends on ARCH_DAVINCI644x 15 depends on ARCH_DAVINCI_DM644x
17 help 16 help
18 Configure this option to specify the whether the board used 17 Configure this option to specify the whether the board used
19 for development is a DaVinci EVM 18 for development is a DM644x EVM
19
20
21config DAVINCI_MUX
22 bool "DAVINCI multiplexing support"
23 depends on ARCH_DAVINCI
24 default y
25 help
26 Pin multiplexing support for DAVINCI boards. If your bootloader
27 sets the multiplexing correctly, say N. Otherwise, or if unsure,
28 say Y.
29
30config DAVINCI_MUX_DEBUG
31 bool "Multiplexing debug output"
32 depends on DAVINCI_MUX
33 help
34 Makes the multiplexing functions print out a lot of debug info.
35 This is useful if you want to find out the correct values of the
36 multiplexing registers.
37
38config DAVINCI_MUX_WARNINGS
39 bool "Warn about pins the bootloader didn't set up"
40 depends on DAVINCI_MUX
41 help
42 Choose Y here to warn whenever driver initialization logic needs
43 to change the pin multiplexing setup. When there are no warnings
44 printed, it's safe to deselect DAVINCI_MUX for your product.
45
46config DAVINCI_RESET_CLOCKS
47 bool "Reset unused clocks during boot"
48 depends on ARCH_DAVINCI
49 help
50 Say Y if you want to reset unused clocks during boot.
51 This option saves power, but assumes all drivers are
52 using the clock framework. Broken drivers that do not
53 yet use clock framework may not work with this option.
54 If you are booting from another operating system, you
55 probably do not want this option enabled until your
56 device drivers work properly.
20 57
21endmenu 58endmenu
22 59
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 4dc458597f40..1674661942f3 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,12 @@
5 5
6# Common objects 6# Common objects
7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ 7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
8 gpio.o mux.o devices.o usb.o 8 gpio.o devices.o dma.o usb.o
9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o
11
12# Chip specific
13obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
9 14
10# Board specific 15# Board specific
11obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o 16obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0b97a528902b..c039674fe99e 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -15,15 +15,20 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/leds.h> 17#include <linux/leds.h>
18#include <linux/memory.h>
19#include <linux/etherdevice.h>
18 20
19#include <linux/i2c.h> 21#include <linux/i2c.h>
20#include <linux/i2c/pcf857x.h> 22#include <linux/i2c/pcf857x.h>
21#include <linux/i2c/at24.h> 23#include <linux/i2c/at24.h>
22 24
23#include <linux/mtd/mtd.h> 25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h> 27#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
26#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/phy.h>
31#include <linux/clk.h>
27 32
28#include <asm/setup.h> 33#include <asm/setup.h>
29#include <asm/mach-types.h> 34#include <asm/mach-types.h>
@@ -32,25 +37,34 @@
32#include <asm/mach/map.h> 37#include <asm/mach/map.h>
33#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
34 39
35#include <mach/hardware.h> 40#include <mach/dm644x.h>
36#include <mach/common.h> 41#include <mach/common.h>
37#include <mach/i2c.h> 42#include <mach/i2c.h>
43#include <mach/serial.h>
44#include <mach/mux.h>
45#include <mach/psc.h>
46#include <mach/nand.h>
38 47
39/* other misc. init functions */ 48#define DM644X_EVM_PHY_MASK (0x2)
40void __init davinci_psc_init(void); 49#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
41void __init davinci_irq_init(void);
42void __init davinci_map_common_io(void);
43void __init davinci_init_common_hw(void);
44 50
45#if defined(CONFIG_MTD_PHYSMAP) || \ 51#define DAVINCI_CFC_ATA_BASE 0x01C66000
46 defined(CONFIG_MTD_PHYSMAP_MODULE) 52
53#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
54#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
55#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
56#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
57#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
58
59#define LXT971_PHY_ID (0x001378e2)
60#define LXT971_PHY_MASK (0xfffffff0)
47 61
48static struct mtd_partition davinci_evm_norflash_partitions[] = { 62static struct mtd_partition davinci_evm_norflash_partitions[] = {
49 /* bootloader (U-Boot, etc) in first 4 sectors */ 63 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
50 { 64 {
51 .name = "bootloader", 65 .name = "bootloader",
52 .offset = 0, 66 .offset = 0,
53 .size = 4 * SZ_64K, 67 .size = 5 * SZ_64K,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */ 68 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 }, 69 },
56 /* bootloader params in the next 1 sectors */ 70 /* bootloader params in the next 1 sectors */
@@ -100,10 +114,89 @@ static struct platform_device davinci_evm_norflash_device = {
100 .resource = &davinci_evm_norflash_resource, 114 .resource = &davinci_evm_norflash_resource,
101}; 115};
102 116
103#endif 117/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
118 * It may used instead of the (default) NOR chip to boot, using TI's
119 * tools to install the secondary boot loader (UBL) and U-Boot.
120 */
121struct mtd_partition davinci_evm_nandflash_partition[] = {
122 /* Bootloader layout depends on whose u-boot is installed, but we
123 * can hide all the details.
124 * - block 0 for u-boot environment ... in mainline u-boot
125 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
126 * - blocks 6...? for u-boot
127 * - blocks 16..23 for u-boot environment ... in TI's u-boot
128 */
129 {
130 .name = "bootloader",
131 .offset = 0,
132 .size = SZ_256K + SZ_128K,
133 .mask_flags = MTD_WRITEABLE, /* force read-only */
134 },
135 /* Kernel */
136 {
137 .name = "kernel",
138 .offset = MTDPART_OFS_APPEND,
139 .size = SZ_4M,
140 .mask_flags = 0,
141 },
142 /* File system (older GIT kernels started this on the 5MB mark) */
143 {
144 .name = "filesystem",
145 .offset = MTDPART_OFS_APPEND,
146 .size = MTDPART_SIZ_FULL,
147 .mask_flags = 0,
148 }
149 /* A few blocks at end hold a flash BBT ... created by TI's CCS
150 * using flashwriter_nand.out, but ignored by TI's versions of
151 * Linux and u-boot. We boot faster by using them.
152 */
153};
104 154
105#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 155static struct davinci_nand_pdata davinci_evm_nandflash_data = {
106 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 156 .parts = davinci_evm_nandflash_partition,
157 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
158 .ecc_mode = NAND_ECC_HW,
159 .options = NAND_USE_FLASH_BBT,
160};
161
162static struct resource davinci_evm_nandflash_resource[] = {
163 {
164 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
165 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
169 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
170 .flags = IORESOURCE_MEM,
171 },
172};
173
174static struct platform_device davinci_evm_nandflash_device = {
175 .name = "davinci_nand",
176 .id = 0,
177 .dev = {
178 .platform_data = &davinci_evm_nandflash_data,
179 },
180 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
181 .resource = davinci_evm_nandflash_resource,
182};
183
184static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
185
186static struct platform_device davinci_fb_device = {
187 .name = "davincifb",
188 .id = -1,
189 .dev = {
190 .dma_mask = &davinci_fb_dma_mask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
192 },
193 .num_resources = 0,
194};
195
196static struct platform_device rtc_dev = {
197 .name = "rtc_davinci_evm",
198 .id = -1,
199};
107 200
108static struct resource ide_resources[] = { 201static struct resource ide_resources[] = {
109 { 202 {
@@ -118,7 +211,7 @@ static struct resource ide_resources[] = {
118 }, 211 },
119}; 212};
120 213
121static u64 ide_dma_mask = DMA_BIT_MASK(32); 214static u64 ide_dma_mask = DMA_32BIT_MASK;
122 215
123static struct platform_device ide_dev = { 216static struct platform_device ide_dev = {
124 .name = "palm_bk3710", 217 .name = "palm_bk3710",
@@ -127,12 +220,10 @@ static struct platform_device ide_dev = {
127 .num_resources = ARRAY_SIZE(ide_resources), 220 .num_resources = ARRAY_SIZE(ide_resources),
128 .dev = { 221 .dev = {
129 .dma_mask = &ide_dma_mask, 222 .dma_mask = &ide_dma_mask,
130 .coherent_dma_mask = DMA_BIT_MASK(32), 223 .coherent_dma_mask = DMA_32BIT_MASK,
131 }, 224 },
132}; 225};
133 226
134#endif
135
136/*----------------------------------------------------------------------*/ 227/*----------------------------------------------------------------------*/
137 228
138/* 229/*
@@ -311,7 +402,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
311 gpio_request(gpio + 7, "nCF_SEL"); 402 gpio_request(gpio + 7, "nCF_SEL");
312 gpio_direction_output(gpio + 7, 1); 403 gpio_direction_output(gpio + 7, 1);
313 404
314 /* irlml6401 sustains over 3A, switches 5V in under 8 msec */ 405 /* irlml6401 switches over 1A, in under 8 msec;
406 * now it can be managed by nDRV_VBUS ...
407 */
315 setup_usb(500, 8); 408 setup_usb(500, 8);
316 409
317 return 0; 410 return 0;
@@ -343,14 +436,120 @@ static struct pcf857x_platform_data pcf_data_u35 = {
343 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) 436 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
344 * - ... newer boards may have more 437 * - ... newer boards may have more
345 */ 438 */
439static struct memory_accessor *at24_mem_acc;
440
441static void at24_setup(struct memory_accessor *mem_acc, void *context)
442{
443 DECLARE_MAC_BUF(mac_str);
444 char mac_addr[6];
445
446 at24_mem_acc = mem_acc;
447
448 /* Read MAC addr from EEPROM */
449 if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
450 printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
451 print_mac(mac_str, mac_addr));
452 }
453}
454
346static struct at24_platform_data eeprom_info = { 455static struct at24_platform_data eeprom_info = {
347 .byte_len = (256*1024) / 8, 456 .byte_len = (256*1024) / 8,
348 .page_size = 64, 457 .page_size = 64,
349 .flags = AT24_FLAG_ADDR16, 458 .flags = AT24_FLAG_ADDR16,
459 .setup = at24_setup,
350}; 460};
351 461
462int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
463{
464 if (at24_mem_acc)
465 return at24_mem_acc->read(at24_mem_acc, buf, off, count);
466 return -ENODEV;
467}
468EXPORT_SYMBOL(dm6446evm_eeprom_read);
469
470int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
471{
472 if (at24_mem_acc)
473 return at24_mem_acc->write(at24_mem_acc, buf, off, count);
474 return -ENODEV;
475}
476EXPORT_SYMBOL(dm6446evm_eeprom_write);
477
478/*
479 * MSP430 supports RTC, card detection, input from IR remote, and
480 * a bit more. It triggers interrupts on GPIO(7) from pressing
481 * buttons on the IR remote, and for card detect switches.
482 */
483static struct i2c_client *dm6446evm_msp;
484
485static int dm6446evm_msp_probe(struct i2c_client *client,
486 const struct i2c_device_id *id)
487{
488 dm6446evm_msp = client;
489 return 0;
490}
491
492static int dm6446evm_msp_remove(struct i2c_client *client)
493{
494 dm6446evm_msp = NULL;
495 return 0;
496}
497
498static const struct i2c_device_id dm6446evm_msp_ids[] = {
499 { "dm6446evm_msp", 0, },
500 { /* end of list */ },
501};
502
503static struct i2c_driver dm6446evm_msp_driver = {
504 .driver.name = "dm6446evm_msp",
505 .id_table = dm6446evm_msp_ids,
506 .probe = dm6446evm_msp_probe,
507 .remove = dm6446evm_msp_remove,
508};
509
510static int dm6444evm_msp430_get_pins(void)
511{
512 static const char txbuf[2] = { 2, 4, };
513 char buf[4];
514 struct i2c_msg msg[2] = {
515 {
516 .addr = dm6446evm_msp->addr,
517 .flags = 0,
518 .len = 2,
519 .buf = (void __force *)txbuf,
520 },
521 {
522 .addr = dm6446evm_msp->addr,
523 .flags = I2C_M_RD,
524 .len = 4,
525 .buf = buf,
526 },
527 };
528 int status;
529
530 if (!dm6446evm_msp)
531 return -ENXIO;
532
533 /* Command 4 == get input state, returns port 2 and port3 data
534 * S Addr W [A] len=2 [A] cmd=4 [A]
535 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
536 */
537 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
538 if (status < 0)
539 return status;
540
541 dev_dbg(&dm6446evm_msp->dev,
542 "PINS: %02x %02x %02x %02x\n",
543 buf[0], buf[1], buf[2], buf[3]);
544
545 return (buf[3] << 8) | buf[2];
546}
547
352static struct i2c_board_info __initdata i2c_info[] = { 548static struct i2c_board_info __initdata i2c_info[] = {
353 { 549 {
550 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
551 },
552 {
354 I2C_BOARD_INFO("pcf8574", 0x38), 553 I2C_BOARD_INFO("pcf8574", 0x38),
355 .platform_data = &pcf_data_u2, 554 .platform_data = &pcf_data_u2,
356 }, 555 },
@@ -368,7 +567,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
368 }, 567 },
369 /* ALSO: 568 /* ALSO:
370 * - tvl320aic33 audio codec (0x1b) 569 * - tvl320aic33 audio codec (0x1b)
371 * - msp430 microcontroller (0x23)
372 * - tvp5146 video decoder (0x5d) 570 * - tvp5146 video decoder (0x5d)
373 */ 571 */
374}; 572};
@@ -384,51 +582,109 @@ static struct davinci_i2c_platform_data i2c_pdata = {
384static void __init evm_init_i2c(void) 582static void __init evm_init_i2c(void)
385{ 583{
386 davinci_init_i2c(&i2c_pdata); 584 davinci_init_i2c(&i2c_pdata);
585 i2c_add_driver(&dm6446evm_msp_driver);
387 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 586 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
388} 587}
389 588
390static struct platform_device *davinci_evm_devices[] __initdata = { 589static struct platform_device *davinci_evm_devices[] __initdata = {
391#if defined(CONFIG_MTD_PHYSMAP) || \ 590 &davinci_fb_device,
392 defined(CONFIG_MTD_PHYSMAP_MODULE) 591 &rtc_dev,
393 &davinci_evm_norflash_device, 592};
394#endif 593
395#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 594static struct davinci_uart_config uart_config __initdata = {
396 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 595 .enabled_uarts = (1 << 0),
397 &ide_dev,
398#endif
399}; 596};
400 597
401static void __init 598static void __init
402davinci_evm_map_io(void) 599davinci_evm_map_io(void)
403{ 600{
404 davinci_map_common_io(); 601 davinci_map_common_io();
602 dm644x_init();
405} 603}
406 604
407static __init void davinci_evm_init(void) 605static int davinci_phy_fixup(struct phy_device *phydev)
408{ 606{
409 davinci_psc_init(); 607 unsigned int control;
608 /* CRITICAL: Fix for increasing PHY signal drive strength for
609 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
610 * signal strength was low causing TX to fail randomly. The
611 * fix is to Set bit 11 (Increased MII drive strength) of PHY
612 * register 26 (Digital Config register) on this phy. */
613 control = phy_read(phydev, 26);
614 phy_write(phydev, 26, (control | 0x800));
615 return 0;
616}
410 617
411#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 618#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
412 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 619 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
620#define HAS_ATA 1
621#else
622#define HAS_ATA 0
623#endif
624
413#if defined(CONFIG_MTD_PHYSMAP) || \ 625#if defined(CONFIG_MTD_PHYSMAP) || \
414 defined(CONFIG_MTD_PHYSMAP_MODULE) 626 defined(CONFIG_MTD_PHYSMAP_MODULE)
415 printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " 627#define HAS_NOR 1
416 "but share pins.\n\t Disable IDE for NOR support.\n"); 628#else
629#define HAS_NOR 0
417#endif 630#endif
631
632#if defined(CONFIG_MTD_NAND_DAVINCI) || \
633 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
634#define HAS_NAND 1
635#else
636#define HAS_NAND 0
418#endif 637#endif
419 638
639static __init void davinci_evm_init(void)
640{
641 struct clk *aemif_clk;
642
643 aemif_clk = clk_get(NULL, "aemif");
644 clk_enable(aemif_clk);
645
646 if (HAS_ATA) {
647 if (HAS_NAND || HAS_NOR)
648 pr_warning("WARNING: both IDE and Flash are "
649 "enabled, but they share AEMIF pins.\n"
650 "\tDisable IDE for NAND/NOR support.\n");
651 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
652 davinci_cfg_reg(DM644X_ATAEN);
653 davinci_cfg_reg(DM644X_HDIREN);
654 platform_device_register(&ide_dev);
655 } else if (HAS_NAND || HAS_NOR) {
656 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
657 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
658
659 /* only one device will be jumpered and detected */
660 if (HAS_NAND) {
661 platform_device_register(&davinci_evm_nandflash_device);
662 evm_leds[7].default_trigger = "nand-disk";
663 if (HAS_NOR)
664 pr_warning("WARNING: both NAND and NOR flash "
665 "are enabled; disable one of them.\n");
666 } else if (HAS_NOR)
667 platform_device_register(&davinci_evm_norflash_device);
668 }
669
420 platform_add_devices(davinci_evm_devices, 670 platform_add_devices(davinci_evm_devices,
421 ARRAY_SIZE(davinci_evm_devices)); 671 ARRAY_SIZE(davinci_evm_devices));
422 evm_init_i2c(); 672 evm_init_i2c();
673
674 davinci_serial_init(&uart_config);
675
676 /* Register the fixup for PHY on DaVinci */
677 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
678 davinci_phy_fixup);
679
423} 680}
424 681
425static __init void davinci_evm_irq_init(void) 682static __init void davinci_evm_irq_init(void)
426{ 683{
427 davinci_init_common_hw();
428 davinci_irq_init(); 684 davinci_irq_init();
429} 685}
430 686
431MACHINE_START(DAVINCI_EVM, "DaVinci EVM") 687MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
432 /* Maintainer: MontaVista Software <source@mvista.com> */ 688 /* Maintainer: MontaVista Software <source@mvista.com> */
433 .phys_io = IO_PHYS, 689 .phys_io = IO_PHYS,
434 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 690 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index abb92b7eca0c..f0baaa15a57e 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * TI DaVinci clock config file 2 * Clock and PLL control for DaVinci devices
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/clk.h>
16#include <linux/err.h> 18#include <linux/err.h>
17#include <linux/mutex.h> 19#include <linux/mutex.h>
18#include <linux/platform_device.h> 20#include <linux/platform_device.h>
@@ -21,98 +23,50 @@
21#include <mach/hardware.h> 23#include <mach/hardware.h>
22 24
23#include <mach/psc.h> 25#include <mach/psc.h>
26#include <mach/cputype.h>
24#include "clock.h" 27#include "clock.h"
25 28
26/* PLL/Reset register offsets */
27#define PLLM 0x110
28
29static LIST_HEAD(clocks); 29static LIST_HEAD(clocks);
30static DEFINE_MUTEX(clocks_mutex); 30static DEFINE_MUTEX(clocks_mutex);
31static DEFINE_SPINLOCK(clockfw_lock); 31static DEFINE_SPINLOCK(clockfw_lock);
32 32
33static unsigned int commonrate; 33static unsigned psc_domain(struct clk *clk)
34static unsigned int armrate;
35static unsigned int fixedrate = 27000000; /* 27 MHZ */
36
37extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable);
38
39/*
40 * Returns a clock. Note that we first try to use device id on the bus
41 * and clock name. If this fails, we try to use clock name only.
42 */
43struct clk *clk_get(struct device *dev, const char *id)
44{ 34{
45 struct clk *p, *clk = ERR_PTR(-ENOENT); 35 return (clk->flags & PSC_DSP)
46 int idno; 36 ? DAVINCI_GPSC_DSPDOMAIN
47 37 : DAVINCI_GPSC_ARMDOMAIN;
48 if (dev == NULL || dev->bus != &platform_bus_type)
49 idno = -1;
50 else
51 idno = to_platform_device(dev)->id;
52
53 mutex_lock(&clocks_mutex);
54
55 list_for_each_entry(p, &clocks, node) {
56 if (p->id == idno &&
57 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
58 clk = p;
59 goto found;
60 }
61 }
62
63 list_for_each_entry(p, &clocks, node) {
64 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
65 clk = p;
66 break;
67 }
68 }
69
70found:
71 mutex_unlock(&clocks_mutex);
72
73 return clk;
74} 38}
75EXPORT_SYMBOL(clk_get);
76 39
77void clk_put(struct clk *clk) 40static void __clk_enable(struct clk *clk)
78{ 41{
79 if (clk && !IS_ERR(clk)) 42 if (clk->parent)
80 module_put(clk->owner); 43 __clk_enable(clk->parent);
81} 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
82EXPORT_SYMBOL(clk_put); 45 davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
83
84static int __clk_enable(struct clk *clk)
85{
86 if (clk->flags & ALWAYS_ENABLED)
87 return 0;
88
89 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
90 return 0;
91} 46}
92 47
93static void __clk_disable(struct clk *clk) 48static void __clk_disable(struct clk *clk)
94{ 49{
95 if (clk->usecount) 50 if (WARN_ON(clk->usecount == 0))
96 return; 51 return;
97 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
98 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); 53 davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
54 if (clk->parent)
55 __clk_disable(clk->parent);
99} 56}
100 57
101int clk_enable(struct clk *clk) 58int clk_enable(struct clk *clk)
102{ 59{
103 unsigned long flags; 60 unsigned long flags;
104 int ret = 0;
105 61
106 if (clk == NULL || IS_ERR(clk)) 62 if (clk == NULL || IS_ERR(clk))
107 return -EINVAL; 63 return -EINVAL;
108 64
109 if (clk->usecount++ == 0) { 65 spin_lock_irqsave(&clockfw_lock, flags);
110 spin_lock_irqsave(&clockfw_lock, flags); 66 __clk_enable(clk);
111 ret = __clk_enable(clk); 67 spin_unlock_irqrestore(&clockfw_lock, flags);
112 spin_unlock_irqrestore(&clockfw_lock, flags);
113 }
114 68
115 return ret; 69 return 0;
116} 70}
117EXPORT_SYMBOL(clk_enable); 71EXPORT_SYMBOL(clk_enable);
118 72
@@ -123,11 +77,9 @@ void clk_disable(struct clk *clk)
123 if (clk == NULL || IS_ERR(clk)) 77 if (clk == NULL || IS_ERR(clk))
124 return; 78 return;
125 79
126 if (clk->usecount > 0 && !(--clk->usecount)) { 80 spin_lock_irqsave(&clockfw_lock, flags);
127 spin_lock_irqsave(&clockfw_lock, flags); 81 __clk_disable(clk);
128 __clk_disable(clk); 82 spin_unlock_irqrestore(&clockfw_lock, flags);
129 spin_unlock_irqrestore(&clockfw_lock, flags);
130 }
131} 83}
132EXPORT_SYMBOL(clk_disable); 84EXPORT_SYMBOL(clk_disable);
133 85
@@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk)
136 if (clk == NULL || IS_ERR(clk)) 88 if (clk == NULL || IS_ERR(clk))
137 return -EINVAL; 89 return -EINVAL;
138 90
139 return *(clk->rate); 91 return clk->rate;
140} 92}
141EXPORT_SYMBOL(clk_get_rate); 93EXPORT_SYMBOL(clk_get_rate);
142 94
@@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
145 if (clk == NULL || IS_ERR(clk)) 97 if (clk == NULL || IS_ERR(clk))
146 return -EINVAL; 98 return -EINVAL;
147 99
148 return *(clk->rate); 100 return clk->rate;
149} 101}
150EXPORT_SYMBOL(clk_round_rate); 102EXPORT_SYMBOL(clk_round_rate);
151 103
@@ -164,10 +116,23 @@ int clk_register(struct clk *clk)
164 if (clk == NULL || IS_ERR(clk)) 116 if (clk == NULL || IS_ERR(clk))
165 return -EINVAL; 117 return -EINVAL;
166 118
119 if (WARN(clk->parent && !clk->parent->rate,
120 "CLK: %s parent %s has no rate!\n",
121 clk->name, clk->parent->name))
122 return -EINVAL;
123
167 mutex_lock(&clocks_mutex); 124 mutex_lock(&clocks_mutex);
168 list_add(&clk->node, &clocks); 125 list_add_tail(&clk->node, &clocks);
169 mutex_unlock(&clocks_mutex); 126 mutex_unlock(&clocks_mutex);
170 127
128 /* If rate is already set, use it */
129 if (clk->rate)
130 return 0;
131
132 /* Otherwise, default to parent rate */
133 if (clk->parent)
134 clk->rate = clk->parent->rate;
135
171 return 0; 136 return 0;
172} 137}
173EXPORT_SYMBOL(clk_register); 138EXPORT_SYMBOL(clk_register);
@@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk)
183} 148}
184EXPORT_SYMBOL(clk_unregister); 149EXPORT_SYMBOL(clk_unregister);
185 150
186static struct clk davinci_clks[] = { 151#ifdef CONFIG_DAVINCI_RESET_CLOCKS
187 { 152/*
188 .name = "ARMCLK", 153 * Disable any unused clocks left on by the bootloader
189 .rate = &armrate, 154 */
190 .lpsc = -1, 155static int __init clk_disable_unused(void)
191 .flags = ALWAYS_ENABLED, 156{
192 }, 157 struct clk *ck;
193 { 158
194 .name = "UART", 159 spin_lock_irq(&clockfw_lock);
195 .rate = &fixedrate, 160 list_for_each_entry(ck, &clocks, node) {
196 .lpsc = DAVINCI_LPSC_UART0, 161 if (ck->usecount > 0)
197 }, 162 continue;
198 { 163 if (!(ck->flags & CLK_PSC))
199 .name = "EMACCLK", 164 continue;
200 .rate = &commonrate, 165
201 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, 166 /* ignore if in Disabled or SwRstDisable states */
202 }, 167 if (!davinci_psc_is_clk_active(ck->lpsc))
203 { 168 continue;
204 .name = "I2CCLK", 169
205 .rate = &fixedrate, 170 pr_info("Clocks: disable unused %s\n", ck->name);
206 .lpsc = DAVINCI_LPSC_I2C, 171 davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
207 },
208 {
209 .name = "IDECLK",
210 .rate = &commonrate,
211 .lpsc = DAVINCI_LPSC_ATA,
212 },
213 {
214 .name = "McBSPCLK",
215 .rate = &commonrate,
216 .lpsc = DAVINCI_LPSC_McBSP,
217 },
218 {
219 .name = "MMCSDCLK",
220 .rate = &commonrate,
221 .lpsc = DAVINCI_LPSC_MMC_SD,
222 },
223 {
224 .name = "SPICLK",
225 .rate = &commonrate,
226 .lpsc = DAVINCI_LPSC_SPI,
227 },
228 {
229 .name = "gpio",
230 .rate = &commonrate,
231 .lpsc = DAVINCI_LPSC_GPIO,
232 },
233 {
234 .name = "usb",
235 .rate = &commonrate,
236 .lpsc = DAVINCI_LPSC_USB,
237 },
238 {
239 .name = "AEMIFCLK",
240 .rate = &commonrate,
241 .lpsc = DAVINCI_LPSC_AEMIF,
242 .usecount = 1,
243 } 172 }
244}; 173 spin_unlock_irq(&clockfw_lock);
174
175 return 0;
176}
177late_initcall(clk_disable_unused);
178#endif
245 179
246int __init davinci_clk_init(void) 180static void clk_sysclk_recalc(struct clk *clk)
247{ 181{
248 struct clk *clkp; 182 u32 v, plldiv;
249 int count = 0; 183 struct pll_data *pll;
250 u32 pll_mult; 184
251 185 /* If this is the PLL base clock, no more calculations needed */
252 pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); 186 if (clk->pll_data)
253 commonrate = ((pll_mult + 1) * 27000000) / 6; 187 return;
254 armrate = ((pll_mult + 1) * 27000000) / 2; 188
255 189 if (WARN_ON(!clk->parent))
256 for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); 190 return;
257 count++, clkp++) { 191
258 clk_register(clkp); 192 clk->rate = clk->parent->rate;
259 193
260 /* Turn on clocks that have been enabled in the 194 /* Otherwise, the parent must be a PLL */
261 * table above */ 195 if (WARN_ON(!clk->parent->pll_data))
262 if (clkp->usecount) 196 return;
263 clk_enable(clkp); 197
198 pll = clk->parent->pll_data;
199
200 /* If pre-PLL, source clock is before the multiplier and divider(s) */
201 if (clk->flags & PRE_PLL)
202 clk->rate = pll->input_rate;
203
204 if (!clk->div_reg)
205 return;
206
207 v = __raw_readl(pll->base + clk->div_reg);
208 if (v & PLLDIV_EN) {
209 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
210 if (plldiv)
211 clk->rate /= plldiv;
212 }
213}
214
215static void __init clk_pll_init(struct clk *clk)
216{
217 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
218 u8 bypass;
219 struct pll_data *pll = clk->pll_data;
220
221 pll->base = IO_ADDRESS(pll->phys_base);
222 ctrl = __raw_readl(pll->base + PLLCTL);
223 clk->rate = pll->input_rate = clk->parent->rate;
224
225 if (ctrl & PLLCTL_PLLEN) {
226 bypass = 0;
227 mult = __raw_readl(pll->base + PLLM);
228 mult = (mult & PLLM_PLLM_MASK) + 1;
229 } else
230 bypass = 1;
231
232 if (pll->flags & PLL_HAS_PREDIV) {
233 prediv = __raw_readl(pll->base + PREDIV);
234 if (prediv & PLLDIV_EN)
235 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
236 else
237 prediv = 1;
238 }
239
240 /* pre-divider is fixed, but (some?) chips won't report that */
241 if (cpu_is_davinci_dm355() && pll->num == 1)
242 prediv = 8;
243
244 if (pll->flags & PLL_HAS_POSTDIV) {
245 postdiv = __raw_readl(pll->base + POSTDIV);
246 if (postdiv & PLLDIV_EN)
247 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
248 else
249 postdiv = 1;
250 }
251
252 if (!bypass) {
253 clk->rate /= prediv;
254 clk->rate *= mult;
255 clk->rate /= postdiv;
256 }
257
258 pr_debug("PLL%d: input = %lu MHz [ ",
259 pll->num, clk->parent->rate / 1000000);
260 if (bypass)
261 pr_debug("bypass ");
262 if (prediv > 1)
263 pr_debug("/ %d ", prediv);
264 if (mult > 1)
265 pr_debug("* %d ", mult);
266 if (postdiv > 1)
267 pr_debug("/ %d ", postdiv);
268 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
269}
270
271int __init davinci_clk_init(struct davinci_clk *clocks)
272 {
273 struct davinci_clk *c;
274 struct clk *clk;
275
276 for (c = clocks; c->lk.clk; c++) {
277 clk = c->lk.clk;
278
279 if (clk->pll_data)
280 clk_pll_init(clk);
281
282 /* Calculate rates for PLL-derived clocks */
283 else if (clk->flags & CLK_PLL)
284 clk_sysclk_recalc(clk);
285
286 if (clk->lpsc)
287 clk->flags |= CLK_PSC;
288
289 clkdev_add(&c->lk);
290 clk_register(clk);
291
292 /* Turn on clocks that Linux doesn't otherwise manage */
293 if (clk->flags & ALWAYS_ENABLED)
294 clk_enable(clk);
264 } 295 }
265 296
266 return 0; 297 return 0;
@@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v)
285{ 316{
286} 317}
287 318
288static int davinci_ck_show(struct seq_file *m, void *v) 319#define CLKNAME_MAX 10 /* longest clock name */
320#define NEST_DELTA 2
321#define NEST_MAX 4
322
323static void
324dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
289{ 325{
290 struct clk *cp; 326 char *state;
327 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
328 struct clk *clk;
329 unsigned i;
330
331 if (parent->flags & CLK_PLL)
332 state = "pll";
333 else if (parent->flags & CLK_PSC)
334 state = "psc";
335 else
336 state = "";
337
338 /* <nest spaces> name <pad to end> */
339 memset(buf, ' ', sizeof(buf) - 1);
340 buf[sizeof(buf) - 1] = 0;
341 i = strlen(parent->name);
342 memcpy(buf + nest, parent->name,
343 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
344
345 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
346 buf, parent->usecount, state, clk_get_rate(parent));
347 /* REVISIT show device associations too */
348
349 /* cost is now small, but not linear... */
350 list_for_each_entry(clk, &clocks, node) {
351 if (clk->parent == parent)
352 dump_clock(s, nest + NEST_DELTA, clk);
353 }
354}
291 355
292 list_for_each_entry(cp, &clocks, node) 356static int davinci_ck_show(struct seq_file *m, void *v)
293 seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); 357{
358 /* Show clock tree; we know the main oscillator is first.
359 * We trust nonzero usecounts equate to PSC enables...
360 */
361 mutex_lock(&clocks_mutex);
362 if (!list_empty(&clocks))
363 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
364 mutex_unlock(&clocks_mutex);
294 365
295 return 0; 366 return 0;
296} 367}
@@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void)
321 392
322} 393}
323__initcall(davinci_ck_proc_init); 394__initcall(davinci_ck_proc_init);
324#endif /* CONFIG_DEBUG_PROC_FS */ 395#endif /* CONFIG_DEBUG_PROC_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ed47079a52e4..35736ec202f8 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -1,7 +1,8 @@
1/* 1/*
2 * TI DaVinci clock definitions 2 * TI DaVinci clock definitions
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -11,23 +12,85 @@
11#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
12#define __ARCH_ARM_DAVINCI_CLOCK_H 13#define __ARCH_ARM_DAVINCI_CLOCK_H
13 14
15#include <linux/list.h>
16#include <asm/clkdev.h>
17
18#define DAVINCI_PLL1_BASE 0x01c40800
19#define DAVINCI_PLL2_BASE 0x01c40c00
20#define MAX_PLL 2
21
22/* PLL/Reset register offsets */
23#define PLLCTL 0x100
24#define PLLCTL_PLLEN BIT(0)
25#define PLLCTL_CLKMODE BIT(8)
26
27#define PLLM 0x110
28#define PLLM_PLLM_MASK 0xff
29
30#define PREDIV 0x114
31#define PLLDIV1 0x118
32#define PLLDIV2 0x11c
33#define PLLDIV3 0x120
34#define POSTDIV 0x128
35#define BPDIV 0x12c
36#define PLLCMD 0x138
37#define PLLSTAT 0x13c
38#define PLLALNCTL 0x140
39#define PLLDCHANGE 0x144
40#define PLLCKEN 0x148
41#define PLLCKSTAT 0x14c
42#define PLLSYSTAT 0x150
43#define PLLDIV4 0x160
44#define PLLDIV5 0x164
45#define PLLDIV6 0x168
46#define PLLDIV7 0x16c
47#define PLLDIV8 0x170
48#define PLLDIV9 0x174
49#define PLLDIV_EN BIT(15)
50#define PLLDIV_RATIO_MASK 0x1f
51
52struct pll_data {
53 u32 phys_base;
54 void __iomem *base;
55 u32 num;
56 u32 flags;
57 u32 input_rate;
58};
59#define PLL_HAS_PREDIV 0x01
60#define PLL_HAS_POSTDIV 0x02
61
14struct clk { 62struct clk {
15 struct list_head node; 63 struct list_head node;
16 struct module *owner; 64 struct module *owner;
17 const char *name; 65 const char *name;
18 unsigned int *rate; 66 unsigned long rate;
19 int id; 67 u8 usecount;
20 __s8 usecount; 68 u8 flags;
21 __u8 flags; 69 u8 lpsc;
22 __u8 lpsc; 70 struct clk *parent;
71 struct pll_data *pll_data;
72 u32 div_reg;
23}; 73};
24 74
25/* Clock flags */ 75/* Clock flags */
26#define RATE_CKCTL 1 76#define ALWAYS_ENABLED BIT(1)
27#define RATE_FIXED 2 77#define CLK_PSC BIT(2)
28#define RATE_PROPAGATES 4 78#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
29#define VIRTUAL_CLOCK 8 79#define CLK_PLL BIT(4) /* PLL-derived clock */
30#define ALWAYS_ENABLED 16 80#define PRE_PLL BIT(5) /* source is before PLL mult/div */
31#define ENABLE_REG_32BIT 32 81
82struct davinci_clk {
83 struct clk_lookup lk;
84};
85
86#define CLK(dev, con, ck) \
87 { \
88 .lk = { \
89 .dev_id = dev, \
90 .con_id = con, \
91 .clk = ck, \
92 }, \
93 }
32 94
95int davinci_clk_init(struct davinci_clk *clocks);
33#endif 96#endif
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 808633f9f03c..a31370b93dd2 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -21,6 +21,10 @@
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/i2c.h> 22#include <mach/i2c.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/mux.h>
26
27#define DAVINCI_I2C_BASE 0x01C21000
24 28
25static struct resource i2c_resources[] = { 29static struct resource i2c_resources[] = {
26 { 30 {
@@ -43,6 +47,9 @@ static struct platform_device davinci_i2c_device = {
43 47
44void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) 48void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
45{ 49{
50 if (cpu_is_davinci_dm644x())
51 davinci_cfg_reg(DM644X_I2C);
52
46 davinci_i2c_device.dev.platform_data = pdata; 53 davinci_i2c_device.dev.platform_data = pdata;
47 (void) platform_device_register(&davinci_i2c_device); 54 (void) platform_device_register(&davinci_i2c_device);
48} 55}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
new file mode 100644
index 000000000000..d428ef192eac
--- /dev/null
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -0,0 +1,461 @@
1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <mach/dm644x.h>
17#include <mach/clock.h>
18#include <mach/cputype.h>
19#include <mach/edma.h>
20#include <mach/irqs.h>
21#include <mach/psc.h>
22#include <mach/mux.h>
23
24#include "clock.h"
25#include "mux.h"
26
27/*
28 * Device specific clocks
29 */
30#define DM644X_REF_FREQ 27000000
31
32static struct pll_data pll1_data = {
33 .num = 1,
34 .phys_base = DAVINCI_PLL1_BASE,
35};
36
37static struct pll_data pll2_data = {
38 .num = 2,
39 .phys_base = DAVINCI_PLL2_BASE,
40};
41
42static struct clk ref_clk = {
43 .name = "ref_clk",
44 .rate = DM644X_REF_FREQ,
45};
46
47static struct clk pll1_clk = {
48 .name = "pll1",
49 .parent = &ref_clk,
50 .pll_data = &pll1_data,
51 .flags = CLK_PLL,
52};
53
54static struct clk pll1_sysclk1 = {
55 .name = "pll1_sysclk1",
56 .parent = &pll1_clk,
57 .flags = CLK_PLL,
58 .div_reg = PLLDIV1,
59};
60
61static struct clk pll1_sysclk2 = {
62 .name = "pll1_sysclk2",
63 .parent = &pll1_clk,
64 .flags = CLK_PLL,
65 .div_reg = PLLDIV2,
66};
67
68static struct clk pll1_sysclk3 = {
69 .name = "pll1_sysclk3",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV3,
73};
74
75static struct clk pll1_sysclk5 = {
76 .name = "pll1_sysclk5",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV5,
80};
81
82static struct clk pll1_aux_clk = {
83 .name = "pll1_aux_clk",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL | PRE_PLL,
86};
87
88static struct clk pll1_sysclkbp = {
89 .name = "pll1_sysclkbp",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL | PRE_PLL,
92 .div_reg = BPDIV
93};
94
95static struct clk pll2_clk = {
96 .name = "pll2",
97 .parent = &ref_clk,
98 .pll_data = &pll2_data,
99 .flags = CLK_PLL,
100};
101
102static struct clk pll2_sysclk1 = {
103 .name = "pll2_sysclk1",
104 .parent = &pll2_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV1,
107};
108
109static struct clk pll2_sysclk2 = {
110 .name = "pll2_sysclk2",
111 .parent = &pll2_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV2,
114};
115
116static struct clk pll2_sysclkbp = {
117 .name = "pll2_sysclkbp",
118 .parent = &pll2_clk,
119 .flags = CLK_PLL | PRE_PLL,
120 .div_reg = BPDIV
121};
122
123static struct clk dsp_clk = {
124 .name = "dsp",
125 .parent = &pll1_sysclk1,
126 .lpsc = DAVINCI_LPSC_GEM,
127 .flags = PSC_DSP,
128 .usecount = 1, /* REVISIT how to disable? */
129};
130
131static struct clk arm_clk = {
132 .name = "arm",
133 .parent = &pll1_sysclk2,
134 .lpsc = DAVINCI_LPSC_ARM,
135 .flags = ALWAYS_ENABLED,
136};
137
138static struct clk vicp_clk = {
139 .name = "vicp",
140 .parent = &pll1_sysclk2,
141 .lpsc = DAVINCI_LPSC_IMCOP,
142 .flags = PSC_DSP,
143 .usecount = 1, /* REVISIT how to disable? */
144};
145
146static struct clk vpss_master_clk = {
147 .name = "vpss_master",
148 .parent = &pll1_sysclk3,
149 .lpsc = DAVINCI_LPSC_VPSSMSTR,
150 .flags = CLK_PSC,
151};
152
153static struct clk vpss_slave_clk = {
154 .name = "vpss_slave",
155 .parent = &pll1_sysclk3,
156 .lpsc = DAVINCI_LPSC_VPSSSLV,
157};
158
159static struct clk uart0_clk = {
160 .name = "uart0",
161 .parent = &pll1_aux_clk,
162 .lpsc = DAVINCI_LPSC_UART0,
163};
164
165static struct clk uart1_clk = {
166 .name = "uart1",
167 .parent = &pll1_aux_clk,
168 .lpsc = DAVINCI_LPSC_UART1,
169};
170
171static struct clk uart2_clk = {
172 .name = "uart2",
173 .parent = &pll1_aux_clk,
174 .lpsc = DAVINCI_LPSC_UART2,
175};
176
177static struct clk emac_clk = {
178 .name = "emac",
179 .parent = &pll1_sysclk5,
180 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
181};
182
183static struct clk i2c_clk = {
184 .name = "i2c",
185 .parent = &pll1_aux_clk,
186 .lpsc = DAVINCI_LPSC_I2C,
187};
188
189static struct clk ide_clk = {
190 .name = "ide",
191 .parent = &pll1_sysclk5,
192 .lpsc = DAVINCI_LPSC_ATA,
193};
194
195static struct clk asp_clk = {
196 .name = "asp0",
197 .parent = &pll1_sysclk5,
198 .lpsc = DAVINCI_LPSC_McBSP,
199};
200
201static struct clk mmcsd_clk = {
202 .name = "mmcsd",
203 .parent = &pll1_sysclk5,
204 .lpsc = DAVINCI_LPSC_MMC_SD,
205};
206
207static struct clk spi_clk = {
208 .name = "spi",
209 .parent = &pll1_sysclk5,
210 .lpsc = DAVINCI_LPSC_SPI,
211};
212
213static struct clk gpio_clk = {
214 .name = "gpio",
215 .parent = &pll1_sysclk5,
216 .lpsc = DAVINCI_LPSC_GPIO,
217};
218
219static struct clk usb_clk = {
220 .name = "usb",
221 .parent = &pll1_sysclk5,
222 .lpsc = DAVINCI_LPSC_USB,
223};
224
225static struct clk vlynq_clk = {
226 .name = "vlynq",
227 .parent = &pll1_sysclk5,
228 .lpsc = DAVINCI_LPSC_VLYNQ,
229};
230
231static struct clk aemif_clk = {
232 .name = "aemif",
233 .parent = &pll1_sysclk5,
234 .lpsc = DAVINCI_LPSC_AEMIF,
235};
236
237static struct clk pwm0_clk = {
238 .name = "pwm0",
239 .parent = &pll1_aux_clk,
240 .lpsc = DAVINCI_LPSC_PWM0,
241};
242
243static struct clk pwm1_clk = {
244 .name = "pwm1",
245 .parent = &pll1_aux_clk,
246 .lpsc = DAVINCI_LPSC_PWM1,
247};
248
249static struct clk pwm2_clk = {
250 .name = "pwm2",
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_PWM2,
253};
254
255static struct clk timer0_clk = {
256 .name = "timer0",
257 .parent = &pll1_aux_clk,
258 .lpsc = DAVINCI_LPSC_TIMER0,
259};
260
261static struct clk timer1_clk = {
262 .name = "timer1",
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_TIMER1,
265};
266
267static struct clk timer2_clk = {
268 .name = "timer2",
269 .parent = &pll1_aux_clk,
270 .lpsc = DAVINCI_LPSC_TIMER2,
271 .usecount = 1, /* REVISIT: why cant' this be disabled? */
272};
273
274struct davinci_clk dm644x_clks[] = {
275 CLK(NULL, "ref", &ref_clk),
276 CLK(NULL, "pll1", &pll1_clk),
277 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
278 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
279 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
280 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
281 CLK(NULL, "pll1_aux", &pll1_aux_clk),
282 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
283 CLK(NULL, "pll2", &pll2_clk),
284 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
285 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
286 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
287 CLK(NULL, "dsp", &dsp_clk),
288 CLK(NULL, "arm", &arm_clk),
289 CLK(NULL, "vicp", &vicp_clk),
290 CLK(NULL, "vpss_master", &vpss_master_clk),
291 CLK(NULL, "vpss_slave", &vpss_slave_clk),
292 CLK(NULL, "arm", &arm_clk),
293 CLK(NULL, "uart0", &uart0_clk),
294 CLK(NULL, "uart1", &uart1_clk),
295 CLK(NULL, "uart2", &uart2_clk),
296 CLK("davinci_emac.1", NULL, &emac_clk),
297 CLK("i2c_davinci.1", NULL, &i2c_clk),
298 CLK("palm_bk3710", NULL, &ide_clk),
299 CLK("soc-audio.0", NULL, &asp_clk),
300 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
301 CLK(NULL, "spi", &spi_clk),
302 CLK(NULL, "gpio", &gpio_clk),
303 CLK(NULL, "usb", &usb_clk),
304 CLK(NULL, "vlynq", &vlynq_clk),
305 CLK(NULL, "aemif", &aemif_clk),
306 CLK(NULL, "pwm0", &pwm0_clk),
307 CLK(NULL, "pwm1", &pwm1_clk),
308 CLK(NULL, "pwm2", &pwm2_clk),
309 CLK(NULL, "timer0", &timer0_clk),
310 CLK(NULL, "timer1", &timer1_clk),
311 CLK("watchdog", NULL, &timer2_clk),
312 CLK(NULL, NULL, NULL),
313};
314
315#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
316
317static struct resource dm644x_emac_resources[] = {
318 {
319 .start = DM644X_EMAC_BASE,
320 .end = DM644X_EMAC_BASE + 0x47ff,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .start = IRQ_EMACINT,
325 .end = IRQ_EMACINT,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device dm644x_emac_device = {
331 .name = "davinci_emac",
332 .id = 1,
333 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
334 .resource = dm644x_emac_resources,
335};
336
337#endif
338
339/*
340 * Device specific mux setup
341 *
342 * soc description mux mode mode mux dbg
343 * reg offset mask mode
344 */
345static const struct mux_config dm644x_pins[] = {
346MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
347MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
348MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
349
350MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
351
352MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
353
354MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
355
356MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
357
358MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
359
360MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
361MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
362
363MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
364
365MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
366
367MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
368
369MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
370MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
371MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
372
373MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
374
375MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
376
377MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
378MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
379MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
380MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
381
382MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
383
384MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
385MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
386};
387
388
389/*----------------------------------------------------------------------*/
390
391static const s8 dma_chan_dm644x_no_event[] = {
392 0, 1, 12, 13, 14,
393 15, 25, 30, 31, 45,
394 46, 47, 55, 56, 57,
395 58, 59, 60, 61, 62,
396 63,
397 -1
398};
399
400static struct edma_soc_info dm644x_edma_info = {
401 .n_channel = 64,
402 .n_region = 4,
403 .n_slot = 128,
404 .n_tc = 2,
405 .noevent = dma_chan_dm644x_no_event,
406};
407
408static struct resource edma_resources[] = {
409 {
410 .name = "edma_cc",
411 .start = 0x01c00000,
412 .end = 0x01c00000 + SZ_64K - 1,
413 .flags = IORESOURCE_MEM,
414 },
415 {
416 .name = "edma_tc0",
417 .start = 0x01c10000,
418 .end = 0x01c10000 + SZ_1K - 1,
419 .flags = IORESOURCE_MEM,
420 },
421 {
422 .name = "edma_tc1",
423 .start = 0x01c10400,
424 .end = 0x01c10400 + SZ_1K - 1,
425 .flags = IORESOURCE_MEM,
426 },
427 {
428 .start = IRQ_CCINT0,
429 .flags = IORESOURCE_IRQ,
430 },
431 {
432 .start = IRQ_CCERRINT,
433 .flags = IORESOURCE_IRQ,
434 },
435 /* not using TC*_ERR */
436};
437
438static struct platform_device dm644x_edma_device = {
439 .name = "edma",
440 .id = -1,
441 .dev.platform_data = &dm644x_edma_info,
442 .num_resources = ARRAY_SIZE(edma_resources),
443 .resource = edma_resources,
444};
445
446/*----------------------------------------------------------------------*/
447void __init dm644x_init(void)
448{
449 davinci_clk_init(dm644x_clks);
450 davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
451}
452
453static int __init dm644x_init_devices(void)
454{
455 if (!cpu_is_davinci_dm644x())
456 return 0;
457
458 platform_device_register(&dm644x_edma_device);
459 return 0;
460}
461postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
new file mode 100644
index 000000000000..15e9eb158bb7
--- /dev/null
+++ b/arch/arm/mach-davinci/dma.c
@@ -0,0 +1,1135 @@
1/*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/compiler.h>
28#include <linux/io.h>
29
30#include <mach/cputype.h>
31#include <mach/memory.h>
32#include <mach/hardware.h>
33#include <mach/irqs.h>
34#include <mach/edma.h>
35#include <mach/mux.h>
36
37
38/* Offsets matching "struct edmacc_param" */
39#define PARM_OPT 0x00
40#define PARM_SRC 0x04
41#define PARM_A_B_CNT 0x08
42#define PARM_DST 0x0c
43#define PARM_SRC_DST_BIDX 0x10
44#define PARM_LINK_BCNTRLD 0x14
45#define PARM_SRC_DST_CIDX 0x18
46#define PARM_CCNT 0x1c
47
48#define PARM_SIZE 0x20
49
50/* Offsets for EDMA CC global channel registers and their shadows */
51#define SH_ER 0x00 /* 64 bits */
52#define SH_ECR 0x08 /* 64 bits */
53#define SH_ESR 0x10 /* 64 bits */
54#define SH_CER 0x18 /* 64 bits */
55#define SH_EER 0x20 /* 64 bits */
56#define SH_EECR 0x28 /* 64 bits */
57#define SH_EESR 0x30 /* 64 bits */
58#define SH_SER 0x38 /* 64 bits */
59#define SH_SECR 0x40 /* 64 bits */
60#define SH_IER 0x50 /* 64 bits */
61#define SH_IECR 0x58 /* 64 bits */
62#define SH_IESR 0x60 /* 64 bits */
63#define SH_IPR 0x68 /* 64 bits */
64#define SH_ICR 0x70 /* 64 bits */
65#define SH_IEVAL 0x78
66#define SH_QER 0x80
67#define SH_QEER 0x84
68#define SH_QEECR 0x88
69#define SH_QEESR 0x8c
70#define SH_QSER 0x90
71#define SH_QSECR 0x94
72#define SH_SIZE 0x200
73
74/* Offsets for EDMA CC global registers */
75#define EDMA_REV 0x0000
76#define EDMA_CCCFG 0x0004
77#define EDMA_QCHMAP 0x0200 /* 8 registers */
78#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
79#define EDMA_QDMAQNUM 0x0260
80#define EDMA_QUETCMAP 0x0280
81#define EDMA_QUEPRI 0x0284
82#define EDMA_EMR 0x0300 /* 64 bits */
83#define EDMA_EMCR 0x0308 /* 64 bits */
84#define EDMA_QEMR 0x0310
85#define EDMA_QEMCR 0x0314
86#define EDMA_CCERR 0x0318
87#define EDMA_CCERRCLR 0x031c
88#define EDMA_EEVAL 0x0320
89#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
90#define EDMA_QRAE 0x0380 /* 4 registers */
91#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
92#define EDMA_QSTAT 0x0600 /* 2 registers */
93#define EDMA_QWMTHRA 0x0620
94#define EDMA_QWMTHRB 0x0624
95#define EDMA_CCSTAT 0x0640
96
97#define EDMA_M 0x1000 /* global channel registers */
98#define EDMA_ECR 0x1008
99#define EDMA_ECRH 0x100C
100#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
101#define EDMA_PARM 0x4000 /* 128 param entries */
102
103#define DAVINCI_DMA_3PCC_BASE 0x01C00000
104
105#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
106
107#define EDMA_MAX_DMACH 64
108#define EDMA_MAX_PARAMENTRY 512
109#define EDMA_MAX_EVQUE 2 /* FIXME too small */
110
111
112/*****************************************************************************/
113
114static void __iomem *edmacc_regs_base;
115
116static inline unsigned int edma_read(int offset)
117{
118 return (unsigned int)__raw_readl(edmacc_regs_base + offset);
119}
120
121static inline void edma_write(int offset, int val)
122{
123 __raw_writel(val, edmacc_regs_base + offset);
124}
125static inline void edma_modify(int offset, unsigned and, unsigned or)
126{
127 unsigned val = edma_read(offset);
128 val &= and;
129 val |= or;
130 edma_write(offset, val);
131}
132static inline void edma_and(int offset, unsigned and)
133{
134 unsigned val = edma_read(offset);
135 val &= and;
136 edma_write(offset, val);
137}
138static inline void edma_or(int offset, unsigned or)
139{
140 unsigned val = edma_read(offset);
141 val |= or;
142 edma_write(offset, val);
143}
144static inline unsigned int edma_read_array(int offset, int i)
145{
146 return edma_read(offset + (i << 2));
147}
148static inline void edma_write_array(int offset, int i, unsigned val)
149{
150 edma_write(offset + (i << 2), val);
151}
152static inline void edma_modify_array(int offset, int i,
153 unsigned and, unsigned or)
154{
155 edma_modify(offset + (i << 2), and, or);
156}
157static inline void edma_or_array(int offset, int i, unsigned or)
158{
159 edma_or(offset + (i << 2), or);
160}
161static inline void edma_or_array2(int offset, int i, int j, unsigned or)
162{
163 edma_or(offset + ((i*2 + j) << 2), or);
164}
165static inline void edma_write_array2(int offset, int i, int j, unsigned val)
166{
167 edma_write(offset + ((i*2 + j) << 2), val);
168}
169static inline unsigned int edma_shadow0_read(int offset)
170{
171 return edma_read(EDMA_SHADOW0 + offset);
172}
173static inline unsigned int edma_shadow0_read_array(int offset, int i)
174{
175 return edma_read(EDMA_SHADOW0 + offset + (i << 2));
176}
177static inline void edma_shadow0_write(int offset, unsigned val)
178{
179 edma_write(EDMA_SHADOW0 + offset, val);
180}
181static inline void edma_shadow0_write_array(int offset, int i, unsigned val)
182{
183 edma_write(EDMA_SHADOW0 + offset + (i << 2), val);
184}
185static inline unsigned int edma_parm_read(int offset, int param_no)
186{
187 return edma_read(EDMA_PARM + offset + (param_no << 5));
188}
189static inline void edma_parm_write(int offset, int param_no, unsigned val)
190{
191 edma_write(EDMA_PARM + offset + (param_no << 5), val);
192}
193static inline void edma_parm_modify(int offset, int param_no,
194 unsigned and, unsigned or)
195{
196 edma_modify(EDMA_PARM + offset + (param_no << 5), and, or);
197}
198static inline void edma_parm_and(int offset, int param_no, unsigned and)
199{
200 edma_and(EDMA_PARM + offset + (param_no << 5), and);
201}
202static inline void edma_parm_or(int offset, int param_no, unsigned or)
203{
204 edma_or(EDMA_PARM + offset + (param_no << 5), or);
205}
206
207/*****************************************************************************/
208
209/* actual number of DMA channels and slots on this silicon */
210static unsigned num_channels;
211static unsigned num_slots;
212
213static struct dma_interrupt_data {
214 void (*callback)(unsigned channel, unsigned short ch_status,
215 void *data);
216 void *data;
217} intr_data[EDMA_MAX_DMACH];
218
219/* The edma_inuse bit for each PaRAM slot is clear unless the
220 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
221 */
222static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
223
224/* The edma_noevent bit for each channel is clear unless
225 * it doesn't trigger DMA events on this platform. It uses a
226 * bit of SOC-specific initialization code.
227 */
228static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
229
230/* dummy param set used to (re)initialize parameter RAM slots */
231static const struct edmacc_param dummy_paramset = {
232 .link_bcntrld = 0xffff,
233 .ccnt = 1,
234};
235
236static const int __initconst
237queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
238/* {event queue no, TC no} */
239 {0, 0},
240 {1, 1},
241 {-1, -1}
242};
243
244static const int __initconst
245queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
246 /* {event queue no, Priority} */
247 {0, 3},
248 {1, 7},
249 {-1, -1}
250};
251
252/*****************************************************************************/
253
254static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
255{
256 int bit = (ch_no & 0x7) * 4;
257
258 /* default to low priority queue */
259 if (queue_no == EVENTQ_DEFAULT)
260 queue_no = EVENTQ_1;
261
262 queue_no &= 7;
263 edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
264 ~(0x7 << bit), queue_no << bit);
265}
266
267static void __init map_queue_tc(int queue_no, int tc_no)
268{
269 int bit = queue_no * 4;
270 edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
271}
272
273static void __init assign_priority_to_queue(int queue_no, int priority)
274{
275 int bit = queue_no * 4;
276 edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
277}
278
279static inline void
280setup_dma_interrupt(unsigned lch,
281 void (*callback)(unsigned channel, u16 ch_status, void *data),
282 void *data)
283{
284 if (!callback) {
285 edma_shadow0_write_array(SH_IECR, lch >> 5,
286 (1 << (lch & 0x1f)));
287 }
288
289 intr_data[lch].callback = callback;
290 intr_data[lch].data = data;
291
292 if (callback) {
293 edma_shadow0_write_array(SH_ICR, lch >> 5,
294 (1 << (lch & 0x1f)));
295 edma_shadow0_write_array(SH_IESR, lch >> 5,
296 (1 << (lch & 0x1f)));
297 }
298}
299
300/******************************************************************************
301 *
302 * DMA interrupt handler
303 *
304 *****************************************************************************/
305static irqreturn_t dma_irq_handler(int irq, void *data)
306{
307 int i;
308 unsigned int cnt = 0;
309
310 dev_dbg(data, "dma_irq_handler\n");
311
312 if ((edma_shadow0_read_array(SH_IPR, 0) == 0)
313 && (edma_shadow0_read_array(SH_IPR, 1) == 0))
314 return IRQ_NONE;
315
316 while (1) {
317 int j;
318 if (edma_shadow0_read_array(SH_IPR, 0))
319 j = 0;
320 else if (edma_shadow0_read_array(SH_IPR, 1))
321 j = 1;
322 else
323 break;
324 dev_dbg(data, "IPR%d %08x\n", j,
325 edma_shadow0_read_array(SH_IPR, j));
326 for (i = 0; i < 32; i++) {
327 int k = (j << 5) + i;
328 if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) {
329 /* Clear the corresponding IPR bits */
330 edma_shadow0_write_array(SH_ICR, j, (1 << i));
331 if (intr_data[k].callback) {
332 intr_data[k].callback(k, DMA_COMPLETE,
333 intr_data[k].data);
334 }
335 }
336 }
337 cnt++;
338 if (cnt > 10)
339 break;
340 }
341 edma_shadow0_write(SH_IEVAL, 1);
342 return IRQ_HANDLED;
343}
344
345/******************************************************************************
346 *
347 * DMA error interrupt handler
348 *
349 *****************************************************************************/
350static irqreturn_t dma_ccerr_handler(int irq, void *data)
351{
352 int i;
353 unsigned int cnt = 0;
354
355 dev_dbg(data, "dma_ccerr_handler\n");
356
357 if ((edma_read_array(EDMA_EMR, 0) == 0) &&
358 (edma_read_array(EDMA_EMR, 1) == 0) &&
359 (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0))
360 return IRQ_NONE;
361
362 while (1) {
363 int j = -1;
364 if (edma_read_array(EDMA_EMR, 0))
365 j = 0;
366 else if (edma_read_array(EDMA_EMR, 1))
367 j = 1;
368 if (j >= 0) {
369 dev_dbg(data, "EMR%d %08x\n", j,
370 edma_read_array(EDMA_EMR, j));
371 for (i = 0; i < 32; i++) {
372 int k = (j << 5) + i;
373 if (edma_read_array(EDMA_EMR, j) & (1 << i)) {
374 /* Clear the corresponding EMR bits */
375 edma_write_array(EDMA_EMCR, j, 1 << i);
376 /* Clear any SER */
377 edma_shadow0_write_array(SH_SECR, j,
378 (1 << i));
379 if (intr_data[k].callback) {
380 intr_data[k].callback(k,
381 DMA_CC_ERROR,
382 intr_data
383 [k].data);
384 }
385 }
386 }
387 } else if (edma_read(EDMA_QEMR)) {
388 dev_dbg(data, "QEMR %02x\n",
389 edma_read(EDMA_QEMR));
390 for (i = 0; i < 8; i++) {
391 if (edma_read(EDMA_QEMR) & (1 << i)) {
392 /* Clear the corresponding IPR bits */
393 edma_write(EDMA_QEMCR, 1 << i);
394 edma_shadow0_write(SH_QSECR, (1 << i));
395
396 /* NOTE: not reported!! */
397 }
398 }
399 } else if (edma_read(EDMA_CCERR)) {
400 dev_dbg(data, "CCERR %08x\n",
401 edma_read(EDMA_CCERR));
402 /* FIXME: CCERR.BIT(16) ignored! much better
403 * to just write CCERRCLR with CCERR value...
404 */
405 for (i = 0; i < 8; i++) {
406 if (edma_read(EDMA_CCERR) & (1 << i)) {
407 /* Clear the corresponding IPR bits */
408 edma_write(EDMA_CCERRCLR, 1 << i);
409
410 /* NOTE: not reported!! */
411 }
412 }
413 }
414 if ((edma_read_array(EDMA_EMR, 0) == 0)
415 && (edma_read_array(EDMA_EMR, 1) == 0)
416 && (edma_read(EDMA_QEMR) == 0)
417 && (edma_read(EDMA_CCERR) == 0)) {
418 break;
419 }
420 cnt++;
421 if (cnt > 10)
422 break;
423 }
424 edma_write(EDMA_EEVAL, 1);
425 return IRQ_HANDLED;
426}
427
428/******************************************************************************
429 *
430 * Transfer controller error interrupt handlers
431 *
432 *****************************************************************************/
433
434#define tc_errs_handled false /* disabled as long as they're NOPs */
435
436static irqreturn_t dma_tc0err_handler(int irq, void *data)
437{
438 dev_dbg(data, "dma_tc0err_handler\n");
439 return IRQ_HANDLED;
440}
441
442static irqreturn_t dma_tc1err_handler(int irq, void *data)
443{
444 dev_dbg(data, "dma_tc1err_handler\n");
445 return IRQ_HANDLED;
446}
447
448/*-----------------------------------------------------------------------*/
449
450/* Resource alloc/free: dma channels, parameter RAM slots */
451
452/**
453 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
454 * @channel: specific channel to allocate; negative for "any unmapped channel"
455 * @callback: optional; to be issued on DMA completion or errors
456 * @data: passed to callback
457 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
458 * Controller (TC) executes requests using this channel. Use
459 * EVENTQ_DEFAULT unless you really need a high priority queue.
460 *
461 * This allocates a DMA channel and its associated parameter RAM slot.
462 * The parameter RAM is initialized to hold a dummy transfer.
463 *
464 * Normal use is to pass a specific channel number as @channel, to make
465 * use of hardware events mapped to that channel. When the channel will
466 * be used only for software triggering or event chaining, channels not
467 * mapped to hardware events (or mapped to unused events) are preferable.
468 *
469 * DMA transfers start from a channel using edma_start(), or by
470 * chaining. When the transfer described in that channel's parameter RAM
471 * slot completes, that slot's data may be reloaded through a link.
472 *
473 * DMA errors are only reported to the @callback associated with the
474 * channel driving that transfer, but transfer completion callbacks can
475 * be sent to another channel under control of the TCC field in
476 * the option word of the transfer's parameter RAM set. Drivers must not
477 * use DMA transfer completion callbacks for channels they did not allocate.
478 * (The same applies to TCC codes used in transfer chaining.)
479 *
480 * Returns the number of the channel, else negative errno.
481 */
482int edma_alloc_channel(int channel,
483 void (*callback)(unsigned channel, u16 ch_status, void *data),
484 void *data,
485 enum dma_event_q eventq_no)
486{
487 if (channel < 0) {
488 channel = 0;
489 for (;;) {
490 channel = find_next_bit(edma_noevent,
491 num_channels, channel);
492 if (channel == num_channels)
493 return -ENOMEM;
494 if (!test_and_set_bit(channel, edma_inuse))
495 break;
496 channel++;
497 }
498 } else if (channel >= num_channels) {
499 return -EINVAL;
500 } else if (test_and_set_bit(channel, edma_inuse)) {
501 return -EBUSY;
502 }
503
504 /* ensure access through shadow region 0 */
505 edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
506
507 /* ensure no events are pending */
508 edma_stop(channel);
509 memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
510 &dummy_paramset, PARM_SIZE);
511
512 if (callback)
513 setup_dma_interrupt(channel, callback, data);
514
515 map_dmach_queue(channel, eventq_no);
516
517 return channel;
518}
519EXPORT_SYMBOL(edma_alloc_channel);
520
521
522/**
523 * edma_free_channel - deallocate DMA channel
524 * @channel: dma channel returned from edma_alloc_channel()
525 *
526 * This deallocates the DMA channel and associated parameter RAM slot
527 * allocated by edma_alloc_channel().
528 *
529 * Callers are responsible for ensuring the channel is inactive, and
530 * will not be reactivated by linking, chaining, or software calls to
531 * edma_start().
532 */
533void edma_free_channel(unsigned channel)
534{
535 if (channel >= num_channels)
536 return;
537
538 setup_dma_interrupt(channel, NULL, NULL);
539 /* REVISIT should probably take out of shadow region 0 */
540
541 memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
542 &dummy_paramset, PARM_SIZE);
543 clear_bit(channel, edma_inuse);
544}
545EXPORT_SYMBOL(edma_free_channel);
546
547/**
548 * edma_alloc_slot - allocate DMA parameter RAM
549 * @slot: specific slot to allocate; negative for "any unused slot"
550 *
551 * This allocates a parameter RAM slot, initializing it to hold a
552 * dummy transfer. Slots allocated using this routine have not been
553 * mapped to a hardware DMA channel, and will normally be used by
554 * linking to them from a slot associated with a DMA channel.
555 *
556 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
557 * slots may be allocated on behalf of DSP firmware.
558 *
559 * Returns the number of the slot, else negative errno.
560 */
561int edma_alloc_slot(int slot)
562{
563 if (slot < 0) {
564 slot = num_channels;
565 for (;;) {
566 slot = find_next_zero_bit(edma_inuse,
567 num_slots, slot);
568 if (slot == num_slots)
569 return -ENOMEM;
570 if (!test_and_set_bit(slot, edma_inuse))
571 break;
572 }
573 } else if (slot < num_channels || slot >= num_slots) {
574 return -EINVAL;
575 } else if (test_and_set_bit(slot, edma_inuse)) {
576 return -EBUSY;
577 }
578
579 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
580 &dummy_paramset, PARM_SIZE);
581
582 return slot;
583}
584EXPORT_SYMBOL(edma_alloc_slot);
585
586/**
587 * edma_free_slot - deallocate DMA parameter RAM
588 * @slot: parameter RAM slot returned from edma_alloc_slot()
589 *
590 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
591 * Callers are responsible for ensuring the slot is inactive, and will
592 * not be activated.
593 */
594void edma_free_slot(unsigned slot)
595{
596 if (slot < num_channels || slot >= num_slots)
597 return;
598
599 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
600 &dummy_paramset, PARM_SIZE);
601 clear_bit(slot, edma_inuse);
602}
603EXPORT_SYMBOL(edma_free_slot);
604
605/*-----------------------------------------------------------------------*/
606
607/* Parameter RAM operations (i) -- read/write partial slots */
608
609/**
610 * edma_set_src - set initial DMA source address in parameter RAM slot
611 * @slot: parameter RAM slot being configured
612 * @src_port: physical address of source (memory, controller FIFO, etc)
613 * @addressMode: INCR, except in very rare cases
614 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
615 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
616 *
617 * Note that the source address is modified during the DMA transfer
618 * according to edma_set_src_index().
619 */
620void edma_set_src(unsigned slot, dma_addr_t src_port,
621 enum address_mode mode, enum fifo_width width)
622{
623 if (slot < num_slots) {
624 unsigned int i = edma_parm_read(PARM_OPT, slot);
625
626 if (mode) {
627 /* set SAM and program FWID */
628 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
629 } else {
630 /* clear SAM */
631 i &= ~SAM;
632 }
633 edma_parm_write(PARM_OPT, slot, i);
634
635 /* set the source port address
636 in source register of param structure */
637 edma_parm_write(PARM_SRC, slot, src_port);
638 }
639}
640EXPORT_SYMBOL(edma_set_src);
641
642/**
643 * edma_set_dest - set initial DMA destination address in parameter RAM slot
644 * @slot: parameter RAM slot being configured
645 * @dest_port: physical address of destination (memory, controller FIFO, etc)
646 * @addressMode: INCR, except in very rare cases
647 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
648 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
649 *
650 * Note that the destination address is modified during the DMA transfer
651 * according to edma_set_dest_index().
652 */
653void edma_set_dest(unsigned slot, dma_addr_t dest_port,
654 enum address_mode mode, enum fifo_width width)
655{
656 if (slot < num_slots) {
657 unsigned int i = edma_parm_read(PARM_OPT, slot);
658
659 if (mode) {
660 /* set DAM and program FWID */
661 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
662 } else {
663 /* clear DAM */
664 i &= ~DAM;
665 }
666 edma_parm_write(PARM_OPT, slot, i);
667 /* set the destination port address
668 in dest register of param structure */
669 edma_parm_write(PARM_DST, slot, dest_port);
670 }
671}
672EXPORT_SYMBOL(edma_set_dest);
673
674/**
675 * edma_get_position - returns the current transfer points
676 * @slot: parameter RAM slot being examined
677 * @src: pointer to source port position
678 * @dst: pointer to destination port position
679 *
680 * Returns current source and destination addresses for a particular
681 * parameter RAM slot. Its channel should not be active when this is called.
682 */
683void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
684{
685 struct edmacc_param temp;
686
687 edma_read_slot(slot, &temp);
688 if (src != NULL)
689 *src = temp.src;
690 if (dst != NULL)
691 *dst = temp.dst;
692}
693EXPORT_SYMBOL(edma_get_position);
694
695/**
696 * edma_set_src_index - configure DMA source address indexing
697 * @slot: parameter RAM slot being configured
698 * @src_bidx: byte offset between source arrays in a frame
699 * @src_cidx: byte offset between source frames in a block
700 *
701 * Offsets are specified to support either contiguous or discontiguous
702 * memory transfers, or repeated access to a hardware register, as needed.
703 * When accessing hardware registers, both offsets are normally zero.
704 */
705void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
706{
707 if (slot < num_slots) {
708 edma_parm_modify(PARM_SRC_DST_BIDX, slot,
709 0xffff0000, src_bidx);
710 edma_parm_modify(PARM_SRC_DST_CIDX, slot,
711 0xffff0000, src_cidx);
712 }
713}
714EXPORT_SYMBOL(edma_set_src_index);
715
716/**
717 * edma_set_dest_index - configure DMA destination address indexing
718 * @slot: parameter RAM slot being configured
719 * @dest_bidx: byte offset between destination arrays in a frame
720 * @dest_cidx: byte offset between destination frames in a block
721 *
722 * Offsets are specified to support either contiguous or discontiguous
723 * memory transfers, or repeated access to a hardware register, as needed.
724 * When accessing hardware registers, both offsets are normally zero.
725 */
726void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
727{
728 if (slot < num_slots) {
729 edma_parm_modify(PARM_SRC_DST_BIDX, slot,
730 0x0000ffff, dest_bidx << 16);
731 edma_parm_modify(PARM_SRC_DST_CIDX, slot,
732 0x0000ffff, dest_cidx << 16);
733 }
734}
735EXPORT_SYMBOL(edma_set_dest_index);
736
737/**
738 * edma_set_transfer_params - configure DMA transfer parameters
739 * @slot: parameter RAM slot being configured
740 * @acnt: how many bytes per array (at least one)
741 * @bcnt: how many arrays per frame (at least one)
742 * @ccnt: how many frames per block (at least one)
743 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
744 * the value to reload into bcnt when it decrements to zero
745 * @sync_mode: ASYNC or ABSYNC
746 *
747 * See the EDMA3 documentation to understand how to configure and link
748 * transfers using the fields in PaRAM slots. If you are not doing it
749 * all at once with edma_write_slot(), you will use this routine
750 * plus two calls each for source and destination, setting the initial
751 * address and saying how to index that address.
752 *
753 * An example of an A-Synchronized transfer is a serial link using a
754 * single word shift register. In that case, @acnt would be equal to
755 * that word size; the serial controller issues a DMA synchronization
756 * event to transfer each word, and memory access by the DMA transfer
757 * controller will be word-at-a-time.
758 *
759 * An example of an AB-Synchronized transfer is a device using a FIFO.
760 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
761 * The controller with the FIFO issues DMA synchronization events when
762 * the FIFO threshold is reached, and the DMA transfer controller will
763 * transfer one frame to (or from) the FIFO. It will probably use
764 * efficient burst modes to access memory.
765 */
766void edma_set_transfer_params(unsigned slot,
767 u16 acnt, u16 bcnt, u16 ccnt,
768 u16 bcnt_rld, enum sync_dimension sync_mode)
769{
770 if (slot < num_slots) {
771 edma_parm_modify(PARM_LINK_BCNTRLD, slot,
772 0x0000ffff, bcnt_rld << 16);
773 if (sync_mode == ASYNC)
774 edma_parm_and(PARM_OPT, slot, ~SYNCDIM);
775 else
776 edma_parm_or(PARM_OPT, slot, SYNCDIM);
777 /* Set the acount, bcount, ccount registers */
778 edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
779 edma_parm_write(PARM_CCNT, slot, ccnt);
780 }
781}
782EXPORT_SYMBOL(edma_set_transfer_params);
783
784/**
785 * edma_link - link one parameter RAM slot to another
786 * @from: parameter RAM slot originating the link
787 * @to: parameter RAM slot which is the link target
788 *
789 * The originating slot should not be part of any active DMA transfer.
790 */
791void edma_link(unsigned from, unsigned to)
792{
793 if (from >= num_slots)
794 return;
795 if (to >= num_slots)
796 return;
797 edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to));
798}
799EXPORT_SYMBOL(edma_link);
800
801/**
802 * edma_unlink - cut link from one parameter RAM slot
803 * @from: parameter RAM slot originating the link
804 *
805 * The originating slot should not be part of any active DMA transfer.
806 * Its link is set to 0xffff.
807 */
808void edma_unlink(unsigned from)
809{
810 if (from >= num_slots)
811 return;
812 edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff);
813}
814EXPORT_SYMBOL(edma_unlink);
815
816/*-----------------------------------------------------------------------*/
817
818/* Parameter RAM operations (ii) -- read/write whole parameter sets */
819
820/**
821 * edma_write_slot - write parameter RAM data for slot
822 * @slot: number of parameter RAM slot being modified
823 * @param: data to be written into parameter RAM slot
824 *
825 * Use this to assign all parameters of a transfer at once. This
826 * allows more efficient setup of transfers than issuing multiple
827 * calls to set up those parameters in small pieces, and provides
828 * complete control over all transfer options.
829 */
830void edma_write_slot(unsigned slot, const struct edmacc_param *param)
831{
832 if (slot >= num_slots)
833 return;
834 memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE);
835}
836EXPORT_SYMBOL(edma_write_slot);
837
838/**
839 * edma_read_slot - read parameter RAM data from slot
840 * @slot: number of parameter RAM slot being copied
841 * @param: where to store copy of parameter RAM data
842 *
843 * Use this to read data from a parameter RAM slot, perhaps to
844 * save them as a template for later reuse.
845 */
846void edma_read_slot(unsigned slot, struct edmacc_param *param)
847{
848 if (slot >= num_slots)
849 return;
850 memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE);
851}
852EXPORT_SYMBOL(edma_read_slot);
853
854/*-----------------------------------------------------------------------*/
855
856/* Various EDMA channel control operations */
857
858/**
859 * edma_pause - pause dma on a channel
860 * @channel: on which edma_start() has been called
861 *
862 * This temporarily disables EDMA hardware events on the specified channel,
863 * preventing them from triggering new transfers on its behalf
864 */
865void edma_pause(unsigned channel)
866{
867 if (channel < num_channels) {
868 unsigned int mask = (1 << (channel & 0x1f));
869
870 edma_shadow0_write_array(SH_EECR, channel >> 5, mask);
871 }
872}
873EXPORT_SYMBOL(edma_pause);
874
875/**
876 * edma_resume - resumes dma on a paused channel
877 * @channel: on which edma_pause() has been called
878 *
879 * This re-enables EDMA hardware events on the specified channel.
880 */
881void edma_resume(unsigned channel)
882{
883 if (channel < num_channels) {
884 unsigned int mask = (1 << (channel & 0x1f));
885
886 edma_shadow0_write_array(SH_EESR, channel >> 5, mask);
887 }
888}
889EXPORT_SYMBOL(edma_resume);
890
891/**
892 * edma_start - start dma on a channel
893 * @channel: channel being activated
894 *
895 * Channels with event associations will be triggered by their hardware
896 * events, and channels without such associations will be triggered by
897 * software. (At this writing there is no interface for using software
898 * triggers except with channels that don't support hardware triggers.)
899 *
900 * Returns zero on success, else negative errno.
901 */
902int edma_start(unsigned channel)
903{
904 if (channel < num_channels) {
905 int j = channel >> 5;
906 unsigned int mask = (1 << (channel & 0x1f));
907
908 /* EDMA channels without event association */
909 if (test_bit(channel, edma_noevent)) {
910 pr_debug("EDMA: ESR%d %08x\n", j,
911 edma_shadow0_read_array(SH_ESR, j));
912 edma_shadow0_write_array(SH_ESR, j, mask);
913 return 0;
914 }
915
916 /* EDMA channel with event association */
917 pr_debug("EDMA: ER%d %08x\n", j,
918 edma_shadow0_read_array(SH_ER, j));
919 /* Clear any pending error */
920 edma_write_array(EDMA_EMCR, j, mask);
921 /* Clear any SER */
922 edma_shadow0_write_array(SH_SECR, j, mask);
923 edma_shadow0_write_array(SH_EESR, j, mask);
924 pr_debug("EDMA: EER%d %08x\n", j,
925 edma_shadow0_read_array(SH_EER, j));
926 return 0;
927 }
928
929 return -EINVAL;
930}
931EXPORT_SYMBOL(edma_start);
932
933/**
934 * edma_stop - stops dma on the channel passed
935 * @channel: channel being deactivated
936 *
937 * When @lch is a channel, any active transfer is paused and
938 * all pending hardware events are cleared. The current transfer
939 * may not be resumed, and the channel's Parameter RAM should be
940 * reinitialized before being reused.
941 */
942void edma_stop(unsigned channel)
943{
944 if (channel < num_channels) {
945 int j = channel >> 5;
946 unsigned int mask = (1 << (channel & 0x1f));
947
948 edma_shadow0_write_array(SH_EECR, j, mask);
949 edma_shadow0_write_array(SH_ECR, j, mask);
950 edma_shadow0_write_array(SH_SECR, j, mask);
951 edma_write_array(EDMA_EMCR, j, mask);
952
953 pr_debug("EDMA: EER%d %08x\n", j,
954 edma_shadow0_read_array(SH_EER, j));
955
956 /* REVISIT: consider guarding against inappropriate event
957 * chaining by overwriting with dummy_paramset.
958 */
959 }
960}
961EXPORT_SYMBOL(edma_stop);
962
963/******************************************************************************
964 *
965 * It cleans ParamEntry qand bring back EDMA to initial state if media has
966 * been removed before EDMA has finished.It is usedful for removable media.
967 * Arguments:
968 * ch_no - channel no
969 *
970 * Return: zero on success, or corresponding error no on failure
971 *
972 * FIXME this should not be needed ... edma_stop() should suffice.
973 *
974 *****************************************************************************/
975
976void edma_clean_channel(unsigned channel)
977{
978 if (channel < num_channels) {
979 int j = (channel >> 5);
980 unsigned int mask = 1 << (channel & 0x1f);
981
982 pr_debug("EDMA: EMR%d %08x\n", j,
983 edma_read_array(EDMA_EMR, j));
984 edma_shadow0_write_array(SH_ECR, j, mask);
985 /* Clear the corresponding EMR bits */
986 edma_write_array(EDMA_EMCR, j, mask);
987 /* Clear any SER */
988 edma_shadow0_write_array(SH_SECR, j, mask);
989 edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3);
990 }
991}
992EXPORT_SYMBOL(edma_clean_channel);
993
994/*
995 * edma_clear_event - clear an outstanding event on the DMA channel
996 * Arguments:
997 * channel - channel number
998 */
999void edma_clear_event(unsigned channel)
1000{
1001 if (channel >= num_channels)
1002 return;
1003 if (channel < 32)
1004 edma_write(EDMA_ECR, 1 << channel);
1005 else
1006 edma_write(EDMA_ECRH, 1 << (channel - 32));
1007}
1008EXPORT_SYMBOL(edma_clear_event);
1009
1010/*-----------------------------------------------------------------------*/
1011
1012static int __init edma_probe(struct platform_device *pdev)
1013{
1014 struct edma_soc_info *info = pdev->dev.platform_data;
1015 int i;
1016 int status;
1017 const s8 *noevent;
1018 int irq = 0, err_irq = 0;
1019 struct resource *r;
1020 resource_size_t len;
1021
1022 if (!info)
1023 return -ENODEV;
1024
1025 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc");
1026 if (!r)
1027 return -ENODEV;
1028
1029 len = r->end - r->start + 1;
1030
1031 r = request_mem_region(r->start, len, r->name);
1032 if (!r)
1033 return -EBUSY;
1034
1035 edmacc_regs_base = ioremap(r->start, len);
1036 if (!edmacc_regs_base) {
1037 status = -EBUSY;
1038 goto fail1;
1039 }
1040
1041 num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH);
1042 num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY);
1043
1044 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base);
1045
1046 for (i = 0; i < num_slots; i++)
1047 memcpy_toio(edmacc_regs_base + PARM_OFFSET(i),
1048 &dummy_paramset, PARM_SIZE);
1049
1050 noevent = info->noevent;
1051 if (noevent) {
1052 while (*noevent != -1)
1053 set_bit(*noevent++, edma_noevent);
1054 }
1055
1056 irq = platform_get_irq(pdev, 0);
1057 status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev);
1058 if (status < 0) {
1059 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1060 irq, status);
1061 goto fail;
1062 }
1063
1064 err_irq = platform_get_irq(pdev, 1);
1065 status = request_irq(err_irq, dma_ccerr_handler, 0,
1066 "edma_error", &pdev->dev);
1067 if (status < 0) {
1068 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1069 err_irq, status);
1070 goto fail;
1071 }
1072
1073 if (tc_errs_handled) {
1074 status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1075 "edma_tc0", &pdev->dev);
1076 if (status < 0) {
1077 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1078 IRQ_TCERRINT0, status);
1079 return status;
1080 }
1081 status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1082 "edma_tc1", &pdev->dev);
1083 if (status < 0) {
1084 dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1085 IRQ_TCERRINT, status);
1086 return status;
1087 }
1088 }
1089
1090 /* Everything lives on transfer controller 1 until otherwise specified.
1091 * This way, long transfers on the low priority queue
1092 * started by the codec engine will not cause audio defects.
1093 */
1094 for (i = 0; i < num_channels; i++)
1095 map_dmach_queue(i, EVENTQ_1);
1096
1097 /* Event queue to TC mapping */
1098 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1099 map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]);
1100
1101 /* Event queue priority mapping */
1102 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1103 assign_priority_to_queue(queue_priority_mapping[i][0],
1104 queue_priority_mapping[i][1]);
1105
1106 for (i = 0; i < info->n_region; i++) {
1107 edma_write_array2(EDMA_DRAE, i, 0, 0x0);
1108 edma_write_array2(EDMA_DRAE, i, 1, 0x0);
1109 edma_write_array(EDMA_QRAE, i, 0x0);
1110 }
1111
1112 return 0;
1113
1114fail:
1115 if (err_irq)
1116 free_irq(err_irq, NULL);
1117 if (irq)
1118 free_irq(irq, NULL);
1119 iounmap(edmacc_regs_base);
1120fail1:
1121 release_mem_region(r->start, len);
1122 return status;
1123}
1124
1125
1126static struct platform_driver edma_driver = {
1127 .driver.name = "edma",
1128};
1129
1130static int __init edma_init(void)
1131{
1132 return platform_driver_probe(&edma_driver, edma_probe);
1133}
1134arch_initcall(edma_init);
1135
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b49e9d092aab..1aba41c6351e 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,7 @@
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/bitops.h> 21#include <linux/bitops.h>
22 22
23#include <mach/cputype.h>
23#include <mach/irqs.h> 24#include <mach/irqs.h>
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25#include <mach/gpio.h> 26#include <mach/gpio.h>
@@ -36,9 +37,10 @@ struct davinci_gpio {
36 37
37static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; 38static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38 39
40static unsigned __initdata ngpio;
39 41
40/* create a non-inlined version */ 42/* create a non-inlined version */
41static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio) 43static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
42{ 44{
43 return __gpio_to_controller(gpio); 45 return __gpio_to_controller(gpio);
44} 46}
@@ -114,9 +116,30 @@ static int __init davinci_gpio_setup(void)
114{ 116{
115 int i, base; 117 int i, base;
116 118
117 for (i = 0, base = 0; 119 /* The gpio banks conceptually expose a segmented bitmap,
118 i < ARRAY_SIZE(chips); 120 * and "ngpio" is one more than the largest zero-based
119 i++, base += 32) { 121 * bit index that's valid.
122 */
123 if (cpu_is_davinci_dm355()) { /* or dm335() */
124 ngpio = 104;
125 } else if (cpu_is_davinci_dm644x()) { /* or dm337() */
126 ngpio = 71;
127 } else if (cpu_is_davinci_dm646x()) {
128 /* NOTE: each bank has several "reserved" bits,
129 * unusable as GPIOs. Only 33 of the GPIO numbers
130 * are usable, and we're not rejecting the others.
131 */
132 ngpio = 43;
133 } else {
134 /* if cpu_is_davinci_dm643x() ngpio = 111 */
135 pr_err("GPIO setup: how many GPIOs?\n");
136 return -EINVAL;
137 }
138
139 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
140 ngpio = DAVINCI_N_GPIO;
141
142 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
120 chips[i].chip.label = "DaVinci"; 143 chips[i].chip.label = "DaVinci";
121 144
122 chips[i].chip.direction_input = davinci_direction_in; 145 chips[i].chip.direction_input = davinci_direction_in;
@@ -125,7 +148,7 @@ static int __init davinci_gpio_setup(void)
125 chips[i].chip.set = davinci_gpio_set; 148 chips[i].chip.set = davinci_gpio_set;
126 149
127 chips[i].chip.base = base; 150 chips[i].chip.base = base;
128 chips[i].chip.ngpio = DAVINCI_N_GPIO - base; 151 chips[i].chip.ngpio = ngpio - base;
129 if (chips[i].chip.ngpio > 32) 152 if (chips[i].chip.ngpio > 32)
130 chips[i].chip.ngpio = 32; 153 chips[i].chip.ngpio = 32;
131 154
@@ -143,11 +166,11 @@ pure_initcall(davinci_gpio_setup);
143 * We expect irqs will normally be set up as input pins, but they can also be 166 * We expect irqs will normally be set up as input pins, but they can also be
144 * used as output pins ... which is convenient for testing. 167 * used as output pins ... which is convenient for testing.
145 * 168 *
146 * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition 169 * NOTE: The first few GPIOs also have direct INTC hookups in addition
147 * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have 170 * to their GPIOBNK0 irq, with a bit less overhead but less flexibility
148 * a good way to hook those up ... 171 * on triggering (e.g. no edge options). We don't try to use those.
149 * 172 *
150 * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also 173 * All those INTC hookups (direct, plus several IRQ banks) can also
151 * serve as EDMA event triggers. 174 * serve as EDMA event triggers.
152 */ 175 */
153 176
@@ -235,29 +258,42 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
235} 258}
236 259
237/* 260/*
238 * NOTE: for suspend/resume, probably best to make a sysdev (and class) 261 * NOTE: for suspend/resume, probably best to make a platform_device with
239 * with its suspend/resume calls hooking into the results of the set_wake() 262 * suspend_late/resume_resume calls hooking into results of the set_wake()
240 * calls ... so if no gpios are wakeup events the clock can be disabled, 263 * calls ... so if no gpios are wakeup events the clock can be disabled,
241 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 264 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
242 * can be set appropriately for GPIOV33 pins. 265 * (dm6446) can be set appropriately for GPIOV33 pins.
243 */ 266 */
244 267
245static int __init davinci_gpio_irq_setup(void) 268static int __init davinci_gpio_irq_setup(void)
246{ 269{
247 unsigned gpio, irq, bank; 270 unsigned gpio, irq, bank;
271 unsigned bank_irq;
248 struct clk *clk; 272 struct clk *clk;
273 u32 binten = 0;
274
275 if (cpu_is_davinci_dm355()) { /* or dm335() */
276 bank_irq = IRQ_DM355_GPIOBNK0;
277 } else if (cpu_is_davinci_dm644x()) {
278 bank_irq = IRQ_GPIOBNK0;
279 } else if (cpu_is_davinci_dm646x()) {
280 bank_irq = IRQ_DM646X_GPIOBNK0;
281 } else {
282 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
283 return -EINVAL;
284 }
249 285
250 clk = clk_get(NULL, "gpio"); 286 clk = clk_get(NULL, "gpio");
251 if (IS_ERR(clk)) { 287 if (IS_ERR(clk)) {
252 printk(KERN_ERR "Error %ld getting gpio clock?\n", 288 printk(KERN_ERR "Error %ld getting gpio clock?\n",
253 PTR_ERR(clk)); 289 PTR_ERR(clk));
254 return 0; 290 return PTR_ERR(clk);
255 } 291 }
256
257 clk_enable(clk); 292 clk_enable(clk);
258 293
259 for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; 294 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
260 gpio < DAVINCI_N_GPIO; bank++) { 295 gpio < ngpio;
296 bank++, bank_irq++) {
261 struct gpio_controller *__iomem g = gpio2controller(gpio); 297 struct gpio_controller *__iomem g = gpio2controller(gpio);
262 unsigned i; 298 unsigned i;
263 299
@@ -265,28 +301,28 @@ static int __init davinci_gpio_irq_setup(void)
265 __raw_writel(~0, &g->clr_rising); 301 __raw_writel(~0, &g->clr_rising);
266 302
267 /* set up all irqs in this bank */ 303 /* set up all irqs in this bank */
268 set_irq_chained_handler(bank, gpio_irq_handler); 304 set_irq_chained_handler(bank_irq, gpio_irq_handler);
269 set_irq_chip_data(bank, g); 305 set_irq_chip_data(bank_irq, g);
270 set_irq_data(bank, (void *)irq); 306 set_irq_data(bank_irq, (void *)irq);
271 307
272 for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; 308 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
273 i++, irq++, gpio++) {
274 set_irq_chip(irq, &gpio_irqchip); 309 set_irq_chip(irq, &gpio_irqchip);
275 set_irq_chip_data(irq, g); 310 set_irq_chip_data(irq, g);
276 set_irq_handler(irq, handle_simple_irq); 311 set_irq_handler(irq, handle_simple_irq);
277 set_irq_flags(irq, IRQF_VALID); 312 set_irq_flags(irq, IRQF_VALID);
278 } 313 }
314
315 binten |= BIT(bank);
279 } 316 }
280 317
281 /* BINTEN -- per-bank interrupt enable. genirq would also let these 318 /* BINTEN -- per-bank interrupt enable. genirq would also let these
282 * bits be set/cleared dynamically. 319 * bits be set/cleared dynamically.
283 */ 320 */
284 __raw_writel(0x1f, (void *__iomem) 321 __raw_writel(binten, (void *__iomem)
285 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); 322 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
286 323
287 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 324 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
288 325
289 return 0; 326 return 0;
290} 327}
291
292arch_initcall(davinci_gpio_irq_setup); 328arch_initcall(davinci_gpio_irq_setup);
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
index bf067d604918..018b994cd794 100644
--- a/arch/arm/mach-davinci/id.c
+++ b/arch/arm/mach-davinci/id.c
@@ -15,7 +15,9 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#define JTAG_ID_BASE 0x01c40028 18#define JTAG_ID_BASE IO_ADDRESS(0x01c40028)
19
20static unsigned int davinci_revision;
19 21
20struct davinci_id { 22struct davinci_id {
21 u8 variant; /* JTAG ID bits 31:28 */ 23 u8 variant; /* JTAG ID bits 31:28 */
@@ -33,6 +35,20 @@ static struct davinci_id davinci_ids[] __initdata = {
33 .manufacturer = 0x017, 35 .manufacturer = 0x017,
34 .type = 0x64460000, 36 .type = 0x64460000,
35 }, 37 },
38 {
39 /* DM646X */
40 .part_no = 0xb770,
41 .variant = 0x0,
42 .manufacturer = 0x017,
43 .type = 0x64670000,
44 },
45 {
46 /* DM355 */
47 .part_no = 0xb73b,
48 .variant = 0x0,
49 .manufacturer = 0x00f,
50 .type = 0x03550000,
51 },
36}; 52};
37 53
38/* 54/*
@@ -42,7 +58,7 @@ static u16 __init davinci_get_part_no(void)
42{ 58{
43 u32 dev_id, part_no; 59 u32 dev_id, part_no;
44 60
45 dev_id = davinci_readl(JTAG_ID_BASE); 61 dev_id = __raw_readl(JTAG_ID_BASE);
46 62
47 part_no = ((dev_id >> 12) & 0xffff); 63 part_no = ((dev_id >> 12) & 0xffff);
48 64
@@ -56,13 +72,19 @@ static u8 __init davinci_get_variant(void)
56{ 72{
57 u32 variant; 73 u32 variant;
58 74
59 variant = davinci_readl(JTAG_ID_BASE); 75 variant = __raw_readl(JTAG_ID_BASE);
60 76
61 variant = (variant >> 28) & 0xf; 77 variant = (variant >> 28) & 0xf;
62 78
63 return variant; 79 return variant;
64} 80}
65 81
82unsigned int davinci_rev(void)
83{
84 return davinci_revision >> 16;
85}
86EXPORT_SYMBOL(davinci_rev);
87
66void __init davinci_check_revision(void) 88void __init davinci_check_revision(void)
67{ 89{
68 int i; 90 int i;
@@ -75,7 +97,7 @@ void __init davinci_check_revision(void)
75 /* First check only the major version in a safe way */ 97 /* First check only the major version in a safe way */
76 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 98 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
77 if (part_no == (davinci_ids[i].part_no)) { 99 if (part_no == (davinci_ids[i].part_no)) {
78 system_rev = davinci_ids[i].type; 100 davinci_revision = davinci_ids[i].type;
79 break; 101 break;
80 } 102 }
81 } 103 }
@@ -84,10 +106,11 @@ void __init davinci_check_revision(void)
84 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { 106 for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
85 if (part_no == davinci_ids[i].part_no && 107 if (part_no == davinci_ids[i].part_no &&
86 variant == davinci_ids[i].variant) { 108 variant == davinci_ids[i].variant) {
87 system_rev = davinci_ids[i].type; 109 davinci_revision = davinci_ids[i].type;
88 break; 110 break;
89 } 111 }
90 } 112 }
91 113
92 printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); 114 printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n",
115 davinci_rev(), variant);
93} 116}
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
new file mode 100644
index 000000000000..3216f21c1238
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
@@ -0,0 +1,20 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index 38bdd49bc181..a3b040219876 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -17,6 +17,5 @@ struct clk;
17 17
18extern int clk_register(struct clk *clk); 18extern int clk_register(struct clk *clk);
19extern void clk_unregister(struct clk *clk); 19extern void clk_unregister(struct clk *clk);
20extern int davinci_clk_init(void);
21 20
22#endif 21#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4b522e5c70ec..191770976250 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,6 +16,12 @@ struct sys_timer;
16 16
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void);
21
22/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec);
24
19/* parameters describe VBUS sourcing for host mode */ 25/* parameters describe VBUS sourcing for host mode */
20extern void setup_usb(unsigned mA, unsigned potpgt_msec); 26extern void setup_usb(unsigned mA, unsigned potpgt_msec);
21 27
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
new file mode 100644
index 000000000000..27cfb1b3a662
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -0,0 +1,49 @@
1/*
2 * DaVinci CPU type detection
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * Defines the cpu_is_*() macros for runtime detection of DaVinci
7 * device type. In addtion, if support for a given device is not
8 * compiled in to the kernel, the macros return 0 so that
9 * resulting code can be optimized out.
10 *
11 * 2009 (c) Deep Root Systems, LLC. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16#ifndef _ASM_ARCH_CPU_H
17#define _ASM_ARCH_CPU_H
18
19extern unsigned int davinci_rev(void);
20
21#define IS_DAVINCI_CPU(type, id) \
22static inline int is_davinci_dm ##type(void) \
23{ \
24 return (davinci_rev() == (id)) ? 1 : 0; \
25}
26
27IS_DAVINCI_CPU(644x, 0x6446)
28IS_DAVINCI_CPU(646x, 0x6467)
29IS_DAVINCI_CPU(355, 0x355)
30
31#ifdef CONFIG_ARCH_DAVINCI_DM644x
32#define cpu_is_davinci_dm644x() is_davinci_dm644x()
33#else
34#define cpu_is_davinci_dm644x() 0
35#endif
36
37#ifdef CONFIG_ARCH_DAVINCI_DM646x
38#define cpu_is_davinci_dm646x() is_davinci_dm646x()
39#else
40#define cpu_is_davinci_dm646x() 0
41#endif
42
43#ifdef CONFIG_ARCH_DAVINCI_DM355
44#define cpu_is_davinci_dm355() is_davinci_dm355()
45#else
46#define cpu_is_davinci_dm355() 0
47#endif
48
49#endif
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 000000000000..3dcb9f4e58b4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,37 @@
1/*
2 * This file contains the processor specific definitions
3 * of the TI DM644x.
4 *
5 * Copyright (C) 2008 Texas Instruments.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H
24
25#include <linux/platform_device.h>
26#include <mach/hardware.h>
27
28#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
30#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
31#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
32#define DM644X_EMAC_MDIO_OFFSET (0x4000)
33#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
34
35void __init dm644x_init(void);
36
37#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
new file mode 100644
index 000000000000..f6fc5396dafc
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -0,0 +1,228 @@
1/*
2 * TI DAVINCI dma definitions
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28/*
29 * This EDMA3 programming framework exposes two basic kinds of resource:
30 *
31 * Channel Triggers transfers, usually from a hardware event but
32 * also manually or by "chaining" from DMA completions.
33 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
34 *
35 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
36 * "set"), source and destination addresses, a link to a
37 * next PaRAM slot (if any), options for the transfer, and
38 * instructions for updating those addresses. There are
39 * more than twice as many slots as event channels.
40 *
41 * Each PaRAM set describes a sequence of transfers, either for one large
42 * buffer or for several discontiguous smaller buffers. An EDMA transfer
43 * is driven only from a channel, which performs the transfers specified
44 * in its PaRAM slot until there are no more transfers. When that last
45 * transfer completes, the "link" field may be used to reload the channel's
46 * PaRAM slot with a new transfer descriptor.
47 *
48 * The EDMA Channel Controller (CC) maps requests from channels into physical
49 * Transfer Controller (TC) requests when the channel triggers (by hardware
50 * or software events, or by chaining). The two physical DMA channels provided
51 * by the TCs are thus shared by many logical channels.
52 *
53 * DaVinci hardware also has a "QDMA" mechanism which is not currently
54 * supported through this interface. (DSP firmware uses it though.)
55 */
56
57#ifndef EDMA_H_
58#define EDMA_H_
59
60/* PaRAM slots are laid out like this */
61struct edmacc_param {
62 unsigned int opt;
63 unsigned int src;
64 unsigned int a_b_cnt;
65 unsigned int dst;
66 unsigned int src_dst_bidx;
67 unsigned int link_bcntrld;
68 unsigned int src_dst_cidx;
69 unsigned int ccnt;
70};
71
72#define CCINT0_INTERRUPT 16
73#define CCERRINT_INTERRUPT 17
74#define TCERRINT0_INTERRUPT 18
75#define TCERRINT1_INTERRUPT 19
76
77/* fields in edmacc_param.opt */
78#define SAM BIT(0)
79#define DAM BIT(1)
80#define SYNCDIM BIT(2)
81#define STATIC BIT(3)
82#define EDMA_FWID (0x07 << 8)
83#define TCCMODE BIT(11)
84#define EDMA_TCC(t) ((t) << 12)
85#define TCINTEN BIT(20)
86#define ITCINTEN BIT(21)
87#define TCCHEN BIT(22)
88#define ITCCHEN BIT(23)
89
90#define TRWORD (0x7<<2)
91#define PAENTRY (0x1ff<<5)
92
93/* Drivers should avoid using these symbolic names for dm644x
94 * channels, and use platform_device IORESOURCE_DMA resources
95 * instead. (Other DaVinci chips have different peripherals
96 * and thus have different DMA channel mappings.)
97 */
98#define DAVINCI_DMA_MCBSP_TX 2
99#define DAVINCI_DMA_MCBSP_RX 3
100#define DAVINCI_DMA_VPSS_HIST 4
101#define DAVINCI_DMA_VPSS_H3A 5
102#define DAVINCI_DMA_VPSS_PRVU 6
103#define DAVINCI_DMA_VPSS_RSZ 7
104#define DAVINCI_DMA_IMCOP_IMXINT 8
105#define DAVINCI_DMA_IMCOP_VLCDINT 9
106#define DAVINCI_DMA_IMCO_PASQINT 10
107#define DAVINCI_DMA_IMCOP_DSQINT 11
108#define DAVINCI_DMA_SPI_SPIX 16
109#define DAVINCI_DMA_SPI_SPIR 17
110#define DAVINCI_DMA_UART0_URXEVT0 18
111#define DAVINCI_DMA_UART0_UTXEVT0 19
112#define DAVINCI_DMA_UART1_URXEVT1 20
113#define DAVINCI_DMA_UART1_UTXEVT1 21
114#define DAVINCI_DMA_UART2_URXEVT2 22
115#define DAVINCI_DMA_UART2_UTXEVT2 23
116#define DAVINCI_DMA_MEMSTK_MSEVT 24
117#define DAVINCI_DMA_MMCRXEVT 26
118#define DAVINCI_DMA_MMCTXEVT 27
119#define DAVINCI_DMA_I2C_ICREVT 28
120#define DAVINCI_DMA_I2C_ICXEVT 29
121#define DAVINCI_DMA_GPIO_GPINT0 32
122#define DAVINCI_DMA_GPIO_GPINT1 33
123#define DAVINCI_DMA_GPIO_GPINT2 34
124#define DAVINCI_DMA_GPIO_GPINT3 35
125#define DAVINCI_DMA_GPIO_GPINT4 36
126#define DAVINCI_DMA_GPIO_GPINT5 37
127#define DAVINCI_DMA_GPIO_GPINT6 38
128#define DAVINCI_DMA_GPIO_GPINT7 39
129#define DAVINCI_DMA_GPIO_GPBNKINT0 40
130#define DAVINCI_DMA_GPIO_GPBNKINT1 41
131#define DAVINCI_DMA_GPIO_GPBNKINT2 42
132#define DAVINCI_DMA_GPIO_GPBNKINT3 43
133#define DAVINCI_DMA_GPIO_GPBNKINT4 44
134#define DAVINCI_DMA_TIMER0_TINT0 48
135#define DAVINCI_DMA_TIMER1_TINT1 49
136#define DAVINCI_DMA_TIMER2_TINT2 50
137#define DAVINCI_DMA_TIMER3_TINT3 51
138#define DAVINCI_DMA_PWM0 52
139#define DAVINCI_DMA_PWM1 53
140#define DAVINCI_DMA_PWM2 54
141
142/*ch_status paramater of callback function possible values*/
143#define DMA_COMPLETE 1
144#define DMA_CC_ERROR 2
145#define DMA_TC1_ERROR 3
146#define DMA_TC2_ERROR 4
147
148enum address_mode {
149 INCR = 0,
150 FIFO = 1
151};
152
153enum fifo_width {
154 W8BIT = 0,
155 W16BIT = 1,
156 W32BIT = 2,
157 W64BIT = 3,
158 W128BIT = 4,
159 W256BIT = 5
160};
161
162enum dma_event_q {
163 EVENTQ_0 = 0,
164 EVENTQ_1 = 1,
165 EVENTQ_DEFAULT = -1
166};
167
168enum sync_dimension {
169 ASYNC = 0,
170 ABSYNC = 1
171};
172
173#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
174#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
175
176/* alloc/free DMA channels and their dedicated parameter RAM slots */
177int edma_alloc_channel(int channel,
178 void (*callback)(unsigned channel, u16 ch_status, void *data),
179 void *data, enum dma_event_q);
180void edma_free_channel(unsigned channel);
181
182/* alloc/free parameter RAM slots */
183int edma_alloc_slot(int slot);
184void edma_free_slot(unsigned slot);
185
186/* calls that operate on part of a parameter RAM slot */
187void edma_set_src(unsigned slot, dma_addr_t src_port,
188 enum address_mode mode, enum fifo_width);
189void edma_set_dest(unsigned slot, dma_addr_t dest_port,
190 enum address_mode mode, enum fifo_width);
191void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
192void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
193void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
194void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
195 u16 bcnt_rld, enum sync_dimension sync_mode);
196void edma_link(unsigned from, unsigned to);
197void edma_unlink(unsigned from);
198
199/* calls that operate on an entire parameter RAM slot */
200void edma_write_slot(unsigned slot, const struct edmacc_param *params);
201void edma_read_slot(unsigned slot, struct edmacc_param *params);
202
203/* channel control operations */
204int edma_start(unsigned channel);
205void edma_stop(unsigned channel);
206void edma_clean_channel(unsigned channel);
207void edma_clear_event(unsigned channel);
208void edma_pause(unsigned channel);
209void edma_resume(unsigned channel);
210
211/* UNRELATED TO DMA */
212int davinci_alloc_iram(unsigned size);
213void davinci_free_iram(unsigned addr, unsigned size);
214
215/* platform_data for EDMA driver */
216struct edma_soc_info {
217
218 /* how many dma resources of each type */
219 unsigned n_channel;
220 unsigned n_region;
221 unsigned n_slot;
222 unsigned n_tc;
223
224 /* list of channels with no even trigger; terminated by "-1" */
225 const s8 *noevent;
226};
227
228#endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index b456f079f43f..efe3281364e6 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -15,9 +15,11 @@
15 15
16#include <linux/io.h> 16#include <linux/io.h>
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18#include <mach/hardware.h> 18
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20 20
21#define DAVINCI_GPIO_BASE 0x01C67000
22
21/* 23/*
22 * basic gpio routines 24 * basic gpio routines
23 * 25 *
@@ -26,23 +28,18 @@
26 * go through boot loaders. 28 * go through boot loaders.
27 * 29 *
28 * the gpio clock will be turned on when gpios are used, and you may also 30 * the gpio clock will be turned on when gpios are used, and you may also
29 * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are 31 * need to pay attention to PINMUX registers to be sure those pins are
30 * used as gpios, not with other peripherals. 32 * used as gpios, not with other peripherals.
31 * 33 *
32 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, 34 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
33 * and maybe for later updates, code should write GPIO(N) or: 35 * and maybe for later updates, code may write GPIO(N). These may be
34 * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) 36 * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
35 * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) 37 * may not support all the GPIOs in that range.
36 *
37 * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
38 * for now, that's != GPIO(N)
39 * 38 *
40 * GPIOs can also be on external chips, numbered after the ones built-in 39 * GPIOs can also be on external chips, numbered after the ones built-in
41 * to the DaVinci chip. For now, they won't be usable as IRQ sources. 40 * to the DaVinci chip. For now, they won't be usable as IRQ sources.
42 */ 41 */
43#define GPIO(X) (X) /* 0 <= X <= 70 */ 42#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
44#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
45#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
46 43
47struct gpio_controller { 44struct gpio_controller {
48 u32 dir; 45 u32 dir;
@@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio)
71{ 68{
72 void *__iomem ptr; 69 void *__iomem ptr;
73 70
74 if (gpio < 32) 71 if (gpio < 32 * 1)
75 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); 72 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
76 else if (gpio < 64) 73 else if (gpio < 32 * 2)
77 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); 74 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
78 else if (gpio < DAVINCI_N_GPIO) 75 else if (gpio < 32 * 3)
79 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); 76 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
77 else if (gpio < 32 * 4)
78 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
80 else 79 else
81 ptr = NULL; 80 ptr = NULL;
82 return ptr; 81 return ptr;
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a2e8969afaca..48c77934d519 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common hardware definitions 2 * Hardware definitions common to all DaVinci family processors
3 * 3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 * 5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
@@ -12,41 +12,16 @@
12#define __ASM_ARCH_HARDWARE_H 12#define __ASM_ARCH_HARDWARE_H
13 13
14/* 14/*
15 * Base register addresses 15 * Before you add anything to ths file:
16 *
17 * This header is for defines common to ALL DaVinci family chips.
18 * Anything that is chip specific should go in <chipname>.h,
19 * and the chip/board init code should then explicitly include
20 * <chipname>.h
16 */ 21 */
17#define DAVINCI_DMA_3PCC_BASE (0x01C00000) 22#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
18#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) 23
19#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) 24/* System control register offsets */
20#define DAVINCI_I2C_BASE (0x01C21000) 25#define DM64XX_VDD3P3V_PWDN 0x48
21#define DAVINCI_PWM0_BASE (0x01C22000)
22#define DAVINCI_PWM1_BASE (0x01C22400)
23#define DAVINCI_PWM2_BASE (0x01C22800)
24#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
25#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
26#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
27#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
28#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
29#define DAVINCI_IEEE1394_BASE (0x01C60000)
30#define DAVINCI_USB_OTG_BASE (0x01C64000)
31#define DAVINCI_CFC_ATA_BASE (0x01C66000)
32#define DAVINCI_SPI_BASE (0x01C66800)
33#define DAVINCI_GPIO_BASE (0x01C67000)
34#define DAVINCI_UHPI_BASE (0x01C67800)
35#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
36#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
37#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
38#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
39#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
40#define DAVINCI_IMCOP_BASE (0x01CC0000)
41#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
42#define DAVINCI_VLYNQ_BASE (0x01E01000)
43#define DAVINCI_MCBSP_BASE (0x01E02000)
44#define DAVINCI_MMC_SD_BASE (0x01E10000)
45#define DAVINCI_MS_BASE (0x01E20000)
46#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
47#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
48#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
49#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
50#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
51 26
52#endif /* __ASM_ARCH_HARDWARE_H */ 27#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index a48795fd2417..2479785405af 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -40,22 +40,12 @@
40#else 40#else
41#define IOMEM(x) ((void __force __iomem *)(x)) 41#define IOMEM(x) ((void __force __iomem *)(x))
42 42
43/* 43#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
44 * Functions to access the DaVinci IO region 44#define __arch_iounmap(v) davinci_iounmap(v)
45 *
46 * NOTE: - Use davinci_read/write[bwl] for physical register addresses
47 * - Use __raw_read/write[bwl]() for virtual register addresses
48 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
49 * - DO NOT use hardcoded virtual addresses to allow changing the
50 * IO address space again if needed
51 */
52#define davinci_readb(a) __raw_readb(IO_ADDRESS(a))
53#define davinci_readw(a) __raw_readw(IO_ADDRESS(a))
54#define davinci_readl(a) __raw_readl(IO_ADDRESS(a))
55 45
56#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a)) 46void __iomem *davinci_ioremap(unsigned long phys, size_t size,
57#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a)) 47 unsigned int type);
58#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a)) 48void davinci_iounmap(volatile void __iomem *addr);
59 49
60#endif /* __ASSEMBLER__ */ 50#endif /* __ASSEMBLER__ */
61#endif /* __ASM_ARCH_IO_H */ 51#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..18066074c995 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -96,10 +96,111 @@
96#define IRQ_EMUINT 63 96#define IRQ_EMUINT 63
97 97
98#define DAVINCI_N_AINTC_IRQ 64 98#define DAVINCI_N_AINTC_IRQ 64
99#define DAVINCI_N_GPIO 71 99#define DAVINCI_N_GPIO 104
100 100
101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) 101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
102 102
103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
104 104
105/* DaVinci DM6467-specific Interrupts */
106#define IRQ_DM646X_VP_VERTINT0 0
107#define IRQ_DM646X_VP_VERTINT1 1
108#define IRQ_DM646X_VP_VERTINT2 2
109#define IRQ_DM646X_VP_VERTINT3 3
110#define IRQ_DM646X_VP_ERRINT 4
111#define IRQ_DM646X_RESERVED_1 5
112#define IRQ_DM646X_RESERVED_2 6
113#define IRQ_DM646X_WDINT 7
114#define IRQ_DM646X_CRGENINT0 8
115#define IRQ_DM646X_CRGENINT1 9
116#define IRQ_DM646X_TSIFINT0 10
117#define IRQ_DM646X_TSIFINT1 11
118#define IRQ_DM646X_VDCEINT 12
119#define IRQ_DM646X_USBINT 13
120#define IRQ_DM646X_USBDMAINT 14
121#define IRQ_DM646X_PCIINT 15
122#define IRQ_DM646X_TCERRINT2 20
123#define IRQ_DM646X_TCERRINT3 21
124#define IRQ_DM646X_IDE 22
125#define IRQ_DM646X_HPIINT 23
126#define IRQ_DM646X_EMACRXTHINT 24
127#define IRQ_DM646X_EMACRXINT 25
128#define IRQ_DM646X_EMACTXINT 26
129#define IRQ_DM646X_EMACMISCINT 27
130#define IRQ_DM646X_MCASP0TXINT 28
131#define IRQ_DM646X_MCASP0RXINT 29
132#define IRQ_DM646X_RESERVED_3 31
133#define IRQ_DM646X_MCASP1TXINT 32
134#define IRQ_DM646X_VLQINT 38
135#define IRQ_DM646X_UARTINT2 42
136#define IRQ_DM646X_SPINT0 43
137#define IRQ_DM646X_SPINT1 44
138#define IRQ_DM646X_DSP2ARMINT 45
139#define IRQ_DM646X_RESERVED_4 46
140#define IRQ_DM646X_PSCINT 47
141#define IRQ_DM646X_GPIO0 48
142#define IRQ_DM646X_GPIO1 49
143#define IRQ_DM646X_GPIO2 50
144#define IRQ_DM646X_GPIO3 51
145#define IRQ_DM646X_GPIO4 52
146#define IRQ_DM646X_GPIO5 53
147#define IRQ_DM646X_GPIO6 54
148#define IRQ_DM646X_GPIO7 55
149#define IRQ_DM646X_GPIOBNK0 56
150#define IRQ_DM646X_GPIOBNK1 57
151#define IRQ_DM646X_GPIOBNK2 58
152#define IRQ_DM646X_DDRINT 59
153#define IRQ_DM646X_AEMIFINT 60
154
155/* DaVinci DM355-specific Interrupts */
156#define IRQ_DM355_CCDC_VDINT0 0
157#define IRQ_DM355_CCDC_VDINT1 1
158#define IRQ_DM355_CCDC_VDINT2 2
159#define IRQ_DM355_IPIPE_HST 3
160#define IRQ_DM355_H3AINT 4
161#define IRQ_DM355_IPIPE_SDR 5
162#define IRQ_DM355_IPIPEIFINT 6
163#define IRQ_DM355_OSDINT 7
164#define IRQ_DM355_VENCINT 8
165#define IRQ_DM355_IMCOPINT 11
166#define IRQ_DM355_RTOINT 13
167#define IRQ_DM355_TINT4 13
168#define IRQ_DM355_TINT2_TINT12 13
169#define IRQ_DM355_UARTINT2 14
170#define IRQ_DM355_TINT5 14
171#define IRQ_DM355_TINT2_TINT34 14
172#define IRQ_DM355_TINT6 15
173#define IRQ_DM355_TINT3_TINT12 15
174#define IRQ_DM355_SPINT1_0 17
175#define IRQ_DM355_SPINT1_1 18
176#define IRQ_DM355_SPINT2_0 19
177#define IRQ_DM355_SPINT2_1 21
178#define IRQ_DM355_TINT7 22
179#define IRQ_DM355_TINT3_TINT34 22
180#define IRQ_DM355_SDIOINT0 23
181#define IRQ_DM355_MMCINT0 26
182#define IRQ_DM355_MSINT 26
183#define IRQ_DM355_MMCINT1 27
184#define IRQ_DM355_PWMINT3 28
185#define IRQ_DM355_SDIOINT1 31
186#define IRQ_DM355_SPINT0_0 42
187#define IRQ_DM355_SPINT0_1 43
188#define IRQ_DM355_GPIO0 44
189#define IRQ_DM355_GPIO1 45
190#define IRQ_DM355_GPIO2 46
191#define IRQ_DM355_GPIO3 47
192#define IRQ_DM355_GPIO4 48
193#define IRQ_DM355_GPIO5 49
194#define IRQ_DM355_GPIO6 50
195#define IRQ_DM355_GPIO7 51
196#define IRQ_DM355_GPIO8 52
197#define IRQ_DM355_GPIO9 53
198#define IRQ_DM355_GPIOBNK0 54
199#define IRQ_DM355_GPIOBNK1 55
200#define IRQ_DM355_GPIOBNK2 56
201#define IRQ_DM355_GPIOBNK3 57
202#define IRQ_DM355_GPIOBNK4 58
203#define IRQ_DM355_GPIOBNK5 59
204#define IRQ_DM355_GPIOBNK6 60
205
105#endif /* __ASM_ARCH_IRQS_H */ 206#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804d..bae22cb3e27b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1,55 +1,183 @@
1/* 1/*
2 * DaVinci pin multiplexing defines 2 * Table of the DAVINCI register configurations for the PINMUX combinations
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#ifndef __ASM_ARCH_MUX_H 18
12#define __ASM_ARCH_MUX_H 19#ifndef __INC_MACH_MUX_H
13 20#define __INC_MACH_MUX_H
14#define DAVINCI_MUX_AEAW0 0 21
15#define DAVINCI_MUX_AEAW1 1 22/* System module registers */
16#define DAVINCI_MUX_AEAW2 2 23#define PINMUX0 0x00
17#define DAVINCI_MUX_AEAW3 3 24#define PINMUX1 0x04
18#define DAVINCI_MUX_AEAW4 4 25/* dm355 only */
19#define DAVINCI_MUX_AECS4 10 26#define PINMUX2 0x08
20#define DAVINCI_MUX_AECS5 11 27#define PINMUX3 0x0c
21#define DAVINCI_MUX_VLYNQWD0 12 28#define PINMUX4 0x10
22#define DAVINCI_MUX_VLYNQWD1 13 29#define INTMUX 0x18
23#define DAVINCI_MUX_VLSCREN 14 30#define EVTMUX 0x1c
24#define DAVINCI_MUX_VLYNQEN 15 31
25#define DAVINCI_MUX_HDIREN 16 32struct mux_config {
26#define DAVINCI_MUX_ATAEN 17 33 const char *name;
27#define DAVINCI_MUX_RGB666 22 34 const char *mux_reg_name;
28#define DAVINCI_MUX_RGB888 23 35 const unsigned char mux_reg;
29#define DAVINCI_MUX_LOEEN 24 36 const unsigned char mask_offset;
30#define DAVINCI_MUX_LFLDEN 25 37 const unsigned char mask;
31#define DAVINCI_MUX_CWEN 26 38 const unsigned char mode;
32#define DAVINCI_MUX_CFLDEN 27 39 bool debug;
33#define DAVINCI_MUX_HPIEN 29 40};
34#define DAVINCI_MUX_1394EN 30 41
35#define DAVINCI_MUX_EMACEN 31 42enum davinci_dm644x_index {
36 43 /* ATA and HDDIR functions */
37#define DAVINCI_MUX_LEVEL2 32 44 DM644X_HDIREN,
38#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) 45 DM644X_ATAEN,
39#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) 46 DM644X_ATAEN_DISABLE,
40#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) 47
41#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) 48 /* HPI functions */
42#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) 49 DM644X_HPIEN_DISABLE,
43#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) 50
44#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) 51 /* AEAW functions */
45#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) 52 DM644X_AEAW,
46#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) 53
47#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) 54 /* Memory Stick */
48#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) 55 DM644X_MSTK,
49#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) 56
50#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) 57 /* I2C */
51#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) 58 DM644X_I2C,
52 59
53extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); 60 /* ASP function */
54 61 DM644X_MCBSP,
55#endif /* __ASM_ARCH_MUX_H */ 62
63 /* UART1 */
64 DM644X_UART1,
65
66 /* UART2 */
67 DM644X_UART2,
68
69 /* PWM0 */
70 DM644X_PWM0,
71
72 /* PWM1 */
73 DM644X_PWM1,
74
75 /* PWM2 */
76 DM644X_PWM2,
77
78 /* VLYNQ function */
79 DM644X_VLYNQEN,
80 DM644X_VLSCREN,
81 DM644X_VLYNQWD,
82
83 /* EMAC and MDIO function */
84 DM644X_EMACEN,
85
86 /* GPIO3V[0:16] pins */
87 DM644X_GPIO3V,
88
89 /* GPIO pins */
90 DM644X_GPIO0,
91 DM644X_GPIO3,
92 DM644X_GPIO43_44,
93 DM644X_GPIO46_47,
94
95 /* VPBE */
96 DM644X_RGB666,
97
98 /* LCD */
99 DM644X_LOEEN,
100 DM644X_LFLDEN,
101};
102
103enum davinci_dm646x_index {
104 /* ATA function */
105 DM646X_ATAEN,
106
107 /* AUDIO Clock */
108 DM646X_AUDCK1,
109 DM646X_AUDCK0,
110
111 /* CRGEN Control */
112 DM646X_CRGMUX,
113
114 /* VPIF Control */
115 DM646X_STSOMUX_DISABLE,
116 DM646X_STSIMUX_DISABLE,
117 DM646X_PTSOMUX_DISABLE,
118 DM646X_PTSIMUX_DISABLE,
119
120 /* TSIF Control */
121 DM646X_STSOMUX,
122 DM646X_STSIMUX,
123 DM646X_PTSOMUX_PARALLEL,
124 DM646X_PTSIMUX_PARALLEL,
125 DM646X_PTSOMUX_SERIAL,
126 DM646X_PTSIMUX_SERIAL,
127};
128
129enum davinci_dm355_index {
130 /* MMC/SD 0 */
131 DM355_MMCSD0,
132
133 /* MMC/SD 1 */
134 DM355_SD1_CLK,
135 DM355_SD1_CMD,
136 DM355_SD1_DATA3,
137 DM355_SD1_DATA2,
138 DM355_SD1_DATA1,
139 DM355_SD1_DATA0,
140
141 /* I2C */
142 DM355_I2C_SDA,
143 DM355_I2C_SCL,
144
145 /* ASP0 function */
146 DM355_MCBSP0_BDX,
147 DM355_MCBSP0_X,
148 DM355_MCBSP0_BFSX,
149 DM355_MCBSP0_BDR,
150 DM355_MCBSP0_R,
151 DM355_MCBSP0_BFSR,
152
153 /* SPI0 */
154 DM355_SPI0_SDI,
155 DM355_SPI0_SDENA0,
156 DM355_SPI0_SDENA1,
157
158 /* IRQ muxing */
159 DM355_INT_EDMA_CC,
160 DM355_INT_EDMA_TC0_ERR,
161 DM355_INT_EDMA_TC1_ERR,
162
163 /* EDMA event muxing */
164 DM355_EVT8_ASP1_TX,
165 DM355_EVT9_ASP1_RX,
166 DM355_EVT26_MMC0_RX,
167};
168
169#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif
182
183#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..55a90d419fac 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -38,8 +38,6 @@
38#define DAVINCI_LPSC_TPTC1 4 38#define DAVINCI_LPSC_TPTC1 4
39#define DAVINCI_LPSC_EMAC 5 39#define DAVINCI_LPSC_EMAC 5
40#define DAVINCI_LPSC_EMAC_WRAPPER 6 40#define DAVINCI_LPSC_EMAC_WRAPPER 6
41#define DAVINCI_LPSC_MDIO 7
42#define DAVINCI_LPSC_IEEE1394 8
43#define DAVINCI_LPSC_USB 9 41#define DAVINCI_LPSC_USB 9
44#define DAVINCI_LPSC_ATA 10 42#define DAVINCI_LPSC_ATA 10
45#define DAVINCI_LPSC_VLYNQ 11 43#define DAVINCI_LPSC_VLYNQ 11
@@ -47,7 +45,6 @@
47#define DAVINCI_LPSC_DDR_EMIF 13 45#define DAVINCI_LPSC_DDR_EMIF 13
48#define DAVINCI_LPSC_AEMIF 14 46#define DAVINCI_LPSC_AEMIF 14
49#define DAVINCI_LPSC_MMC_SD 15 47#define DAVINCI_LPSC_MMC_SD 15
50#define DAVINCI_LPSC_MEMSTICK 16
51#define DAVINCI_LPSC_McBSP 17 48#define DAVINCI_LPSC_McBSP 17
52#define DAVINCI_LPSC_I2C 18 49#define DAVINCI_LPSC_I2C 18
53#define DAVINCI_LPSC_UART0 19 50#define DAVINCI_LPSC_UART0 19
@@ -73,4 +70,54 @@
73#define DAVINCI_LPSC_GEM 39 70#define DAVINCI_LPSC_GEM 39
74#define DAVINCI_LPSC_IMCOP 40 71#define DAVINCI_LPSC_IMCOP 40
75 72
73#define DM355_LPSC_TIMER3 5
74#define DM355_LPSC_SPI1 6
75#define DM355_LPSC_MMC_SD1 7
76#define DM355_LPSC_McBSP1 8
77#define DM355_LPSC_PWM3 10
78#define DM355_LPSC_SPI2 11
79#define DM355_LPSC_RTO 12
80#define DM355_LPSC_VPSS_DAC 41
81
82/*
83 * LPSC Assignments
84 */
85#define DM646X_LPSC_ARM 0
86#define DM646X_LPSC_C64X_CPU 1
87#define DM646X_LPSC_HDVICP0 2
88#define DM646X_LPSC_HDVICP1 3
89#define DM646X_LPSC_TPCC 4
90#define DM646X_LPSC_TPTC0 5
91#define DM646X_LPSC_TPTC1 6
92#define DM646X_LPSC_TPTC2 7
93#define DM646X_LPSC_TPTC3 8
94#define DM646X_LPSC_PCI 13
95#define DM646X_LPSC_EMAC 14
96#define DM646X_LPSC_VDCE 15
97#define DM646X_LPSC_VPSSMSTR 16
98#define DM646X_LPSC_VPSSSLV 17
99#define DM646X_LPSC_TSIF0 18
100#define DM646X_LPSC_TSIF1 19
101#define DM646X_LPSC_DDR_EMIF 20
102#define DM646X_LPSC_AEMIF 21
103#define DM646X_LPSC_McASP0 22
104#define DM646X_LPSC_McASP1 23
105#define DM646X_LPSC_CRGEN0 24
106#define DM646X_LPSC_CRGEN1 25
107#define DM646X_LPSC_UART0 26
108#define DM646X_LPSC_UART1 27
109#define DM646X_LPSC_UART2 28
110#define DM646X_LPSC_PWM0 29
111#define DM646X_LPSC_PWM1 30
112#define DM646X_LPSC_I2C 31
113#define DM646X_LPSC_SPI 32
114#define DM646X_LPSC_GPIO 33
115#define DM646X_LPSC_TIMER0 34
116#define DM646X_LPSC_TIMER1 35
117#define DM646X_LPSC_ARM_INTC 45
118
119extern int davinci_psc_is_clk_active(unsigned int id);
120extern void davinci_psc_config(unsigned int domain, unsigned int id,
121 char enable);
122
76#endif /* __ASM_ARCH_PSC_H */ 123#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index fb8cb229bfd2..632847d74a1c 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,8 +13,23 @@
13 13
14#include <mach/io.h> 14#include <mach/io.h>
15 15
16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22
23/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c
25#define UART_DM646X_SCR 0x10
26#define UART_DM646X_SCR_TX_WATERMARK 0x08
27
28struct davinci_uart_config {
29 /* Bit field of UARTs present; bit 0 --> UART1 */
30 unsigned int enabled_uarts;
31};
32
33extern void davinci_serial_init(struct davinci_uart_config *);
19 34
20#endif /* __ASM_ARCH_SERIAL_H */ 35#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 299515f70b8b..a548abb513e2 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -51,7 +51,26 @@ void __init davinci_map_common_io(void)
51 davinci_check_revision(); 51 davinci_check_revision();
52} 52}
53 53
54void __init davinci_init_common_hw(void) 54#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
55#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
56
57/*
58 * Intercept ioremap() requests for addresses in our fixed mapping regions.
59 */
60void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
61{
62 if (BETWEEN(p, IO_PHYS, IO_SIZE))
63 return XLATE(p, IO_PHYS, IO_VIRT);
64
65 return __arm_ioremap(p, size, type);
66}
67EXPORT_SYMBOL(davinci_ioremap);
68
69void davinci_iounmap(volatile void __iomem *addr)
55{ 70{
56 davinci_clk_init(); 71 unsigned long virt = (unsigned long)addr;
72
73 if (virt >= VMALLOC_START && virt < VMALLOC_END)
74 __iounmap(addr);
57} 75}
76EXPORT_SYMBOL(davinci_iounmap);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 38021af8359a..5a324c90e291 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h>
28#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
29 30
30#define IRQ_BIT(irq) ((irq) & 0x1f) 31#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -40,14 +41,18 @@
40#define IRQ_INTPRI0_REG_OFFSET 0x0030 41#define IRQ_INTPRI0_REG_OFFSET 0x0030
41#define IRQ_INTPRI7_REG_OFFSET 0x004C 42#define IRQ_INTPRI7_REG_OFFSET 0x004C
42 43
44const u8 *davinci_def_priorities;
45
46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
47
43static inline unsigned int davinci_irq_readl(int offset) 48static inline unsigned int davinci_irq_readl(int offset)
44{ 49{
45 return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); 50 return __raw_readl(INTC_BASE + offset);
46} 51}
47 52
48static inline void davinci_irq_writel(unsigned long value, int offset) 53static inline void davinci_irq_writel(unsigned long value, int offset)
49{ 54{
50 davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); 55 __raw_writel(value, INTC_BASE + offset);
51} 56}
52 57
53/* Disable interrupt */ 58/* Disable interrupt */
@@ -108,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = {
108 .unmask = davinci_unmask_irq, 113 .unmask = davinci_unmask_irq,
109}; 114};
110 115
111
112/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
113static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { 117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
114 [IRQ_VDINT0] = 2, 118 [IRQ_VDINT0] = 2,
115 [IRQ_VDINT1] = 6, 119 [IRQ_VDINT1] = 6,
116 [IRQ_VDINT2] = 6, 120 [IRQ_VDINT2] = 6,
@@ -177,11 +181,149 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
177 [IRQ_EMUINT] = 7, 181 [IRQ_EMUINT] = 7,
178}; 182};
179 183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
251static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
252 [IRQ_DM355_CCDC_VDINT0] = 2,
253 [IRQ_DM355_CCDC_VDINT1] = 6,
254 [IRQ_DM355_CCDC_VDINT2] = 6,
255 [IRQ_DM355_IPIPE_HST] = 6,
256 [IRQ_DM355_H3AINT] = 6,
257 [IRQ_DM355_IPIPE_SDR] = 6,
258 [IRQ_DM355_IPIPEIFINT] = 6,
259 [IRQ_DM355_OSDINT] = 7,
260 [IRQ_DM355_VENCINT] = 6,
261 [IRQ_ASQINT] = 6,
262 [IRQ_IMXINT] = 6,
263 [IRQ_USBINT] = 4,
264 [IRQ_DM355_RTOINT] = 4,
265 [IRQ_DM355_UARTINT2] = 7,
266 [IRQ_DM355_TINT6] = 7,
267 [IRQ_CCINT0] = 5, /* dma */
268 [IRQ_CCERRINT] = 5, /* dma */
269 [IRQ_TCERRINT0] = 5, /* dma */
270 [IRQ_TCERRINT] = 5, /* dma */
271 [IRQ_DM355_SPINT2_1] = 7,
272 [IRQ_DM355_TINT7] = 4,
273 [IRQ_DM355_SDIOINT0] = 7,
274 [IRQ_MBXINT] = 7,
275 [IRQ_MBRINT] = 7,
276 [IRQ_MMCINT] = 7,
277 [IRQ_DM355_MMCINT1] = 7,
278 [IRQ_DM355_PWMINT3] = 7,
279 [IRQ_DDRINT] = 7,
280 [IRQ_AEMIFINT] = 7,
281 [IRQ_DM355_SDIOINT1] = 4,
282 [IRQ_TINT0_TINT12] = 2, /* clockevent */
283 [IRQ_TINT0_TINT34] = 2, /* clocksource */
284 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
285 [IRQ_TINT1_TINT34] = 7, /* system tick */
286 [IRQ_PWMINT0] = 7,
287 [IRQ_PWMINT1] = 7,
288 [IRQ_PWMINT2] = 7,
289 [IRQ_I2C] = 3,
290 [IRQ_UARTINT0] = 3,
291 [IRQ_UARTINT1] = 3,
292 [IRQ_DM355_SPINT0_0] = 3,
293 [IRQ_DM355_SPINT0_1] = 3,
294 [IRQ_DM355_GPIO0] = 3,
295 [IRQ_DM355_GPIO1] = 7,
296 [IRQ_DM355_GPIO2] = 4,
297 [IRQ_DM355_GPIO3] = 4,
298 [IRQ_DM355_GPIO4] = 7,
299 [IRQ_DM355_GPIO5] = 7,
300 [IRQ_DM355_GPIO6] = 7,
301 [IRQ_DM355_GPIO7] = 7,
302 [IRQ_DM355_GPIO8] = 7,
303 [IRQ_DM355_GPIO9] = 7,
304 [IRQ_DM355_GPIOBNK0] = 7,
305 [IRQ_DM355_GPIOBNK1] = 7,
306 [IRQ_DM355_GPIOBNK2] = 7,
307 [IRQ_DM355_GPIOBNK3] = 7,
308 [IRQ_DM355_GPIOBNK4] = 7,
309 [IRQ_DM355_GPIOBNK5] = 7,
310 [IRQ_DM355_GPIOBNK6] = 7,
311 [IRQ_COMMTX] = 7,
312 [IRQ_COMMRX] = 7,
313 [IRQ_EMUINT] = 7,
314};
315
180/* ARM Interrupt Controller Initialization */ 316/* ARM Interrupt Controller Initialization */
181void __init davinci_irq_init(void) 317void __init davinci_irq_init(void)
182{ 318{
183 unsigned i; 319 unsigned i;
184 const u8 *priority = default_priorities; 320
321 if (cpu_is_davinci_dm644x())
322 davinci_def_priorities = dm644x_default_priorities;
323 else if (cpu_is_davinci_dm646x())
324 davinci_def_priorities = dm646x_default_priorities;
325 else if (cpu_is_davinci_dm355())
326 davinci_def_priorities = dm355_default_priorities;
185 327
186 /* Clear all interrupt requests */ 328 /* Clear all interrupt requests */
187 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 329 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -209,8 +351,8 @@ void __init davinci_irq_init(void)
209 unsigned j; 351 unsigned j;
210 u32 pri; 352 u32 pri;
211 353
212 for (j = 0, pri = 0; j < 32; j += 4, priority++) 354 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
213 pri |= (*priority & 0x07) << j; 355 pri |= (*davinci_def_priorities & 0x07) << j;
214 davinci_irq_writel(pri, i); 356 davinci_irq_writel(pri, i);
215 } 357 }
216 358
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 8ff9d8aca60b..bbba0b247a44 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,41 +1,103 @@
1/* 1/*
2 * DaVinci pin multiplexing configurations 2 * Utility to set the DAVINCI MUX register from a table in mux.h
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/arch/arm/plat-omap/mux.c:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/module.h>
12#include <linux/spinlock.h> 20#include <linux/spinlock.h>
13 21
14#include <mach/hardware.h> 22#include <mach/hardware.h>
15
16#include <mach/mux.h> 23#include <mach/mux.h>
17 24
18/* System control register offsets */ 25static const struct mux_config *mux_table;
19#define PINMUX0 0x00 26static unsigned long pin_table_sz;
20#define PINMUX1 0x04 27
28int __init davinci_mux_register(const struct mux_config *pins,
29 unsigned long size)
30{
31 mux_table = pins;
32 pin_table_sz = size;
21 33
22static DEFINE_SPINLOCK(mux_lock); 34 return 0;
35}
23 36
24void davinci_mux_peripheral(unsigned int mux, unsigned int enable) 37/*
38 * Sets the DAVINCI MUX register based on the table
39 */
40int __init_or_module davinci_cfg_reg(const unsigned long index)
25{ 41{
26 u32 pinmux, muxreg = PINMUX0; 42 static DEFINE_SPINLOCK(mux_spin_lock);
43 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
44 unsigned long flags;
45 const struct mux_config *cfg;
46 unsigned int reg_orig = 0, reg = 0;
47 unsigned int mask, warn = 0;
48
49 if (!mux_table)
50 BUG();
51
52 if (index >= pin_table_sz) {
53 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
54 index, pin_table_sz);
55 dump_stack();
56 return -ENODEV;
57 }
58
59 cfg = &mux_table[index];
60
61 if (cfg->name == NULL) {
62 printk(KERN_ERR "No entry for the specified index\n");
63 return -ENODEV;
64 }
65
66 /* Update the mux register in question */
67 if (cfg->mask) {
68 unsigned tmp1, tmp2;
69
70 spin_lock_irqsave(&mux_spin_lock, flags);
71 reg_orig = __raw_readl(base + cfg->mux_reg);
72
73 mask = (cfg->mask << cfg->mask_offset);
74 tmp1 = reg_orig & mask;
75 reg = reg_orig & ~mask;
76
77 tmp2 = (cfg->mode << cfg->mask_offset);
78 reg |= tmp2;
79
80 if (tmp1 != tmp2)
81 warn = 1;
82
83 __raw_writel(reg, base + cfg->mux_reg);
84 spin_unlock_irqrestore(&mux_spin_lock, flags);
85 }
86
87 if (warn) {
88#ifdef CONFIG_DAVINCI_MUX_WARNINGS
89 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
90#endif
91 }
27 92
28 if (mux >= DAVINCI_MUX_LEVEL2) { 93#ifdef CONFIG_DAVINCI_MUX_DEBUG
29 muxreg = PINMUX1; 94 if (cfg->debug || warn) {
30 mux -= DAVINCI_MUX_LEVEL2; 95 printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
96 printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
97 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
31 } 98 }
99#endif
32 100
33 spin_lock(&mux_lock); 101 return 0;
34 pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
35 if (enable)
36 pinmux |= (1 << mux);
37 else
38 pinmux &= ~(1 << mux);
39 davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
40 spin_unlock(&mux_lock);
41} 102}
103EXPORT_SYMBOL(davinci_cfg_reg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
new file mode 100644
index 000000000000..adc869413371
--- /dev/null
+++ b/arch/arm/mach-davinci/mux.h
@@ -0,0 +1,51 @@
1/*
2 * Pin-multiplex helper macros for TI DaVinci family devices
3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright (C) 2008 Texas Instruments.
12 */
13#ifndef _MACH_DAVINCI_MUX_H_
14#define _MACH_DAVINCI_MUX_H_
15
16#include <mach/mux.h>
17
18#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
19[soc##_##desc] = { \
20 .name = #desc, \
21 .debug = dbg, \
22 .mux_reg_name = "PINMUX"#muxreg, \
23 .mux_reg = PINMUX##muxreg, \
24 .mask_offset = mode_offset, \
25 .mask = mode_mask, \
26 .mode = mux_mode, \
27 },
28
29#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
30[soc##_##desc] = { \
31 .name = #desc, \
32 .debug = dbg, \
33 .mux_reg_name = "INTMUX", \
34 .mux_reg = INTMUX, \
35 .mask_offset = mode_offset, \
36 .mask = mode_mask, \
37 .mode = mux_mode, \
38 },
39
40#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
41[soc##_##desc] = { \
42 .name = #desc, \
43 .debug = dbg, \
44 .mux_reg_name = "EVTMUX", \
45 .mux_reg = EVTMUX, \
46 .mask_offset = mode_offset, \
47 .mask = mode_mask, \
48 .mode = mux_mode, \
49 },
50
51#endif /* _MACH_DAVINCI_MUX_H */
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 58754f066d5b..84171abf5f7b 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,10 +23,13 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25 25
26#include <mach/cputype.h>
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/psc.h> 28#include <mach/psc.h>
28#include <mach/mux.h> 29#include <mach/mux.h>
29 30
31#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
32
30/* PSC register offsets */ 33/* PSC register offsets */
31#define EPCPR 0x070 34#define EPCPR 0x070
32#define PTCMD 0x120 35#define PTCMD 0x120
@@ -36,102 +39,61 @@
36#define MDSTAT 0x800 39#define MDSTAT 0x800
37#define MDCTL 0xA00 40#define MDCTL 0xA00
38 41
39/* System control register offsets */ 42#define MDSTAT_STATE_MASK 0x1f
40#define VDD3P3V_PWDN 0x48
41 43
42static void davinci_psc_mux(unsigned int id) 44/* Return nonzero iff the domain's clock is active */
45int __init davinci_psc_is_clk_active(unsigned int id)
43{ 46{
44 switch (id) { 47 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
45 case DAVINCI_LPSC_ATA: 48 u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
46 davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); 49
47 davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); 50 /* if clocked, state can be "Enable" or "SyncReset" */
48 break; 51 return mdstat & BIT(12);
49 case DAVINCI_LPSC_MMC_SD:
50 /* VDD power manupulations are done in U-Boot for CPMAC
51 * so applies to MMC as well
52 */
53 /*Set up the pull regiter for MMC */
54 davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
55 davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
56 break;
57 case DAVINCI_LPSC_I2C:
58 davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
59 break;
60 case DAVINCI_LPSC_McBSP:
61 davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
62 break;
63 default:
64 break;
65 }
66} 52}
67 53
68/* Enable or disable a PSC domain */ 54/* Enable or disable a PSC domain */
69void davinci_psc_config(unsigned int domain, unsigned int id, char enable) 55void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
70{ 56{
71 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; 57 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
58 void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
59 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
72 60
73 mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); 61 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
74 if (enable) 62 mdctl &= ~MDSTAT_STATE_MASK;
75 mdctl |= 0x00000003; /* Enable Module */ 63 mdctl |= next_state;
76 else 64 __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
77 mdctl &= 0xFFFFFFF2; /* Disable Module */
78 davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
79 65
80 pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); 66 pdstat = __raw_readl(psc_base + PDSTAT);
81 if ((pdstat & 0x00000001) == 0) { 67 if ((pdstat & 0x00000001) == 0) {
82 pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 68 pdctl1 = __raw_readl(psc_base + PDCTL1);
83 pdctl1 |= 0x1; 69 pdctl1 |= 0x1;
84 davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 70 __raw_writel(pdctl1, psc_base + PDCTL1);
85 71
86 ptcmd = 1 << domain; 72 ptcmd = 1 << domain;
87 davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); 73 __raw_writel(ptcmd, psc_base + PTCMD);
88 74
89 do { 75 do {
90 epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 76 epcpr = __raw_readl(psc_base + EPCPR);
91 EPCPR);
92 } while ((((epcpr >> domain) & 1) == 0)); 77 } while ((((epcpr >> domain) & 1) == 0));
93 78
94 pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 79 pdctl1 = __raw_readl(psc_base + PDCTL1);
95 pdctl1 |= 0x100; 80 pdctl1 |= 0x100;
96 davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); 81 __raw_writel(pdctl1, psc_base + PDCTL1);
97 82
98 do { 83 do {
99 ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 84 ptstat = __raw_readl(psc_base +
100 PTSTAT); 85 PTSTAT);
101 } while (!(((ptstat >> domain) & 1) == 0)); 86 } while (!(((ptstat >> domain) & 1) == 0));
102 } else { 87 } else {
103 ptcmd = 1 << domain; 88 ptcmd = 1 << domain;
104 davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); 89 __raw_writel(ptcmd, psc_base + PTCMD);
105 90
106 do { 91 do {
107 ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 92 ptstat = __raw_readl(psc_base + PTSTAT);
108 PTSTAT);
109 } while (!(((ptstat >> domain) & 1) == 0)); 93 } while (!(((ptstat >> domain) & 1) == 0));
110 } 94 }
111 95
112 if (enable)
113 mdstat_mask = 0x3;
114 else
115 mdstat_mask = 0x2;
116
117 do { 96 do {
118 mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + 97 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
119 MDSTAT + 4 * id); 98 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
120 } while (!((mdstat & 0x0000001F) == mdstat_mask));
121
122 if (enable)
123 davinci_psc_mux(id);
124}
125
126void __init davinci_psc_init(void)
127{
128 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
129 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
130 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
131 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1);
132 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1);
133 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1);
134
135 /* Turn on WatchDog timer LPSC. Needed for RESET to work */
136 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1);
137} 99}
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 3010f9971255..695075796522 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -32,32 +32,47 @@
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/serial.h> 33#include <mach/serial.h>
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/cputype.h>
36#include "clock.h"
35 37
36#define UART_DAVINCI_PWREMU 0x0c 38static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
37 39 int offset)
38static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up,
39 int offset)
40{ 40{
41 offset <<= up->regshift; 41 offset <<= up->regshift;
42 return (unsigned int)__raw_readb(up->membase + offset); 42 return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
43} 43}
44 44
45static inline void davinci_serial_outp(struct plat_serial8250_port *p, 45static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
46 int offset, int value) 46 int value)
47{ 47{
48 offset <<= p->regshift; 48 offset <<= p->regshift;
49 __raw_writeb(value, p->membase + offset); 49 __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
50} 50}
51 51
52static struct plat_serial8250_port serial_platform_data[] = { 52static struct plat_serial8250_port serial_platform_data[] = {
53 { 53 {
54 .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), 54 .mapbase = DAVINCI_UART0_BASE,
55 .mapbase = (unsigned long)DAVINCI_UART0_BASE,
56 .irq = IRQ_UARTINT0, 55 .irq = IRQ_UARTINT0,
57 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
57 UPF_IOREMAP,
58 .iotype = UPIO_MEM,
59 .regshift = 2,
60 },
61 {
62 .mapbase = DAVINCI_UART1_BASE,
63 .irq = IRQ_UARTINT1,
64 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
65 UPF_IOREMAP,
66 .iotype = UPIO_MEM,
67 .regshift = 2,
68 },
69 {
70 .mapbase = DAVINCI_UART2_BASE,
71 .irq = IRQ_UARTINT2,
72 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
73 UPF_IOREMAP,
58 .iotype = UPIO_MEM, 74 .iotype = UPIO_MEM,
59 .regshift = 2, 75 .regshift = 2,
60 .uartclk = 27000000,
61 }, 76 },
62 { 77 {
63 .flags = 0 78 .flags = 0
@@ -74,22 +89,68 @@ static struct platform_device serial_device = {
74 89
75static void __init davinci_serial_reset(struct plat_serial8250_port *p) 90static void __init davinci_serial_reset(struct plat_serial8250_port *p)
76{ 91{
77 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
78 unsigned int pwremu = 0; 92 unsigned int pwremu = 0;
79 93
80 davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ 94 serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
81 95
82 davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 96 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
97 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
83 mdelay(10); 98 mdelay(10);
84 99
85 pwremu |= (0x3 << 13); 100 pwremu |= (0x3 << 13);
86 pwremu |= 0x1; 101 pwremu |= 0x1;
87 davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); 102 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
103
104 if (cpu_is_davinci_dm646x())
105 serial_write_reg(p, UART_DM646X_SCR,
106 UART_DM646X_SCR_TX_WATERMARK);
107}
108
109void __init davinci_serial_init(struct davinci_uart_config *info)
110{
111 int i;
112 char name[16];
113 struct clk *uart_clk;
114 struct device *dev = &serial_device.dev;
115
116 /*
117 * Make sure the serial ports are muxed on at this point.
118 * You have to mux them off in device drivers later on
119 * if not needed.
120 */
121 for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) {
122 struct plat_serial8250_port *p = serial_platform_data + i;
123
124 if (!(info->enabled_uarts & (1 << i))) {
125 p->flags = 0;
126 continue;
127 }
128
129 if (cpu_is_davinci_dm646x())
130 p->iotype = UPIO_MEM32;
131
132 if (cpu_is_davinci_dm355()) {
133 if (i == 2) {
134 p->mapbase = (unsigned long)DM355_UART2_BASE;
135 p->irq = IRQ_DM355_UARTINT2;
136 }
137 }
138
139 sprintf(name, "uart%d", i);
140 uart_clk = clk_get(dev, name);
141 if (IS_ERR(uart_clk))
142 printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
143 __func__, __LINE__, i);
144 else {
145 clk_enable(uart_clk);
146 p->uartclk = clk_get_rate(uart_clk);
147 davinci_serial_reset(p);
148 }
149 }
88} 150}
89 151
90static int __init davinci_init(void) 152static int __init davinci_init(void)
91{ 153{
92 davinci_serial_reset(&serial_platform_data[0]);
93 return platform_device_register(&serial_device); 154 return platform_device_register(&serial_device);
94} 155}
95 156
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 6c227d4ba998..494e01bff5c3 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -16,6 +16,9 @@
16#include <linux/clockchips.h> 16#include <linux/clockchips.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/device.h>
19 22
20#include <mach/hardware.h> 23#include <mach/hardware.h>
21#include <asm/system.h> 24#include <asm/system.h>
@@ -24,8 +27,11 @@
24#include <asm/mach/time.h> 27#include <asm/mach/time.h>
25#include <asm/errno.h> 28#include <asm/errno.h>
26#include <mach/io.h> 29#include <mach/io.h>
30#include <mach/cputype.h>
31#include "clock.h"
27 32
28static struct clock_event_device clockevent_davinci; 33static struct clock_event_device clockevent_davinci;
34static unsigned int davinci_clock_tick_rate;
29 35
30#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) 36#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
31#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) 37#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
@@ -99,9 +105,9 @@ struct timer_s {
99 unsigned int id; 105 unsigned int id;
100 unsigned long period; 106 unsigned long period;
101 unsigned long opts; 107 unsigned long opts;
102 unsigned long reg_base; 108 void __iomem *base;
103 unsigned long tim_reg; 109 unsigned long tim_off;
104 unsigned long prd_reg; 110 unsigned long prd_off;
105 unsigned long enamode_shift; 111 unsigned long enamode_shift;
106 struct irqaction irqaction; 112 struct irqaction irqaction;
107}; 113};
@@ -114,15 +120,15 @@ static struct timer_s timers[];
114 120
115static int timer32_config(struct timer_s *t) 121static int timer32_config(struct timer_s *t)
116{ 122{
117 u32 tcr = davinci_readl(t->reg_base + TCR); 123 u32 tcr = __raw_readl(t->base + TCR);
118 124
119 /* disable timer */ 125 /* disable timer */
120 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); 126 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
121 davinci_writel(tcr, t->reg_base + TCR); 127 __raw_writel(tcr, t->base + TCR);
122 128
123 /* reset counter to zero, set new period */ 129 /* reset counter to zero, set new period */
124 davinci_writel(0, t->tim_reg); 130 __raw_writel(0, t->base + t->tim_off);
125 davinci_writel(t->period, t->prd_reg); 131 __raw_writel(t->period, t->base + t->prd_off);
126 132
127 /* Set enable mode */ 133 /* Set enable mode */
128 if (t->opts & TIMER_OPTS_ONESHOT) { 134 if (t->opts & TIMER_OPTS_ONESHOT) {
@@ -131,13 +137,13 @@ static int timer32_config(struct timer_s *t)
131 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; 137 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
132 } 138 }
133 139
134 davinci_writel(tcr, t->reg_base + TCR); 140 __raw_writel(tcr, t->base + TCR);
135 return 0; 141 return 0;
136} 142}
137 143
138static inline u32 timer32_read(struct timer_s *t) 144static inline u32 timer32_read(struct timer_s *t)
139{ 145{
140 return davinci_readl(t->tim_reg); 146 return __raw_readl(t->base + t->tim_off);
141} 147}
142 148
143static irqreturn_t timer_interrupt(int irq, void *dev_id) 149static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -176,51 +182,54 @@ static struct timer_s timers[] = {
176 182
177static void __init timer_init(void) 183static void __init timer_init(void)
178{ 184{
179 u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; 185 u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
180 int i; 186 int i;
181 187
182 /* Global init of each 64-bit timer as a whole */ 188 /* Global init of each 64-bit timer as a whole */
183 for(i=0; i<2; i++) { 189 for(i=0; i<2; i++) {
184 u32 tgcr, base = bases[i]; 190 u32 tgcr;
191 void __iomem *base = IO_ADDRESS(phys_bases[i]);
185 192
186 /* Disabled, Internal clock source */ 193 /* Disabled, Internal clock source */
187 davinci_writel(0, base + TCR); 194 __raw_writel(0, base + TCR);
188 195
189 /* reset both timers, no pre-scaler for timer34 */ 196 /* reset both timers, no pre-scaler for timer34 */
190 tgcr = 0; 197 tgcr = 0;
191 davinci_writel(tgcr, base + TGCR); 198 __raw_writel(tgcr, base + TGCR);
192 199
193 /* Set both timers to unchained 32-bit */ 200 /* Set both timers to unchained 32-bit */
194 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; 201 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
195 davinci_writel(tgcr, base + TGCR); 202 __raw_writel(tgcr, base + TGCR);
196 203
197 /* Unreset timers */ 204 /* Unreset timers */
198 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 205 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
199 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 206 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
200 davinci_writel(tgcr, base + TGCR); 207 __raw_writel(tgcr, base + TGCR);
201 208
202 /* Init both counters to zero */ 209 /* Init both counters to zero */
203 davinci_writel(0, base + TIM12); 210 __raw_writel(0, base + TIM12);
204 davinci_writel(0, base + TIM34); 211 __raw_writel(0, base + TIM34);
205 } 212 }
206 213
207 /* Init of each timer as a 32-bit timer */ 214 /* Init of each timer as a 32-bit timer */
208 for (i=0; i< ARRAY_SIZE(timers); i++) { 215 for (i=0; i< ARRAY_SIZE(timers); i++) {
209 struct timer_s *t = &timers[i]; 216 struct timer_s *t = &timers[i];
217 u32 phys_base;
210 218
211 if (t->name) { 219 if (t->name) {
212 t->id = i; 220 t->id = i;
213 t->reg_base = (IS_TIMER1(t->id) ? 221 phys_base = (IS_TIMER1(t->id) ?
214 DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); 222 DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
223 t->base = IO_ADDRESS(phys_base);
215 224
216 if (IS_TIMER_BOT(t->id)) { 225 if (IS_TIMER_BOT(t->id)) {
217 t->enamode_shift = 6; 226 t->enamode_shift = 6;
218 t->tim_reg = t->reg_base + TIM12; 227 t->tim_off = TIM12;
219 t->prd_reg = t->reg_base + PRD12; 228 t->prd_off = PRD12;
220 } else { 229 } else {
221 t->enamode_shift = 22; 230 t->enamode_shift = 22;
222 t->tim_reg = t->reg_base + TIM34; 231 t->tim_off = TIM34;
223 t->prd_reg = t->reg_base + PRD34; 232 t->prd_off = PRD34;
224 } 233 }
225 234
226 /* Register interrupt */ 235 /* Register interrupt */
@@ -274,7 +283,7 @@ static void davinci_set_mode(enum clock_event_mode mode,
274 283
275 switch (mode) { 284 switch (mode) {
276 case CLOCK_EVT_MODE_PERIODIC: 285 case CLOCK_EVT_MODE_PERIODIC:
277 t->period = CLOCK_TICK_RATE / (HZ); 286 t->period = davinci_clock_tick_rate / (HZ);
278 t->opts = TIMER_OPTS_PERIODIC; 287 t->opts = TIMER_OPTS_PERIODIC;
279 timer32_config(t); 288 timer32_config(t);
280 break; 289 break;
@@ -301,21 +310,29 @@ static struct clock_event_device clockevent_davinci = {
301 310
302static void __init davinci_timer_init(void) 311static void __init davinci_timer_init(void)
303{ 312{
313 struct clk *timer_clk;
314
304 static char err[] __initdata = KERN_ERR 315 static char err[] __initdata = KERN_ERR
305 "%s: can't register clocksource!\n"; 316 "%s: can't register clocksource!\n";
306 317
307 /* init timer hw */ 318 /* init timer hw */
308 timer_init(); 319 timer_init();
309 320
321 timer_clk = clk_get(NULL, "timer0");
322 BUG_ON(IS_ERR(timer_clk));
323 clk_enable(timer_clk);
324
325 davinci_clock_tick_rate = clk_get_rate(timer_clk);
326
310 /* setup clocksource */ 327 /* setup clocksource */
311 clocksource_davinci.mult = 328 clocksource_davinci.mult =
312 clocksource_khz2mult(CLOCK_TICK_RATE/1000, 329 clocksource_khz2mult(davinci_clock_tick_rate/1000,
313 clocksource_davinci.shift); 330 clocksource_davinci.shift);
314 if (clocksource_register(&clocksource_davinci)) 331 if (clocksource_register(&clocksource_davinci))
315 printk(err, clocksource_davinci.name); 332 printk(err, clocksource_davinci.name);
316 333
317 /* setup clockevent */ 334 /* setup clockevent */
318 clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 335 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
319 clockevent_davinci.shift); 336 clockevent_davinci.shift);
320 clockevent_davinci.max_delta_ns = 337 clockevent_davinci.max_delta_ns =
321 clockevent_delta2ns(0xfffffffe, &clockevent_davinci); 338 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
@@ -333,42 +350,52 @@ struct sys_timer davinci_timer = {
333 350
334/* reset board using watchdog timer */ 351/* reset board using watchdog timer */
335void davinci_watchdog_reset(void) { 352void davinci_watchdog_reset(void) {
336 u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; 353 u32 tgcr, wdtcr;
354 void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
355 struct device dev;
356 struct clk *wd_clk;
357 char *name = "watchdog";
358
359 dev_set_name(&dev, name);
360 wd_clk = clk_get(&dev, NULL);
361 if (WARN_ON(IS_ERR(wd_clk)))
362 return;
363 clk_enable(wd_clk);
337 364
338 /* disable, internal clock source */ 365 /* disable, internal clock source */
339 davinci_writel(0, base + TCR); 366 __raw_writel(0, base + TCR);
340 367
341 /* reset timer, set mode to 64-bit watchdog, and unreset */ 368 /* reset timer, set mode to 64-bit watchdog, and unreset */
342 tgcr = 0; 369 tgcr = 0;
343 davinci_writel(tgcr, base + TCR); 370 __raw_writel(tgcr, base + TCR);
344 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; 371 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
345 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | 372 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
346 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); 373 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
347 davinci_writel(tgcr, base + TCR); 374 __raw_writel(tgcr, base + TCR);
348 375
349 /* clear counter and period regs */ 376 /* clear counter and period regs */
350 davinci_writel(0, base + TIM12); 377 __raw_writel(0, base + TIM12);
351 davinci_writel(0, base + TIM34); 378 __raw_writel(0, base + TIM34);
352 davinci_writel(0, base + PRD12); 379 __raw_writel(0, base + PRD12);
353 davinci_writel(0, base + PRD34); 380 __raw_writel(0, base + PRD34);
354 381
355 /* enable */ 382 /* enable */
356 wdtcr = davinci_readl(base + WDTCR); 383 wdtcr = __raw_readl(base + WDTCR);
357 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; 384 wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
358 davinci_writel(wdtcr, base + WDTCR); 385 __raw_writel(wdtcr, base + WDTCR);
359 386
360 /* put watchdog in pre-active state */ 387 /* put watchdog in pre-active state */
361 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | 388 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
362 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 389 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
363 davinci_writel(wdtcr, base + WDTCR); 390 __raw_writel(wdtcr, base + WDTCR);
364 391
365 /* put watchdog in active state */ 392 /* put watchdog in active state */
366 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | 393 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
367 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); 394 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
368 davinci_writel(wdtcr, base + WDTCR); 395 __raw_writel(wdtcr, base + WDTCR);
369 396
370 /* write an invalid value to the WDKEY field to trigger 397 /* write an invalid value to the WDKEY field to trigger
371 * a watchdog reset */ 398 * a watchdog reset */
372 wdtcr = 0x00004000; 399 wdtcr = 0x00004000;
373 davinci_writel(wdtcr, base + WDTCR); 400 __raw_writel(wdtcr, base + WDTCR);
374} 401}
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 2429b79f6da2..abedb6337182 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -14,6 +14,8 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/irqs.h> 15#include <mach/irqs.h>
16 16
17#define DAVINCI_USB_OTG_BASE 0x01C64000
18
17#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 19#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
18static struct musb_hdrc_eps_bits musb_eps[] = { 20static struct musb_hdrc_eps_bits musb_eps[] = {
19 { "ep1_tx", 8, }, 21 { "ep1_tx", 8, },
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 22:10:54 -0500