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-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c15
-rw-r--r--arch/arm/mach-davinci/tnetv107x.c23
2 files changed, 26 insertions, 12 deletions
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index c9a86d8130d1..85503debda51 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -344,7 +344,20 @@ static struct platform_device tsc_device = {
344 344
345void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) 345void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
346{ 346{
347 int i; 347 int i, error;
348 struct clk *tsc_clk;
349
350 /*
351 * The reset defaults for tnetv107x tsc clock divider is set too high.
352 * This forces the clock down to a range that allows the ADC to
353 * complete sample conversion in time.
354 */
355 tsc_clk = clk_get(NULL, "sys_tsc_clk");
356 if (tsc_clk) {
357 error = clk_set_rate(tsc_clk, 5000000);
358 WARN_ON(error < 0);
359 clk_put(tsc_clk);
360 }
348 361
349 platform_device_register(&edma_device); 362 platform_device_register(&edma_device);
350 platform_device_register(&tnetv107x_wdt_device); 363 platform_device_register(&tnetv107x_wdt_device);
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index daeae06430b9..6fcdecec8d8c 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200);
131define_pll_clk(eth, 2, 0x0ff, 0x400); 131define_pll_clk(eth, 2, 0x0ff, 0x400);
132 132
133/* Level 2 - divided outputs from the PLLs */ 133/* Level 2 - divided outputs from the PLLs */
134#define define_pll_div_clk(pll, cname, div) \ 134#define define_pll_div_clk(pll, cname, div) \
135 static struct clk pll##_##cname##_clk = { \ 135 static struct clk pll##_##cname##_clk = { \
136 .name = #pll "_" #cname "_clk",\ 136 .name = #pll "_" #cname "_clk", \
137 .parent = &pll_##pll##_clk, \ 137 .parent = &pll_##pll##_clk, \
138 .flags = CLK_PLL, \ 138 .flags = CLK_PLL, \
139 .div_reg = PLLDIV##div, \ 139 .div_reg = PLLDIV##div, \
140 .set_rate = davinci_set_sysclk_rate, \
140 } 141 }
141 142
142define_pll_div_clk(sys, arm1176, 1); 143define_pll_div_clk(sys, arm1176, 1);
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM);
192lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); 193lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST);
193lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); 194lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST);
194lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); 195lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM);
196lpsc_clk_enabled(timer1, sys_half_clk, TIMER1);
195 197
196lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); 198lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE);
197lpsc_clk(ethss, eth_125mhz_clk, ETHSS); 199lpsc_clk(ethss, eth_125mhz_clk, ETHSS);
@@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO);
205lpsc_clk(sdio0, sys_half_clk, SDIO0); 207lpsc_clk(sdio0, sys_half_clk, SDIO0);
206lpsc_clk(sdio1, sys_half_clk, SDIO1); 208lpsc_clk(sdio1, sys_half_clk, SDIO1);
207lpsc_clk(timer0, sys_half_clk, TIMER0); 209lpsc_clk(timer0, sys_half_clk, TIMER0);
208lpsc_clk(timer1, sys_half_clk, TIMER1);
209lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); 210lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP);
210lpsc_clk(ssp, sys_half_clk, SSP); 211lpsc_clk(ssp, sys_half_clk, SSP);
211lpsc_clk(tdm0, tdm_0_clk, TDM0); 212lpsc_clk(tdm0, tdm_0_clk, TDM0);
212lpsc_clk(tdm1, tdm_1_clk, TDM1); 213lpsc_clk(tdm1, tdm_1_clk, TDM1);
213lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); 214lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ);
214lpsc_clk(mcdma, sys_half_clk, MCDMA); 215lpsc_clk(mcdma, sys_half_clk, MCDMA);
215lpsc_clk(usb0, sys_half_clk, USB0);
216lpsc_clk(usb1, sys_half_clk, USB1);
217lpsc_clk(usbss, sys_half_clk, USBSS); 216lpsc_clk(usbss, sys_half_clk, USBSS);
217lpsc_clk(usb0, clk_usbss, USB0);
218lpsc_clk(usb1, clk_usbss, USB1);
218lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); 219lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII);
219lpsc_clk(imcop, sys_dsp_clk, IMCOP); 220lpsc_clk(imcop, sys_dsp_clk, IMCOP);
220lpsc_clk(spare, sys_half_clk, SPARE); 221lpsc_clk(spare, sys_half_clk, SPARE);
@@ -281,7 +282,9 @@ static struct clk_lookup clks[] = {
281 CLK(NULL, "clk_tdm0", &clk_tdm0), 282 CLK(NULL, "clk_tdm0", &clk_tdm0),
282 CLK(NULL, "clk_vlynq", &clk_vlynq), 283 CLK(NULL, "clk_vlynq", &clk_vlynq),
283 CLK(NULL, "clk_mcdma", &clk_mcdma), 284 CLK(NULL, "clk_mcdma", &clk_mcdma),
285 CLK(NULL, "clk_usbss", &clk_usbss),
284 CLK(NULL, "clk_usb0", &clk_usb0), 286 CLK(NULL, "clk_usb0", &clk_usb0),
287 CLK(NULL, "clk_usb1", &clk_usb1),
285 CLK(NULL, "clk_tdm1", &clk_tdm1), 288 CLK(NULL, "clk_tdm1", &clk_tdm1),
286 CLK(NULL, "clk_debugss", &clk_debugss), 289 CLK(NULL, "clk_debugss", &clk_debugss),
287 CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), 290 CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii),
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = {
289 CLK(NULL, "clk_imcop", &clk_imcop), 292 CLK(NULL, "clk_imcop", &clk_imcop),
290 CLK(NULL, "clk_spare", &clk_spare), 293 CLK(NULL, "clk_spare", &clk_spare),
291 CLK("davinci_mmc.1", NULL, &clk_sdio1), 294 CLK("davinci_mmc.1", NULL, &clk_sdio1),
292 CLK(NULL, "clk_usb1", &clk_usb1),
293 CLK(NULL, "clk_usbss", &clk_usbss),
294 CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), 295 CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
295 CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), 296 CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
296 CLK(NULL, NULL, NULL), 297 CLK(NULL, NULL, NULL),