diff options
Diffstat (limited to 'arch/arm/mach-davinci/psc.c')
-rw-r--r-- | arch/arm/mach-davinci/psc.c | 87 |
1 files changed, 57 insertions, 30 deletions
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index e1b0050283a6..1334416559ad 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c | |||
@@ -25,39 +25,40 @@ | |||
25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
26 | #include <asm/hardware.h> | 26 | #include <asm/hardware.h> |
27 | #include <asm/arch/psc.h> | 27 | #include <asm/arch/psc.h> |
28 | #include <asm/arch/mux.h> | ||
28 | 29 | ||
29 | #define PTCMD __REG(0x01C41120) | 30 | /* PSC register offsets */ |
30 | #define PDSTAT __REG(0x01C41200) | 31 | #define EPCPR 0x070 |
31 | #define PDCTL1 __REG(0x01C41304) | 32 | #define PTCMD 0x120 |
32 | #define EPCPR __REG(0x01C41070) | 33 | #define PTSTAT 0x128 |
33 | #define PTSTAT __REG(0x01C41128) | 34 | #define PDSTAT 0x200 |
35 | #define PDCTL1 0x304 | ||
36 | #define MDSTAT 0x800 | ||
37 | #define MDCTL 0xA00 | ||
34 | 38 | ||
35 | #define MDSTAT IO_ADDRESS(0x01C41800) | 39 | /* System control register offsets */ |
36 | #define MDCTL IO_ADDRESS(0x01C41A00) | 40 | #define VDD3P3V_PWDN 0x48 |
37 | |||
38 | #define PINMUX0 __REG(0x01c40000) | ||
39 | #define PINMUX1 __REG(0x01c40004) | ||
40 | #define VDD3P3V_PWDN __REG(0x01C40048) | ||
41 | 41 | ||
42 | static void davinci_psc_mux(unsigned int id) | 42 | static void davinci_psc_mux(unsigned int id) |
43 | { | 43 | { |
44 | switch (id) { | 44 | switch (id) { |
45 | case DAVINCI_LPSC_ATA: | 45 | case DAVINCI_LPSC_ATA: |
46 | PINMUX0 |= (1 << 17) | (1 << 16); | 46 | davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); |
47 | davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); | ||
47 | break; | 48 | break; |
48 | case DAVINCI_LPSC_MMC_SD: | 49 | case DAVINCI_LPSC_MMC_SD: |
49 | /* VDD power manupulations are done in U-Boot for CPMAC | 50 | /* VDD power manupulations are done in U-Boot for CPMAC |
50 | * so applies to MMC as well | 51 | * so applies to MMC as well |
51 | */ | 52 | */ |
52 | /*Set up the pull regiter for MMC */ | 53 | /*Set up the pull regiter for MMC */ |
53 | VDD3P3V_PWDN = 0x0; | 54 | davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); |
54 | PINMUX1 &= (~(1 << 9)); | 55 | davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); |
55 | break; | 56 | break; |
56 | case DAVINCI_LPSC_I2C: | 57 | case DAVINCI_LPSC_I2C: |
57 | PINMUX1 |= (1 << 7); | 58 | davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); |
58 | break; | 59 | break; |
59 | case DAVINCI_LPSC_McBSP: | 60 | case DAVINCI_LPSC_McBSP: |
60 | PINMUX1 |= (1 << 10); | 61 | davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); |
61 | break; | 62 | break; |
62 | default: | 63 | default: |
63 | break; | 64 | break; |
@@ -67,33 +68,59 @@ static void davinci_psc_mux(unsigned int id) | |||
67 | /* Enable or disable a PSC domain */ | 68 | /* Enable or disable a PSC domain */ |
68 | void davinci_psc_config(unsigned int domain, unsigned int id, char enable) | 69 | void davinci_psc_config(unsigned int domain, unsigned int id, char enable) |
69 | { | 70 | { |
70 | volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); | 71 | u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; |
71 | volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); | ||
72 | 72 | ||
73 | if (id < 0) | 73 | if (id < 0) |
74 | return; | 74 | return; |
75 | 75 | ||
76 | mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); | ||
76 | if (enable) | 77 | if (enable) |
77 | *mdctl |= 0x00000003; /* Enable Module */ | 78 | mdctl |= 0x00000003; /* Enable Module */ |
78 | else | 79 | else |
79 | *mdctl &= 0xFFFFFFF2; /* Disable Module */ | 80 | mdctl &= 0xFFFFFFF2; /* Disable Module */ |
81 | davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); | ||
82 | |||
83 | pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); | ||
84 | if ((pdstat & 0x00000001) == 0) { | ||
85 | pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); | ||
86 | pdctl1 |= 0x1; | ||
87 | davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); | ||
88 | |||
89 | ptcmd = 1 << domain; | ||
90 | davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); | ||
80 | 91 | ||
81 | if ((PDSTAT & 0x00000001) == 0) { | 92 | do { |
82 | PDCTL1 |= 0x1; | 93 | epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + |
83 | PTCMD = (1 << domain); | 94 | EPCPR); |
84 | while ((((EPCPR >> domain) & 1) == 0)); | 95 | } while ((((epcpr >> domain) & 1) == 0)); |
85 | 96 | ||
86 | PDCTL1 |= 0x100; | 97 | pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); |
87 | while (!(((PTSTAT >> domain) & 1) == 0)); | 98 | pdctl1 |= 0x100; |
99 | davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); | ||
100 | |||
101 | do { | ||
102 | ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + | ||
103 | PTSTAT); | ||
104 | } while (!(((ptstat >> domain) & 1) == 0)); | ||
88 | } else { | 105 | } else { |
89 | PTCMD = (1 << domain); | 106 | ptcmd = 1 << domain; |
90 | while (!(((PTSTAT >> domain) & 1) == 0)); | 107 | davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); |
108 | |||
109 | do { | ||
110 | ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + | ||
111 | PTSTAT); | ||
112 | } while (!(((ptstat >> domain) & 1) == 0)); | ||
91 | } | 113 | } |
92 | 114 | ||
93 | if (enable) | 115 | if (enable) |
94 | while (!((*mdstat & 0x0000001F) == 0x3)); | 116 | mdstat_mask = 0x3; |
95 | else | 117 | else |
96 | while (!((*mdstat & 0x0000001F) == 0x2)); | 118 | mdstat_mask = 0x2; |
119 | |||
120 | do { | ||
121 | mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + | ||
122 | MDSTAT + 4 * id); | ||
123 | } while (!((mdstat & 0x0000001F) == mdstat_mask)); | ||
97 | 124 | ||
98 | if (enable) | 125 | if (enable) |
99 | davinci_psc_mux(id); | 126 | davinci_psc_mux(id); |