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Diffstat (limited to 'arch/arm/mach-davinci/mux.c')
-rw-r--r--arch/arm/mach-davinci/mux.c19
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83415f3..f34a8dcdae2b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -22,6 +22,8 @@
22#include <mach/mux.h> 22#include <mach/mux.h>
23#include <mach/common.h> 23#include <mach/common.h>
24 24
25static void __iomem *pinmux_base;
26
25/* 27/*
26 * Sets the DAVINCI MUX register based on the table 28 * Sets the DAVINCI MUX register based on the table
27 */ 29 */
@@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
29{ 31{
30 static DEFINE_SPINLOCK(mux_spin_lock); 32 static DEFINE_SPINLOCK(mux_spin_lock);
31 struct davinci_soc_info *soc_info = &davinci_soc_info; 33 struct davinci_soc_info *soc_info = &davinci_soc_info;
32 void __iomem *base = soc_info->pinmux_base;
33 unsigned long flags; 34 unsigned long flags;
34 const struct mux_config *cfg; 35 const struct mux_config *cfg;
35 unsigned int reg_orig = 0, reg = 0; 36 unsigned int reg_orig = 0, reg = 0;
36 unsigned int mask, warn = 0; 37 unsigned int mask, warn = 0;
37 38
38 if (!soc_info->pinmux_pins) 39 if (WARN_ON(!soc_info->pinmux_pins))
39 BUG(); 40 return -ENODEV;
41
42 if (!pinmux_base) {
43 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
44 if (WARN_ON(!pinmux_base))
45 return -ENOMEM;
46 }
40 47
41 if (index >= soc_info->pinmux_pins_num) { 48 if (index >= soc_info->pinmux_pins_num) {
42 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 49 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
57 unsigned tmp1, tmp2; 64 unsigned tmp1, tmp2;
58 65
59 spin_lock_irqsave(&mux_spin_lock, flags); 66 spin_lock_irqsave(&mux_spin_lock, flags);
60 reg_orig = __raw_readl(base + cfg->mux_reg); 67 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
61 68
62 mask = (cfg->mask << cfg->mask_offset); 69 mask = (cfg->mask << cfg->mask_offset);
63 tmp1 = reg_orig & mask; 70 tmp1 = reg_orig & mask;
@@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
69 if (tmp1 != tmp2) 76 if (tmp1 != tmp2)
70 warn = 1; 77 warn = 1;
71 78
72 __raw_writel(reg, base + cfg->mux_reg); 79 __raw_writel(reg, pinmux_base + cfg->mux_reg);
73 spin_unlock_irqrestore(&mux_spin_lock, flags); 80 spin_unlock_irqrestore(&mux_spin_lock, flags);
74 } 81 }
75 82
@@ -91,7 +98,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
91} 98}
92EXPORT_SYMBOL(davinci_cfg_reg); 99EXPORT_SYMBOL(davinci_cfg_reg);
93 100
94int da8xx_pinmux_setup(const short pins[]) 101int __init_or_module davinci_cfg_reg_list(const short pins[])
95{ 102{
96 int i, error = -EINVAL; 103 int i, error = -EINVAL;
97 104