1 files changed, 7 insertions, 74 deletions
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 38021af8359a..af92ffee8471 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,8 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/cputype.h>
+#include <mach/common.h>
 #include <asm/mach/irq.h>
 #define IRQ_BIT(irq)            ((irq) & 0x1f)
@@ -42,12 +44,12 @@
 static inline unsigned int davinci_irq_readl(int offset)
 {
-        return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+        return __raw_readl(davinci_intc_base + offset);
 }
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-        davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+        __raw_writel(value, davinci_intc_base + offset);
 }
 /* Disable interrupt */
@@ -108,80 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
        .unmask = davinci_unmask_irq,
 };
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
-        [IRQ_VDINT0]            = 2,
-        [IRQ_VDINT1]            = 6,
-        [IRQ_VDINT2]            = 6,
-        [IRQ_HISTINT]           = 6,
-        [IRQ_H3AINT]            = 6,
-        [IRQ_PRVUINT]           = 6,
-        [IRQ_RSZINT]            = 6,
-        [7]                     = 7,
-        [IRQ_VENCINT]           = 6,
-        [IRQ_ASQINT]            = 6,
-        [IRQ_IMXINT]            = 6,
-        [IRQ_VLCDINT]           = 6,
-        [IRQ_USBINT]            = 4,
-        [IRQ_EMACINT]           = 4,
-        [14]                    = 7,
-        [15]                    = 7,
-        [IRQ_CCINT0]            = 5,    /* dma */
-        [IRQ_CCERRINT]          = 5,    /* dma */
-        [IRQ_TCERRINT0]         = 5,    /* dma */
-        [IRQ_TCERRINT]          = 5,    /* dma */
-        [IRQ_PSCIN]             = 7,
-        [21]                    = 7,
-        [IRQ_IDE]               = 4,
-        [23]                    = 7,
-        [IRQ_MBXINT]            = 7,
-        [IRQ_MBRINT]            = 7,
-        [IRQ_MMCINT]            = 7,
-        [IRQ_SDIOINT]           = 7,
-        [28]                    = 7,
-        [IRQ_DDRINT]            = 7,
-        [IRQ_AEMIFINT]          = 7,
-        [IRQ_VLQINT]            = 4,
-        [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
-        [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
-        [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
-        [IRQ_TINT1_TINT34]      = 7,    /* system tick */
-        [IRQ_PWMINT0]           = 7,
-        [IRQ_PWMINT1]           = 7,
-        [IRQ_PWMINT2]           = 7,
-        [IRQ_I2C]               = 3,
-        [IRQ_UARTINT0]          = 3,
-        [IRQ_UARTINT1]          = 3,
-        [IRQ_UARTINT2]          = 3,
-        [IRQ_SPINT0]            = 3,
-        [IRQ_SPINT1]            = 3,
-        [45]                    = 7,
-        [IRQ_DSP2ARM0]          = 4,
-        [IRQ_DSP2ARM1]          = 4,
-        [IRQ_GPIO0]             = 7,
-        [IRQ_GPIO1]             = 7,
-        [IRQ_GPIO2]             = 7,
-        [IRQ_GPIO3]             = 7,
-        [IRQ_GPIO4]             = 7,
-        [IRQ_GPIO5]             = 7,
-        [IRQ_GPIO6]             = 7,
-        [IRQ_GPIO7]             = 7,
-        [IRQ_GPIOBNK0]          = 7,
-        [IRQ_GPIOBNK1]          = 7,
-        [IRQ_GPIOBNK2]          = 7,
-        [IRQ_GPIOBNK3]          = 7,
-        [IRQ_GPIOBNK4]          = 7,
-        [IRQ_COMMTX]            = 7,
-        [IRQ_COMMRX]            = 7,
-        [IRQ_EMUINT]            = 7,
-};
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
        unsigned i;
-        const u8 *priority = default_priorities;
+        const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
        /* Clear all interrupt requests */
        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -209,8 +142,8 @@ void __init davinci_irq_init(void)
                unsigned        j;
                u32             pri;
-                for (j = 0, pri = 0; j < 32; j += 4, priority++)
+                for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
-                        pri |= (*priority & 0x07) << j;
+                        pri |= (*davinci_def_priorities & 0x07) << j;
                davinci_irq_writel(pri, i);
        }

diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 38021af8359a..af92ffee8471 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,8 @@
25	#include <linux/io.h>	25	#include <linux/io.h>
26		26
27	#include <mach/hardware.h>	27	#include <mach/hardware.h>
		28	#include <mach/cputype.h>
		29	#include <mach/common.h>
28	#include <asm/mach/irq.h>	30	#include <asm/mach/irq.h>
29		31
30	#define IRQ_BIT(irq) ((irq) & 0x1f)	32	#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -42,12 +44,12 @@
42		44
43	static inline unsigned int davinci_irq_readl(int offset)	45	static inline unsigned int davinci_irq_readl(int offset)
44	{	46	{
45	return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);	47	return __raw_readl(davinci_intc_base + offset);
46	}	48	}
47		49
48	static inline void davinci_irq_writel(unsigned long value, int offset)	50	static inline void davinci_irq_writel(unsigned long value, int offset)
49	{	51	{
50	davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);	52	__raw_writel(value, davinci_intc_base + offset);
51	}	53	}
52		54
53	/* Disable interrupt */	55	/* Disable interrupt */
@@ -108,80 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
108	.unmask = davinci_unmask_irq,	110	.unmask = davinci_unmask_irq,
109	};	111	};
110		112
111
112	/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
113	static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
114	[IRQ_VDINT0] = 2,
115	[IRQ_VDINT1] = 6,
116	[IRQ_VDINT2] = 6,
117	[IRQ_HISTINT] = 6,
118	[IRQ_H3AINT] = 6,
119	[IRQ_PRVUINT] = 6,
120	[IRQ_RSZINT] = 6,
121	[7] = 7,
122	[IRQ_VENCINT] = 6,
123	[IRQ_ASQINT] = 6,
124	[IRQ_IMXINT] = 6,
125	[IRQ_VLCDINT] = 6,
126	[IRQ_USBINT] = 4,
127	[IRQ_EMACINT] = 4,
128	[14] = 7,
129	[15] = 7,
130	[IRQ_CCINT0] = 5, /* dma */
131	[IRQ_CCERRINT] = 5, /* dma */
132	[IRQ_TCERRINT0] = 5, /* dma */
133	[IRQ_TCERRINT] = 5, /* dma */
134	[IRQ_PSCIN] = 7,
135	[21] = 7,
136	[IRQ_IDE] = 4,
137	[23] = 7,
138	[IRQ_MBXINT] = 7,
139	[IRQ_MBRINT] = 7,
140	[IRQ_MMCINT] = 7,
141	[IRQ_SDIOINT] = 7,
142	[28] = 7,
143	[IRQ_DDRINT] = 7,
144	[IRQ_AEMIFINT] = 7,
145	[IRQ_VLQINT] = 4,
146	[IRQ_TINT0_TINT12] = 2, /* clockevent */
147	[IRQ_TINT0_TINT34] = 2, /* clocksource */
148	[IRQ_TINT1_TINT12] = 7, /* DSP timer */
149	[IRQ_TINT1_TINT34] = 7, /* system tick */
150	[IRQ_PWMINT0] = 7,
151	[IRQ_PWMINT1] = 7,
152	[IRQ_PWMINT2] = 7,
153	[IRQ_I2C] = 3,
154	[IRQ_UARTINT0] = 3,
155	[IRQ_UARTINT1] = 3,
156	[IRQ_UARTINT2] = 3,
157	[IRQ_SPINT0] = 3,
158	[IRQ_SPINT1] = 3,
159	[45] = 7,
160	[IRQ_DSP2ARM0] = 4,
161	[IRQ_DSP2ARM1] = 4,
162	[IRQ_GPIO0] = 7,
163	[IRQ_GPIO1] = 7,
164	[IRQ_GPIO2] = 7,
165	[IRQ_GPIO3] = 7,
166	[IRQ_GPIO4] = 7,
167	[IRQ_GPIO5] = 7,
168	[IRQ_GPIO6] = 7,
169	[IRQ_GPIO7] = 7,
170	[IRQ_GPIOBNK0] = 7,
171	[IRQ_GPIOBNK1] = 7,
172	[IRQ_GPIOBNK2] = 7,
173	[IRQ_GPIOBNK3] = 7,
174	[IRQ_GPIOBNK4] = 7,
175	[IRQ_COMMTX] = 7,
176	[IRQ_COMMRX] = 7,
177	[IRQ_EMUINT] = 7,
178	};
179
180	/* ARM Interrupt Controller Initialization */	113	/* ARM Interrupt Controller Initialization */
181	void __init davinci_irq_init(void)	114	void __init davinci_irq_init(void)
182	{	115	{
183	unsigned i;	116	unsigned i;
184	const u8 *priority = default_priorities;	117	const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
185		118
186	/* Clear all interrupt requests */	119	/* Clear all interrupt requests */
187	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);	120	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -209,8 +142,8 @@ void __init davinci_irq_init(void)
209	unsigned j;	142	unsigned j;
210	u32 pri;	143	u32 pri;
211		144
212	for (j = 0, pri = 0; j < 32; j += 4, priority++)	145	for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
213	pri \|= (*priority & 0x07) << j;	146	pri \|= (*davinci_def_priorities & 0x07) << j;
214	davinci_irq_writel(pri, i);	147	davinci_irq_writel(pri, i);
215	}	148	}
216		149