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-rw-r--r--arch/arm/mach-davinci/irq.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index af92ffee8471..784ddf3c5ad4 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -116,6 +116,11 @@ void __init davinci_irq_init(void)
116 unsigned i; 116 unsigned i;
117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; 117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
118 118
119 davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
120 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
121 if (WARN_ON(!davinci_intc_base))
122 return;
123
119 /* Clear all interrupt requests */ 124 /* Clear all interrupt requests */
120 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 125 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
121 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); 126 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
@@ -148,7 +153,7 @@ void __init davinci_irq_init(void)
148 } 153 }
149 154
150 /* set up genirq dispatch for ARM INTC */ 155 /* set up genirq dispatch for ARM INTC */
151 for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) { 156 for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
152 set_irq_chip(i, &davinci_irq_chip_0); 157 set_irq_chip(i, &davinci_irq_chip_0);
153 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 158 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
154 if (i != IRQ_TINT1_TINT34) 159 if (i != IRQ_TINT1_TINT34)