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-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/clkdev.h13
-rw-r--r--arch/arm/mach-davinci/include/mach/clock.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h49
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h37
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h228
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h51
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h103
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h220
-rw-r--r--arch/arm/mach-davinci/include/mach/nand.h80
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h53
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h21
15 files changed, 808 insertions, 121 deletions
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
new file mode 100644
index 000000000000..3216f21c1238
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
@@ -0,0 +1,20 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index 38bdd49bc181..a3b040219876 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -17,6 +17,5 @@ struct clk;
17 17
18extern int clk_register(struct clk *clk); 18extern int clk_register(struct clk *clk);
19extern void clk_unregister(struct clk *clk); 19extern void clk_unregister(struct clk *clk);
20extern int davinci_clk_init(void);
21 20
22#endif 21#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4b522e5c70ec..191770976250 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,6 +16,12 @@ struct sys_timer;
16 16
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void);
21
22/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec);
24
19/* parameters describe VBUS sourcing for host mode */ 25/* parameters describe VBUS sourcing for host mode */
20extern void setup_usb(unsigned mA, unsigned potpgt_msec); 26extern void setup_usb(unsigned mA, unsigned potpgt_msec);
21 27
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
new file mode 100644
index 000000000000..27cfb1b3a662
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -0,0 +1,49 @@
1/*
2 * DaVinci CPU type detection
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * Defines the cpu_is_*() macros for runtime detection of DaVinci
7 * device type. In addtion, if support for a given device is not
8 * compiled in to the kernel, the macros return 0 so that
9 * resulting code can be optimized out.
10 *
11 * 2009 (c) Deep Root Systems, LLC. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16#ifndef _ASM_ARCH_CPU_H
17#define _ASM_ARCH_CPU_H
18
19extern unsigned int davinci_rev(void);
20
21#define IS_DAVINCI_CPU(type, id) \
22static inline int is_davinci_dm ##type(void) \
23{ \
24 return (davinci_rev() == (id)) ? 1 : 0; \
25}
26
27IS_DAVINCI_CPU(644x, 0x6446)
28IS_DAVINCI_CPU(646x, 0x6467)
29IS_DAVINCI_CPU(355, 0x355)
30
31#ifdef CONFIG_ARCH_DAVINCI_DM644x
32#define cpu_is_davinci_dm644x() is_davinci_dm644x()
33#else
34#define cpu_is_davinci_dm644x() 0
35#endif
36
37#ifdef CONFIG_ARCH_DAVINCI_DM646x
38#define cpu_is_davinci_dm646x() is_davinci_dm646x()
39#else
40#define cpu_is_davinci_dm646x() 0
41#endif
42
43#ifdef CONFIG_ARCH_DAVINCI_DM355
44#define cpu_is_davinci_dm355() is_davinci_dm355()
45#else
46#define cpu_is_davinci_dm355() 0
47#endif
48
49#endif
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 000000000000..3dcb9f4e58b4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,37 @@
1/*
2 * This file contains the processor specific definitions
3 * of the TI DM644x.
4 *
5 * Copyright (C) 2008 Texas Instruments.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H
24
25#include <linux/platform_device.h>
26#include <mach/hardware.h>
27
28#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
30#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
31#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
32#define DM644X_EMAC_MDIO_OFFSET (0x4000)
33#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
34
35void __init dm644x_init(void);
36
37#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
new file mode 100644
index 000000000000..f6fc5396dafc
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -0,0 +1,228 @@
1/*
2 * TI DAVINCI dma definitions
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28/*
29 * This EDMA3 programming framework exposes two basic kinds of resource:
30 *
31 * Channel Triggers transfers, usually from a hardware event but
32 * also manually or by "chaining" from DMA completions.
33 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
34 *
35 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
36 * "set"), source and destination addresses, a link to a
37 * next PaRAM slot (if any), options for the transfer, and
38 * instructions for updating those addresses. There are
39 * more than twice as many slots as event channels.
40 *
41 * Each PaRAM set describes a sequence of transfers, either for one large
42 * buffer or for several discontiguous smaller buffers. An EDMA transfer
43 * is driven only from a channel, which performs the transfers specified
44 * in its PaRAM slot until there are no more transfers. When that last
45 * transfer completes, the "link" field may be used to reload the channel's
46 * PaRAM slot with a new transfer descriptor.
47 *
48 * The EDMA Channel Controller (CC) maps requests from channels into physical
49 * Transfer Controller (TC) requests when the channel triggers (by hardware
50 * or software events, or by chaining). The two physical DMA channels provided
51 * by the TCs are thus shared by many logical channels.
52 *
53 * DaVinci hardware also has a "QDMA" mechanism which is not currently
54 * supported through this interface. (DSP firmware uses it though.)
55 */
56
57#ifndef EDMA_H_
58#define EDMA_H_
59
60/* PaRAM slots are laid out like this */
61struct edmacc_param {
62 unsigned int opt;
63 unsigned int src;
64 unsigned int a_b_cnt;
65 unsigned int dst;
66 unsigned int src_dst_bidx;
67 unsigned int link_bcntrld;
68 unsigned int src_dst_cidx;
69 unsigned int ccnt;
70};
71
72#define CCINT0_INTERRUPT 16
73#define CCERRINT_INTERRUPT 17
74#define TCERRINT0_INTERRUPT 18
75#define TCERRINT1_INTERRUPT 19
76
77/* fields in edmacc_param.opt */
78#define SAM BIT(0)
79#define DAM BIT(1)
80#define SYNCDIM BIT(2)
81#define STATIC BIT(3)
82#define EDMA_FWID (0x07 << 8)
83#define TCCMODE BIT(11)
84#define EDMA_TCC(t) ((t) << 12)
85#define TCINTEN BIT(20)
86#define ITCINTEN BIT(21)
87#define TCCHEN BIT(22)
88#define ITCCHEN BIT(23)
89
90#define TRWORD (0x7<<2)
91#define PAENTRY (0x1ff<<5)
92
93/* Drivers should avoid using these symbolic names for dm644x
94 * channels, and use platform_device IORESOURCE_DMA resources
95 * instead. (Other DaVinci chips have different peripherals
96 * and thus have different DMA channel mappings.)
97 */
98#define DAVINCI_DMA_MCBSP_TX 2
99#define DAVINCI_DMA_MCBSP_RX 3
100#define DAVINCI_DMA_VPSS_HIST 4
101#define DAVINCI_DMA_VPSS_H3A 5
102#define DAVINCI_DMA_VPSS_PRVU 6
103#define DAVINCI_DMA_VPSS_RSZ 7
104#define DAVINCI_DMA_IMCOP_IMXINT 8
105#define DAVINCI_DMA_IMCOP_VLCDINT 9
106#define DAVINCI_DMA_IMCO_PASQINT 10
107#define DAVINCI_DMA_IMCOP_DSQINT 11
108#define DAVINCI_DMA_SPI_SPIX 16
109#define DAVINCI_DMA_SPI_SPIR 17
110#define DAVINCI_DMA_UART0_URXEVT0 18
111#define DAVINCI_DMA_UART0_UTXEVT0 19
112#define DAVINCI_DMA_UART1_URXEVT1 20
113#define DAVINCI_DMA_UART1_UTXEVT1 21
114#define DAVINCI_DMA_UART2_URXEVT2 22
115#define DAVINCI_DMA_UART2_UTXEVT2 23
116#define DAVINCI_DMA_MEMSTK_MSEVT 24
117#define DAVINCI_DMA_MMCRXEVT 26
118#define DAVINCI_DMA_MMCTXEVT 27
119#define DAVINCI_DMA_I2C_ICREVT 28
120#define DAVINCI_DMA_I2C_ICXEVT 29
121#define DAVINCI_DMA_GPIO_GPINT0 32
122#define DAVINCI_DMA_GPIO_GPINT1 33
123#define DAVINCI_DMA_GPIO_GPINT2 34
124#define DAVINCI_DMA_GPIO_GPINT3 35
125#define DAVINCI_DMA_GPIO_GPINT4 36
126#define DAVINCI_DMA_GPIO_GPINT5 37
127#define DAVINCI_DMA_GPIO_GPINT6 38
128#define DAVINCI_DMA_GPIO_GPINT7 39
129#define DAVINCI_DMA_GPIO_GPBNKINT0 40
130#define DAVINCI_DMA_GPIO_GPBNKINT1 41
131#define DAVINCI_DMA_GPIO_GPBNKINT2 42
132#define DAVINCI_DMA_GPIO_GPBNKINT3 43
133#define DAVINCI_DMA_GPIO_GPBNKINT4 44
134#define DAVINCI_DMA_TIMER0_TINT0 48
135#define DAVINCI_DMA_TIMER1_TINT1 49
136#define DAVINCI_DMA_TIMER2_TINT2 50
137#define DAVINCI_DMA_TIMER3_TINT3 51
138#define DAVINCI_DMA_PWM0 52
139#define DAVINCI_DMA_PWM1 53
140#define DAVINCI_DMA_PWM2 54
141
142/*ch_status paramater of callback function possible values*/
143#define DMA_COMPLETE 1
144#define DMA_CC_ERROR 2
145#define DMA_TC1_ERROR 3
146#define DMA_TC2_ERROR 4
147
148enum address_mode {
149 INCR = 0,
150 FIFO = 1
151};
152
153enum fifo_width {
154 W8BIT = 0,
155 W16BIT = 1,
156 W32BIT = 2,
157 W64BIT = 3,
158 W128BIT = 4,
159 W256BIT = 5
160};
161
162enum dma_event_q {
163 EVENTQ_0 = 0,
164 EVENTQ_1 = 1,
165 EVENTQ_DEFAULT = -1
166};
167
168enum sync_dimension {
169 ASYNC = 0,
170 ABSYNC = 1
171};
172
173#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
174#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
175
176/* alloc/free DMA channels and their dedicated parameter RAM slots */
177int edma_alloc_channel(int channel,
178 void (*callback)(unsigned channel, u16 ch_status, void *data),
179 void *data, enum dma_event_q);
180void edma_free_channel(unsigned channel);
181
182/* alloc/free parameter RAM slots */
183int edma_alloc_slot(int slot);
184void edma_free_slot(unsigned slot);
185
186/* calls that operate on part of a parameter RAM slot */
187void edma_set_src(unsigned slot, dma_addr_t src_port,
188 enum address_mode mode, enum fifo_width);
189void edma_set_dest(unsigned slot, dma_addr_t dest_port,
190 enum address_mode mode, enum fifo_width);
191void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
192void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
193void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
194void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
195 u16 bcnt_rld, enum sync_dimension sync_mode);
196void edma_link(unsigned from, unsigned to);
197void edma_unlink(unsigned from);
198
199/* calls that operate on an entire parameter RAM slot */
200void edma_write_slot(unsigned slot, const struct edmacc_param *params);
201void edma_read_slot(unsigned slot, struct edmacc_param *params);
202
203/* channel control operations */
204int edma_start(unsigned channel);
205void edma_stop(unsigned channel);
206void edma_clean_channel(unsigned channel);
207void edma_clear_event(unsigned channel);
208void edma_pause(unsigned channel);
209void edma_resume(unsigned channel);
210
211/* UNRELATED TO DMA */
212int davinci_alloc_iram(unsigned size);
213void davinci_free_iram(unsigned addr, unsigned size);
214
215/* platform_data for EDMA driver */
216struct edma_soc_info {
217
218 /* how many dma resources of each type */
219 unsigned n_channel;
220 unsigned n_region;
221 unsigned n_slot;
222 unsigned n_tc;
223
224 /* list of channels with no even trigger; terminated by "-1" */
225 const s8 *noevent;
226};
227
228#endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index b456f079f43f..efe3281364e6 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -15,9 +15,11 @@
15 15
16#include <linux/io.h> 16#include <linux/io.h>
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18#include <mach/hardware.h> 18
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20 20
21#define DAVINCI_GPIO_BASE 0x01C67000
22
21/* 23/*
22 * basic gpio routines 24 * basic gpio routines
23 * 25 *
@@ -26,23 +28,18 @@
26 * go through boot loaders. 28 * go through boot loaders.
27 * 29 *
28 * the gpio clock will be turned on when gpios are used, and you may also 30 * the gpio clock will be turned on when gpios are used, and you may also
29 * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are 31 * need to pay attention to PINMUX registers to be sure those pins are
30 * used as gpios, not with other peripherals. 32 * used as gpios, not with other peripherals.
31 * 33 *
32 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, 34 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
33 * and maybe for later updates, code should write GPIO(N) or: 35 * and maybe for later updates, code may write GPIO(N). These may be
34 * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) 36 * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
35 * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) 37 * may not support all the GPIOs in that range.
36 *
37 * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
38 * for now, that's != GPIO(N)
39 * 38 *
40 * GPIOs can also be on external chips, numbered after the ones built-in 39 * GPIOs can also be on external chips, numbered after the ones built-in
41 * to the DaVinci chip. For now, they won't be usable as IRQ sources. 40 * to the DaVinci chip. For now, they won't be usable as IRQ sources.
42 */ 41 */
43#define GPIO(X) (X) /* 0 <= X <= 70 */ 42#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
44#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
45#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
46 43
47struct gpio_controller { 44struct gpio_controller {
48 u32 dir; 45 u32 dir;
@@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio)
71{ 68{
72 void *__iomem ptr; 69 void *__iomem ptr;
73 70
74 if (gpio < 32) 71 if (gpio < 32 * 1)
75 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); 72 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
76 else if (gpio < 64) 73 else if (gpio < 32 * 2)
77 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); 74 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
78 else if (gpio < DAVINCI_N_GPIO) 75 else if (gpio < 32 * 3)
79 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); 76 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
77 else if (gpio < 32 * 4)
78 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
80 else 79 else
81 ptr = NULL; 80 ptr = NULL;
82 return ptr; 81 return ptr;
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a2e8969afaca..48c77934d519 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common hardware definitions 2 * Hardware definitions common to all DaVinci family processors
3 * 3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 * 5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
@@ -12,41 +12,16 @@
12#define __ASM_ARCH_HARDWARE_H 12#define __ASM_ARCH_HARDWARE_H
13 13
14/* 14/*
15 * Base register addresses 15 * Before you add anything to ths file:
16 *
17 * This header is for defines common to ALL DaVinci family chips.
18 * Anything that is chip specific should go in <chipname>.h,
19 * and the chip/board init code should then explicitly include
20 * <chipname>.h
16 */ 21 */
17#define DAVINCI_DMA_3PCC_BASE (0x01C00000) 22#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
18#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) 23
19#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) 24/* System control register offsets */
20#define DAVINCI_I2C_BASE (0x01C21000) 25#define DM64XX_VDD3P3V_PWDN 0x48
21#define DAVINCI_PWM0_BASE (0x01C22000)
22#define DAVINCI_PWM1_BASE (0x01C22400)
23#define DAVINCI_PWM2_BASE (0x01C22800)
24#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
25#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
26#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
27#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
28#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
29#define DAVINCI_IEEE1394_BASE (0x01C60000)
30#define DAVINCI_USB_OTG_BASE (0x01C64000)
31#define DAVINCI_CFC_ATA_BASE (0x01C66000)
32#define DAVINCI_SPI_BASE (0x01C66800)
33#define DAVINCI_GPIO_BASE (0x01C67000)
34#define DAVINCI_UHPI_BASE (0x01C67800)
35#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
36#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
37#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
38#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
39#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
40#define DAVINCI_IMCOP_BASE (0x01CC0000)
41#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
42#define DAVINCI_VLYNQ_BASE (0x01E01000)
43#define DAVINCI_MCBSP_BASE (0x01E02000)
44#define DAVINCI_MMC_SD_BASE (0x01E10000)
45#define DAVINCI_MS_BASE (0x01E20000)
46#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
47#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
48#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
49#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
50#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
51 26
52#endif /* __ASM_ARCH_HARDWARE_H */ 27#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index a48795fd2417..2479785405af 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -40,22 +40,12 @@
40#else 40#else
41#define IOMEM(x) ((void __force __iomem *)(x)) 41#define IOMEM(x) ((void __force __iomem *)(x))
42 42
43/* 43#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
44 * Functions to access the DaVinci IO region 44#define __arch_iounmap(v) davinci_iounmap(v)
45 *
46 * NOTE: - Use davinci_read/write[bwl] for physical register addresses
47 * - Use __raw_read/write[bwl]() for virtual register addresses
48 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
49 * - DO NOT use hardcoded virtual addresses to allow changing the
50 * IO address space again if needed
51 */
52#define davinci_readb(a) __raw_readb(IO_ADDRESS(a))
53#define davinci_readw(a) __raw_readw(IO_ADDRESS(a))
54#define davinci_readl(a) __raw_readl(IO_ADDRESS(a))
55 45
56#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a)) 46void __iomem *davinci_ioremap(unsigned long phys, size_t size,
57#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a)) 47 unsigned int type);
58#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a)) 48void davinci_iounmap(volatile void __iomem *addr);
59 49
60#endif /* __ASSEMBLER__ */ 50#endif /* __ASSEMBLER__ */
61#endif /* __ASM_ARCH_IO_H */ 51#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..18066074c995 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -96,10 +96,111 @@
96#define IRQ_EMUINT 63 96#define IRQ_EMUINT 63
97 97
98#define DAVINCI_N_AINTC_IRQ 64 98#define DAVINCI_N_AINTC_IRQ 64
99#define DAVINCI_N_GPIO 71 99#define DAVINCI_N_GPIO 104
100 100
101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) 101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
102 102
103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
104 104
105/* DaVinci DM6467-specific Interrupts */
106#define IRQ_DM646X_VP_VERTINT0 0
107#define IRQ_DM646X_VP_VERTINT1 1
108#define IRQ_DM646X_VP_VERTINT2 2
109#define IRQ_DM646X_VP_VERTINT3 3
110#define IRQ_DM646X_VP_ERRINT 4
111#define IRQ_DM646X_RESERVED_1 5
112#define IRQ_DM646X_RESERVED_2 6
113#define IRQ_DM646X_WDINT 7
114#define IRQ_DM646X_CRGENINT0 8
115#define IRQ_DM646X_CRGENINT1 9
116#define IRQ_DM646X_TSIFINT0 10
117#define IRQ_DM646X_TSIFINT1 11
118#define IRQ_DM646X_VDCEINT 12
119#define IRQ_DM646X_USBINT 13
120#define IRQ_DM646X_USBDMAINT 14
121#define IRQ_DM646X_PCIINT 15
122#define IRQ_DM646X_TCERRINT2 20
123#define IRQ_DM646X_TCERRINT3 21
124#define IRQ_DM646X_IDE 22
125#define IRQ_DM646X_HPIINT 23
126#define IRQ_DM646X_EMACRXTHINT 24
127#define IRQ_DM646X_EMACRXINT 25
128#define IRQ_DM646X_EMACTXINT 26
129#define IRQ_DM646X_EMACMISCINT 27
130#define IRQ_DM646X_MCASP0TXINT 28
131#define IRQ_DM646X_MCASP0RXINT 29
132#define IRQ_DM646X_RESERVED_3 31
133#define IRQ_DM646X_MCASP1TXINT 32
134#define IRQ_DM646X_VLQINT 38
135#define IRQ_DM646X_UARTINT2 42
136#define IRQ_DM646X_SPINT0 43
137#define IRQ_DM646X_SPINT1 44
138#define IRQ_DM646X_DSP2ARMINT 45
139#define IRQ_DM646X_RESERVED_4 46
140#define IRQ_DM646X_PSCINT 47
141#define IRQ_DM646X_GPIO0 48
142#define IRQ_DM646X_GPIO1 49
143#define IRQ_DM646X_GPIO2 50
144#define IRQ_DM646X_GPIO3 51
145#define IRQ_DM646X_GPIO4 52
146#define IRQ_DM646X_GPIO5 53
147#define IRQ_DM646X_GPIO6 54
148#define IRQ_DM646X_GPIO7 55
149#define IRQ_DM646X_GPIOBNK0 56
150#define IRQ_DM646X_GPIOBNK1 57
151#define IRQ_DM646X_GPIOBNK2 58
152#define IRQ_DM646X_DDRINT 59
153#define IRQ_DM646X_AEMIFINT 60
154
155/* DaVinci DM355-specific Interrupts */
156#define IRQ_DM355_CCDC_VDINT0 0
157#define IRQ_DM355_CCDC_VDINT1 1
158#define IRQ_DM355_CCDC_VDINT2 2
159#define IRQ_DM355_IPIPE_HST 3
160#define IRQ_DM355_H3AINT 4
161#define IRQ_DM355_IPIPE_SDR 5
162#define IRQ_DM355_IPIPEIFINT 6
163#define IRQ_DM355_OSDINT 7
164#define IRQ_DM355_VENCINT 8
165#define IRQ_DM355_IMCOPINT 11
166#define IRQ_DM355_RTOINT 13
167#define IRQ_DM355_TINT4 13
168#define IRQ_DM355_TINT2_TINT12 13
169#define IRQ_DM355_UARTINT2 14
170#define IRQ_DM355_TINT5 14
171#define IRQ_DM355_TINT2_TINT34 14
172#define IRQ_DM355_TINT6 15
173#define IRQ_DM355_TINT3_TINT12 15
174#define IRQ_DM355_SPINT1_0 17
175#define IRQ_DM355_SPINT1_1 18
176#define IRQ_DM355_SPINT2_0 19
177#define IRQ_DM355_SPINT2_1 21
178#define IRQ_DM355_TINT7 22
179#define IRQ_DM355_TINT3_TINT34 22
180#define IRQ_DM355_SDIOINT0 23
181#define IRQ_DM355_MMCINT0 26
182#define IRQ_DM355_MSINT 26
183#define IRQ_DM355_MMCINT1 27
184#define IRQ_DM355_PWMINT3 28
185#define IRQ_DM355_SDIOINT1 31
186#define IRQ_DM355_SPINT0_0 42
187#define IRQ_DM355_SPINT0_1 43
188#define IRQ_DM355_GPIO0 44
189#define IRQ_DM355_GPIO1 45
190#define IRQ_DM355_GPIO2 46
191#define IRQ_DM355_GPIO3 47
192#define IRQ_DM355_GPIO4 48
193#define IRQ_DM355_GPIO5 49
194#define IRQ_DM355_GPIO6 50
195#define IRQ_DM355_GPIO7 51
196#define IRQ_DM355_GPIO8 52
197#define IRQ_DM355_GPIO9 53
198#define IRQ_DM355_GPIOBNK0 54
199#define IRQ_DM355_GPIOBNK1 55
200#define IRQ_DM355_GPIOBNK2 56
201#define IRQ_DM355_GPIOBNK3 57
202#define IRQ_DM355_GPIOBNK4 58
203#define IRQ_DM355_GPIOBNK5 59
204#define IRQ_DM355_GPIOBNK6 60
205
105#endif /* __ASM_ARCH_IRQS_H */ 206#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804d..bae22cb3e27b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1,55 +1,183 @@
1/* 1/*
2 * DaVinci pin multiplexing defines 2 * Table of the DAVINCI register configurations for the PINMUX combinations
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#ifndef __ASM_ARCH_MUX_H 18
12#define __ASM_ARCH_MUX_H 19#ifndef __INC_MACH_MUX_H
13 20#define __INC_MACH_MUX_H
14#define DAVINCI_MUX_AEAW0 0 21
15#define DAVINCI_MUX_AEAW1 1 22/* System module registers */
16#define DAVINCI_MUX_AEAW2 2 23#define PINMUX0 0x00
17#define DAVINCI_MUX_AEAW3 3 24#define PINMUX1 0x04
18#define DAVINCI_MUX_AEAW4 4 25/* dm355 only */
19#define DAVINCI_MUX_AECS4 10 26#define PINMUX2 0x08
20#define DAVINCI_MUX_AECS5 11 27#define PINMUX3 0x0c
21#define DAVINCI_MUX_VLYNQWD0 12 28#define PINMUX4 0x10
22#define DAVINCI_MUX_VLYNQWD1 13 29#define INTMUX 0x18
23#define DAVINCI_MUX_VLSCREN 14 30#define EVTMUX 0x1c
24#define DAVINCI_MUX_VLYNQEN 15 31
25#define DAVINCI_MUX_HDIREN 16 32struct mux_config {
26#define DAVINCI_MUX_ATAEN 17 33 const char *name;
27#define DAVINCI_MUX_RGB666 22 34 const char *mux_reg_name;
28#define DAVINCI_MUX_RGB888 23 35 const unsigned char mux_reg;
29#define DAVINCI_MUX_LOEEN 24 36 const unsigned char mask_offset;
30#define DAVINCI_MUX_LFLDEN 25 37 const unsigned char mask;
31#define DAVINCI_MUX_CWEN 26 38 const unsigned char mode;
32#define DAVINCI_MUX_CFLDEN 27 39 bool debug;
33#define DAVINCI_MUX_HPIEN 29 40};
34#define DAVINCI_MUX_1394EN 30 41
35#define DAVINCI_MUX_EMACEN 31 42enum davinci_dm644x_index {
36 43 /* ATA and HDDIR functions */
37#define DAVINCI_MUX_LEVEL2 32 44 DM644X_HDIREN,
38#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) 45 DM644X_ATAEN,
39#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) 46 DM644X_ATAEN_DISABLE,
40#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) 47
41#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) 48 /* HPI functions */
42#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) 49 DM644X_HPIEN_DISABLE,
43#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) 50
44#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) 51 /* AEAW functions */
45#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) 52 DM644X_AEAW,
46#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) 53
47#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) 54 /* Memory Stick */
48#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) 55 DM644X_MSTK,
49#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) 56
50#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) 57 /* I2C */
51#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) 58 DM644X_I2C,
52 59
53extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); 60 /* ASP function */
54 61 DM644X_MCBSP,
55#endif /* __ASM_ARCH_MUX_H */ 62
63 /* UART1 */
64 DM644X_UART1,
65
66 /* UART2 */
67 DM644X_UART2,
68
69 /* PWM0 */
70 DM644X_PWM0,
71
72 /* PWM1 */
73 DM644X_PWM1,
74
75 /* PWM2 */
76 DM644X_PWM2,
77
78 /* VLYNQ function */
79 DM644X_VLYNQEN,
80 DM644X_VLSCREN,
81 DM644X_VLYNQWD,
82
83 /* EMAC and MDIO function */
84 DM644X_EMACEN,
85
86 /* GPIO3V[0:16] pins */
87 DM644X_GPIO3V,
88
89 /* GPIO pins */
90 DM644X_GPIO0,
91 DM644X_GPIO3,
92 DM644X_GPIO43_44,
93 DM644X_GPIO46_47,
94
95 /* VPBE */
96 DM644X_RGB666,
97
98 /* LCD */
99 DM644X_LOEEN,
100 DM644X_LFLDEN,
101};
102
103enum davinci_dm646x_index {
104 /* ATA function */
105 DM646X_ATAEN,
106
107 /* AUDIO Clock */
108 DM646X_AUDCK1,
109 DM646X_AUDCK0,
110
111 /* CRGEN Control */
112 DM646X_CRGMUX,
113
114 /* VPIF Control */
115 DM646X_STSOMUX_DISABLE,
116 DM646X_STSIMUX_DISABLE,
117 DM646X_PTSOMUX_DISABLE,
118 DM646X_PTSIMUX_DISABLE,
119
120 /* TSIF Control */
121 DM646X_STSOMUX,
122 DM646X_STSIMUX,
123 DM646X_PTSOMUX_PARALLEL,
124 DM646X_PTSIMUX_PARALLEL,
125 DM646X_PTSOMUX_SERIAL,
126 DM646X_PTSIMUX_SERIAL,
127};
128
129enum davinci_dm355_index {
130 /* MMC/SD 0 */
131 DM355_MMCSD0,
132
133 /* MMC/SD 1 */
134 DM355_SD1_CLK,
135 DM355_SD1_CMD,
136 DM355_SD1_DATA3,
137 DM355_SD1_DATA2,
138 DM355_SD1_DATA1,
139 DM355_SD1_DATA0,
140
141 /* I2C */
142 DM355_I2C_SDA,
143 DM355_I2C_SCL,
144
145 /* ASP0 function */
146 DM355_MCBSP0_BDX,
147 DM355_MCBSP0_X,
148 DM355_MCBSP0_BFSX,
149 DM355_MCBSP0_BDR,
150 DM355_MCBSP0_R,
151 DM355_MCBSP0_BFSR,
152
153 /* SPI0 */
154 DM355_SPI0_SDI,
155 DM355_SPI0_SDENA0,
156 DM355_SPI0_SDENA1,
157
158 /* IRQ muxing */
159 DM355_INT_EDMA_CC,
160 DM355_INT_EDMA_TC0_ERR,
161 DM355_INT_EDMA_TC1_ERR,
162
163 /* EDMA event muxing */
164 DM355_EVT8_ASP1_TX,
165 DM355_EVT9_ASP1_RX,
166 DM355_EVT26_MMC0_RX,
167};
168
169#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif
182
183#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
new file mode 100644
index 000000000000..aa482841270b
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -0,0 +1,80 @@
1/*
2 * mach-davinci/nand.h
3 *
4 * Copyright © 2006 Texas Instruments.
5 *
6 * Ported to 2.6.23 Copyright © 2008 by
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
10 *
11 * --------------------------------------------------------------------------
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ARCH_ARM_DAVINCI_NAND_H
29#define __ARCH_ARM_DAVINCI_NAND_H
30
31#include <linux/mtd/nand.h>
32
33#define NRCSR_OFFSET 0x00
34#define AWCCR_OFFSET 0x04
35#define A1CR_OFFSET 0x10
36#define NANDFCR_OFFSET 0x60
37#define NANDFSR_OFFSET 0x64
38#define NANDF1ECC_OFFSET 0x70
39
40/* 4-bit ECC syndrome registers */
41#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
42#define NAND_4BIT_ECC1_OFFSET 0xc0
43#define NAND_4BIT_ECC2_OFFSET 0xc4
44#define NAND_4BIT_ECC3_OFFSET 0xc8
45#define NAND_4BIT_ECC4_OFFSET 0xcc
46#define NAND_ERR_ADD1_OFFSET 0xd0
47#define NAND_ERR_ADD2_OFFSET 0xd4
48#define NAND_ERR_ERRVAL1_OFFSET 0xd8
49#define NAND_ERR_ERRVAL2_OFFSET 0xdc
50
51/* NOTE: boards don't need to use these address bits
52 * for ALE/CLE unless they support booting from NAND.
53 * They're used unless platform data overrides them.
54 */
55#define MASK_ALE 0x08
56#define MASK_CLE 0x10
57
58struct davinci_nand_pdata { /* platform_data */
59 uint32_t mask_ale;
60 uint32_t mask_cle;
61
62 /* for packages using two chipselects */
63 uint32_t mask_chipsel;
64
65 /* board's default static partition info */
66 struct mtd_partition *parts;
67 unsigned nr_parts;
68
69 /* none == NAND_ECC_NONE (strongly *not* advised!!)
70 * soft == NAND_ECC_SOFT
71 * 1-bit == NAND_ECC_HW
72 * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips)
73 */
74 nand_ecc_modes_t ecc_mode;
75
76 /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
77 unsigned options;
78};
79
80#endif /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..55a90d419fac 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -38,8 +38,6 @@
38#define DAVINCI_LPSC_TPTC1 4 38#define DAVINCI_LPSC_TPTC1 4
39#define DAVINCI_LPSC_EMAC 5 39#define DAVINCI_LPSC_EMAC 5
40#define DAVINCI_LPSC_EMAC_WRAPPER 6 40#define DAVINCI_LPSC_EMAC_WRAPPER 6
41#define DAVINCI_LPSC_MDIO 7
42#define DAVINCI_LPSC_IEEE1394 8
43#define DAVINCI_LPSC_USB 9 41#define DAVINCI_LPSC_USB 9
44#define DAVINCI_LPSC_ATA 10 42#define DAVINCI_LPSC_ATA 10
45#define DAVINCI_LPSC_VLYNQ 11 43#define DAVINCI_LPSC_VLYNQ 11
@@ -47,7 +45,6 @@
47#define DAVINCI_LPSC_DDR_EMIF 13 45#define DAVINCI_LPSC_DDR_EMIF 13
48#define DAVINCI_LPSC_AEMIF 14 46#define DAVINCI_LPSC_AEMIF 14
49#define DAVINCI_LPSC_MMC_SD 15 47#define DAVINCI_LPSC_MMC_SD 15
50#define DAVINCI_LPSC_MEMSTICK 16
51#define DAVINCI_LPSC_McBSP 17 48#define DAVINCI_LPSC_McBSP 17
52#define DAVINCI_LPSC_I2C 18 49#define DAVINCI_LPSC_I2C 18
53#define DAVINCI_LPSC_UART0 19 50#define DAVINCI_LPSC_UART0 19
@@ -73,4 +70,54 @@
73#define DAVINCI_LPSC_GEM 39 70#define DAVINCI_LPSC_GEM 39
74#define DAVINCI_LPSC_IMCOP 40 71#define DAVINCI_LPSC_IMCOP 40
75 72
73#define DM355_LPSC_TIMER3 5
74#define DM355_LPSC_SPI1 6
75#define DM355_LPSC_MMC_SD1 7
76#define DM355_LPSC_McBSP1 8
77#define DM355_LPSC_PWM3 10
78#define DM355_LPSC_SPI2 11
79#define DM355_LPSC_RTO 12
80#define DM355_LPSC_VPSS_DAC 41
81
82/*
83 * LPSC Assignments
84 */
85#define DM646X_LPSC_ARM 0
86#define DM646X_LPSC_C64X_CPU 1
87#define DM646X_LPSC_HDVICP0 2
88#define DM646X_LPSC_HDVICP1 3
89#define DM646X_LPSC_TPCC 4
90#define DM646X_LPSC_TPTC0 5
91#define DM646X_LPSC_TPTC1 6
92#define DM646X_LPSC_TPTC2 7
93#define DM646X_LPSC_TPTC3 8
94#define DM646X_LPSC_PCI 13
95#define DM646X_LPSC_EMAC 14
96#define DM646X_LPSC_VDCE 15
97#define DM646X_LPSC_VPSSMSTR 16
98#define DM646X_LPSC_VPSSSLV 17
99#define DM646X_LPSC_TSIF0 18
100#define DM646X_LPSC_TSIF1 19
101#define DM646X_LPSC_DDR_EMIF 20
102#define DM646X_LPSC_AEMIF 21
103#define DM646X_LPSC_McASP0 22
104#define DM646X_LPSC_McASP1 23
105#define DM646X_LPSC_CRGEN0 24
106#define DM646X_LPSC_CRGEN1 25
107#define DM646X_LPSC_UART0 26
108#define DM646X_LPSC_UART1 27
109#define DM646X_LPSC_UART2 28
110#define DM646X_LPSC_PWM0 29
111#define DM646X_LPSC_PWM1 30
112#define DM646X_LPSC_I2C 31
113#define DM646X_LPSC_SPI 32
114#define DM646X_LPSC_GPIO 33
115#define DM646X_LPSC_TIMER0 34
116#define DM646X_LPSC_TIMER1 35
117#define DM646X_LPSC_ARM_INTC 45
118
119extern int davinci_psc_is_clk_active(unsigned int id);
120extern void davinci_psc_config(unsigned int domain, unsigned int id,
121 char enable);
122
76#endif /* __ASM_ARCH_PSC_H */ 123#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index fb8cb229bfd2..632847d74a1c 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,8 +13,23 @@
13 13
14#include <mach/io.h> 14#include <mach/io.h>
15 15
16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22
23/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c
25#define UART_DM646X_SCR 0x10
26#define UART_DM646X_SCR_TX_WATERMARK 0x08
27
28struct davinci_uart_config {
29 /* Bit field of UARTs present; bit 0 --> UART1 */
30 unsigned int enabled_uarts;
31};
32
33extern void davinci_serial_init(struct davinci_uart_config *);
19 34
20#endif /* __ASM_ARCH_SERIAL_H */ 35#endif /* __ASM_ARCH_SERIAL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 07:14:39 -0500