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-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h148
2 files changed, 74 insertions, 76 deletions
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 7a27f3f13913..2a00fe5ac253 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -15,7 +15,6 @@
15#include <mach/asp.h> 15#include <mach/asp.h>
16#include <linux/i2c.h> 16#include <linux/i2c.h>
17#include <linux/videodev2.h> 17#include <linux/videodev2.h>
18#include <linux/clk.h>
19#include <linux/davinci_emac.h> 18#include <linux/davinci_emac.h>
20 19
21#define DM646X_EMAC_BASE (0x01C80000) 20#define DM646X_EMAC_BASE (0x01C80000)
@@ -31,7 +30,6 @@
31void __init dm646x_init(void); 30void __init dm646x_init(void);
32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 31void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk);
35int __init dm646x_init_edma(struct edma_rsv_info *rsv); 33int __init dm646x_init_edma(struct edma_rsv_info *rsv);
36 34
37void dm646x_video_init(void); 35void dm646x_video_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index a47e6f29206e..1110fdd77ba4 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -30,47 +30,47 @@
30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
31 31
32/* Power and Sleep Controller (PSC) Domains */ 32/* Power and Sleep Controller (PSC) Domains */
33#define DAVINCI_GPSC_ARMDOMAIN 0 33#define DAVINCI_GPSC_ARMDOMAIN 0
34#define DAVINCI_GPSC_DSPDOMAIN 1 34#define DAVINCI_GPSC_DSPDOMAIN 1
35 35
36#define DAVINCI_LPSC_VPSSMSTR 0 36#define DAVINCI_LPSC_VPSSMSTR 0
37#define DAVINCI_LPSC_VPSSSLV 1 37#define DAVINCI_LPSC_VPSSSLV 1
38#define DAVINCI_LPSC_TPCC 2 38#define DAVINCI_LPSC_TPCC 2
39#define DAVINCI_LPSC_TPTC0 3 39#define DAVINCI_LPSC_TPTC0 3
40#define DAVINCI_LPSC_TPTC1 4 40#define DAVINCI_LPSC_TPTC1 4
41#define DAVINCI_LPSC_EMAC 5 41#define DAVINCI_LPSC_EMAC 5
42#define DAVINCI_LPSC_EMAC_WRAPPER 6 42#define DAVINCI_LPSC_EMAC_WRAPPER 6
43#define DAVINCI_LPSC_USB 9 43#define DAVINCI_LPSC_USB 9
44#define DAVINCI_LPSC_ATA 10 44#define DAVINCI_LPSC_ATA 10
45#define DAVINCI_LPSC_VLYNQ 11 45#define DAVINCI_LPSC_VLYNQ 11
46#define DAVINCI_LPSC_UHPI 12 46#define DAVINCI_LPSC_UHPI 12
47#define DAVINCI_LPSC_DDR_EMIF 13 47#define DAVINCI_LPSC_DDR_EMIF 13
48#define DAVINCI_LPSC_AEMIF 14 48#define DAVINCI_LPSC_AEMIF 14
49#define DAVINCI_LPSC_MMC_SD 15 49#define DAVINCI_LPSC_MMC_SD 15
50#define DAVINCI_LPSC_McBSP 17 50#define DAVINCI_LPSC_McBSP 17
51#define DAVINCI_LPSC_I2C 18 51#define DAVINCI_LPSC_I2C 18
52#define DAVINCI_LPSC_UART0 19 52#define DAVINCI_LPSC_UART0 19
53#define DAVINCI_LPSC_UART1 20 53#define DAVINCI_LPSC_UART1 20
54#define DAVINCI_LPSC_UART2 21 54#define DAVINCI_LPSC_UART2 21
55#define DAVINCI_LPSC_SPI 22 55#define DAVINCI_LPSC_SPI 22
56#define DAVINCI_LPSC_PWM0 23 56#define DAVINCI_LPSC_PWM0 23
57#define DAVINCI_LPSC_PWM1 24 57#define DAVINCI_LPSC_PWM1 24
58#define DAVINCI_LPSC_PWM2 25 58#define DAVINCI_LPSC_PWM2 25
59#define DAVINCI_LPSC_GPIO 26 59#define DAVINCI_LPSC_GPIO 26
60#define DAVINCI_LPSC_TIMER0 27 60#define DAVINCI_LPSC_TIMER0 27
61#define DAVINCI_LPSC_TIMER1 28 61#define DAVINCI_LPSC_TIMER1 28
62#define DAVINCI_LPSC_TIMER2 29 62#define DAVINCI_LPSC_TIMER2 29
63#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 63#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
64#define DAVINCI_LPSC_ARM 31 64#define DAVINCI_LPSC_ARM 31
65#define DAVINCI_LPSC_SCR2 32 65#define DAVINCI_LPSC_SCR2 32
66#define DAVINCI_LPSC_SCR3 33 66#define DAVINCI_LPSC_SCR3 33
67#define DAVINCI_LPSC_SCR4 34 67#define DAVINCI_LPSC_SCR4 34
68#define DAVINCI_LPSC_CROSSBAR 35 68#define DAVINCI_LPSC_CROSSBAR 35
69#define DAVINCI_LPSC_CFG27 36 69#define DAVINCI_LPSC_CFG27 36
70#define DAVINCI_LPSC_CFG3 37 70#define DAVINCI_LPSC_CFG3 37
71#define DAVINCI_LPSC_CFG5 38 71#define DAVINCI_LPSC_CFG5 38
72#define DAVINCI_LPSC_GEM 39 72#define DAVINCI_LPSC_GEM 39
73#define DAVINCI_LPSC_IMCOP 40 73#define DAVINCI_LPSC_IMCOP 40
74 74
75#define DM355_LPSC_TIMER3 5 75#define DM355_LPSC_TIMER3 5
76#define DM355_LPSC_SPI1 6 76#define DM355_LPSC_SPI1 6
@@ -102,39 +102,39 @@
102/* 102/*
103 * LPSC Assignments 103 * LPSC Assignments
104 */ 104 */
105#define DM646X_LPSC_ARM 0 105#define DM646X_LPSC_ARM 0
106#define DM646X_LPSC_C64X_CPU 1 106#define DM646X_LPSC_C64X_CPU 1
107#define DM646X_LPSC_HDVICP0 2 107#define DM646X_LPSC_HDVICP0 2
108#define DM646X_LPSC_HDVICP1 3 108#define DM646X_LPSC_HDVICP1 3
109#define DM646X_LPSC_TPCC 4 109#define DM646X_LPSC_TPCC 4
110#define DM646X_LPSC_TPTC0 5 110#define DM646X_LPSC_TPTC0 5
111#define DM646X_LPSC_TPTC1 6 111#define DM646X_LPSC_TPTC1 6
112#define DM646X_LPSC_TPTC2 7 112#define DM646X_LPSC_TPTC2 7
113#define DM646X_LPSC_TPTC3 8 113#define DM646X_LPSC_TPTC3 8
114#define DM646X_LPSC_PCI 13 114#define DM646X_LPSC_PCI 13
115#define DM646X_LPSC_EMAC 14 115#define DM646X_LPSC_EMAC 14
116#define DM646X_LPSC_VDCE 15 116#define DM646X_LPSC_VDCE 15
117#define DM646X_LPSC_VPSSMSTR 16 117#define DM646X_LPSC_VPSSMSTR 16
118#define DM646X_LPSC_VPSSSLV 17 118#define DM646X_LPSC_VPSSSLV 17
119#define DM646X_LPSC_TSIF0 18 119#define DM646X_LPSC_TSIF0 18
120#define DM646X_LPSC_TSIF1 19 120#define DM646X_LPSC_TSIF1 19
121#define DM646X_LPSC_DDR_EMIF 20 121#define DM646X_LPSC_DDR_EMIF 20
122#define DM646X_LPSC_AEMIF 21 122#define DM646X_LPSC_AEMIF 21
123#define DM646X_LPSC_McASP0 22 123#define DM646X_LPSC_McASP0 22
124#define DM646X_LPSC_McASP1 23 124#define DM646X_LPSC_McASP1 23
125#define DM646X_LPSC_CRGEN0 24 125#define DM646X_LPSC_CRGEN0 24
126#define DM646X_LPSC_CRGEN1 25 126#define DM646X_LPSC_CRGEN1 25
127#define DM646X_LPSC_UART0 26 127#define DM646X_LPSC_UART0 26
128#define DM646X_LPSC_UART1 27 128#define DM646X_LPSC_UART1 27
129#define DM646X_LPSC_UART2 28 129#define DM646X_LPSC_UART2 28
130#define DM646X_LPSC_PWM0 29 130#define DM646X_LPSC_PWM0 29
131#define DM646X_LPSC_PWM1 30 131#define DM646X_LPSC_PWM1 30
132#define DM646X_LPSC_I2C 31 132#define DM646X_LPSC_I2C 31
133#define DM646X_LPSC_SPI 32 133#define DM646X_LPSC_SPI 32
134#define DM646X_LPSC_GPIO 33 134#define DM646X_LPSC_GPIO 33
135#define DM646X_LPSC_TIMER0 34 135#define DM646X_LPSC_TIMER0 34
136#define DM646X_LPSC_TIMER1 35 136#define DM646X_LPSC_TIMER1 35
137#define DM646X_LPSC_ARM_INTC 45 137#define DM646X_LPSC_ARM_INTC 45
138 138
139/* PSC0 defines */ 139/* PSC0 defines */
140#define DA8XX_LPSC0_TPCC 0 140#define DA8XX_LPSC0_TPCC 0
@@ -243,7 +243,7 @@
243#define PSC_STATE_DISABLE 2 243#define PSC_STATE_DISABLE 2
244#define PSC_STATE_ENABLE 3 244#define PSC_STATE_ENABLE 3
245 245
246#define MDSTAT_STATE_MASK 0x1f 246#define MDSTAT_STATE_MASK 0x1f
247 247
248#ifndef __ASSEMBLER__ 248#ifndef __ASSEMBLER__
249 249