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-rw-r--r--arch/arm/mach-davinci/include/mach/board-dm6446evm.h20
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h55
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h57
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S31
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h22
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/emac.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S25
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h14
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/mmc.h33
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h16
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/sram.h27
-rw-r--r--arch/arm/mach-davinci/include/mach/time.h35
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h19
21 files changed, 397 insertions, 69 deletions
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
deleted file mode 100644
index 3216f21c1238..000000000000
--- a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * DaVinci DM6446 EVM board specific headers
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or ifndef.
10 */
11
12#ifndef _MACH_DAVINCI_DM6446EVM_H
13#define _MACH_DAVINCI_DM6446EVM_H
14
15#include <linux/types.h>
16
17int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
18int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
19
20#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 191770976250..a1f03b606d8f 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,7 +17,8 @@ struct sys_timer;
17extern struct sys_timer davinci_timer; 17extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void); 19extern void davinci_irq_init(void);
20extern void davinci_map_common_io(void); 20extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type;
21 22
22/* parameters describe VBUS sourcing for host mode */ 23/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec); 24extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -25,4 +26,56 @@ extern void setup_usb(unsigned mA, unsigned potpgt_msec);
25/* parameters describe VBUS sourcing for host mode */ 26/* parameters describe VBUS sourcing for host mode */
26extern void setup_usb(unsigned mA, unsigned potpgt_msec); 27extern void setup_usb(unsigned mA, unsigned potpgt_msec);
27 28
29struct davinci_timer_instance {
30 void __iomem *base;
31 u32 bottom_irq;
32 u32 top_irq;
33 unsigned long cmp_off;
34 unsigned int cmp_irq;
35};
36
37struct davinci_timer_info {
38 struct davinci_timer_instance *timers;
39 unsigned int clockevent_id;
40 unsigned int clocksource_id;
41};
42
43/* SoC specific init support */
44struct davinci_soc_info {
45 struct map_desc *io_desc;
46 unsigned long io_desc_num;
47 u32 cpu_id;
48 u32 jtag_id;
49 void __iomem *jtag_id_base;
50 struct davinci_id *ids;
51 unsigned long ids_num;
52 struct davinci_clk *cpu_clks;
53 void __iomem **psc_bases;
54 unsigned long psc_bases_num;
55 void __iomem *pinmux_base;
56 const struct mux_config *pinmux_pins;
57 unsigned long pinmux_pins_num;
58 void __iomem *intc_base;
59 int intc_type;
60 u8 *intc_irq_prios;
61 unsigned long intc_irq_num;
62 struct davinci_timer_info *timer_info;
63 void __iomem *wdt_base;
64 void __iomem *gpio_base;
65 unsigned gpio_num;
66 unsigned gpio_irq;
67 struct platform_device *serial_dev;
68 struct emac_platform_data *emac_pdata;
69 dma_addr_t sram_dma;
70 unsigned sram_len;
71};
72
73extern struct davinci_soc_info davinci_soc_info;
74
75extern void davinci_common_init(struct davinci_soc_info *soc_info);
76
77/* standard place to map on-chip SRAMs; they *may* support DMA */
78#define SRAM_VIRT 0xfffe0000
79#define SRAM_SIZE SZ_128K
80
28#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ 81#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
new file mode 100644
index 000000000000..c4d27eec8064
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -0,0 +1,57 @@
1/*
2 * TI Common Platform Interrupt Controller (cp_intc) definitions
3 *
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11#ifndef __ASM_HARDWARE_CP_INTC_H
12#define __ASM_HARDWARE_CP_INTC_H
13
14#define CP_INTC_REV 0x00
15#define CP_INTC_CTRL 0x04
16#define CP_INTC_HOST_CTRL 0x0C
17#define CP_INTC_GLOBAL_ENABLE 0x10
18#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
19#define CP_INTC_SYS_STAT_IDX_SET 0x20
20#define CP_INTC_SYS_STAT_IDX_CLR 0x24
21#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
22#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
23#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
24#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
25#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
26#define CP_INTC_PACING_PRESCALE 0x40
27#define CP_INTC_VECTOR_BASE 0x50
28#define CP_INTC_VECTOR_SIZE 0x54
29#define CP_INTC_VECTOR_NULL 0x58
30#define CP_INTC_PRIO_IDX 0x80
31#define CP_INTC_PRIO_VECTOR 0x84
32#define CP_INTC_SECURE_ENABLE 0x90
33#define CP_INTC_SECURE_PRIO_IDX 0x94
34#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
35#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
36#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
37#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
38#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
39#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
40#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
41#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
42#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
43#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
44#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
45#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
46#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
47#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
48#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
49#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
50#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53
54void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
55 u8 *irq_prio);
56
57#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 27cfb1b3a662..d12a5ed2959a 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -16,17 +16,30 @@
16#ifndef _ASM_ARCH_CPU_H 16#ifndef _ASM_ARCH_CPU_H
17#define _ASM_ARCH_CPU_H 17#define _ASM_ARCH_CPU_H
18 18
19extern unsigned int davinci_rev(void); 19#include <mach/common.h>
20 20
21#define IS_DAVINCI_CPU(type, id) \ 21struct davinci_id {
22static inline int is_davinci_dm ##type(void) \ 22 u8 variant; /* JTAG ID bits 31:28 */
23{ \ 23 u16 part_no; /* JTAG ID bits 27:12 */
24 return (davinci_rev() == (id)) ? 1 : 0; \ 24 u16 manufacturer; /* JTAG ID bits 11:1 */
25 u32 cpu_id;
26 char *name;
27};
28
29/* Can use lower 16 bits of cpu id for a variant when required */
30#define DAVINCI_CPU_ID_DM6446 0x64460000
31#define DAVINCI_CPU_ID_DM6467 0x64670000
32#define DAVINCI_CPU_ID_DM355 0x03550000
33
34#define IS_DAVINCI_CPU(type, id) \
35static inline int is_davinci_ ##type(void) \
36{ \
37 return (davinci_soc_info.cpu_id == (id)); \
25} 38}
26 39
27IS_DAVINCI_CPU(644x, 0x6446) 40IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
28IS_DAVINCI_CPU(646x, 0x6467) 41IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
29IS_DAVINCI_CPU(355, 0x355) 42IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
30 43
31#ifdef CONFIG_ARCH_DAVINCI_DM644x 44#ifdef CONFIG_ARCH_DAVINCI_DM644x
32#define cpu_is_davinci_dm644x() is_davinci_dm644x() 45#define cpu_is_davinci_dm644x() is_davinci_dm644x()
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index e6c0f0d5d062..de3fc2182b47 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -9,6 +9,16 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11 11
12/* Modifications
13 * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart
14 * macros, based on debug-8250.S file
15 * but using 32-bit accesses required for
16 * some davinci devices.
17 */
18
19#include <linux/serial_reg.h>
20#define UART_SHIFT 2
21
12 .macro addruart, rx 22 .macro addruart, rx
13 mrc p15, 0, \rx, c1, c0 23 mrc p15, 0, \rx, c1, c0
14 tst \rx, #1 @ MMU enabled? 24 tst \rx, #1 @ MMU enabled?
@@ -17,5 +27,22 @@
17 orr \rx, \rx, #0x00c20000 @ UART 0 27 orr \rx, \rx, #0x00c20000 @ UART 0
18 .endm 28 .endm
19 29
20#define UART_SHIFT 2 30 .macro senduart,rd,rx
21#include <asm/hardware/debug-8250.S> 31 str \rd, [\rx, #UART_TX << UART_SHIFT]
32 .endm
33
34 .macro busyuart,rd,rx
351002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
36 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
37 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
38 bne 1002b
39 .endm
40
41 .macro waituart,rd,rx
42#ifdef FLOW_CONTROL
431001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT]
44 tst \rd, #UART_MSR_CTS
45 beq 1001b
46#endif
47 .endm
48
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
new file mode 100644
index 000000000000..54903b72438e
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -0,0 +1,22 @@
1/*
2 * Chip specific defines for DM355 SoC
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DM355_H
12#define __ASM_ARCH_DM355_H
13
14#include <mach/hardware.h>
15
16struct spi_board_info;
17
18void __init dm355_init(void);
19void dm355_init_spi0(unsigned chipselect_mask,
20 struct spi_board_info *info, unsigned len);
21
22#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 3dcb9f4e58b4..15d42b92a8c9 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -24,6 +24,7 @@
24 24
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/emac.h>
27 28
28#define DM644X_EMAC_BASE (0x01C80000) 29#define DM644X_EMAC_BASE (0x01C80000)
29#define DM644X_EMAC_CNTRL_OFFSET (0x0000) 30#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
new file mode 100644
index 000000000000..1fc764c8646e
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -0,0 +1,26 @@
1/*
2 * Chip specific defines for DM646x SoC
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DM646X_H
12#define __ASM_ARCH_DM646X_H
13
14#include <mach/hardware.h>
15#include <mach/emac.h>
16
17#define DM646X_EMAC_BASE (0x01C80000)
18#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
19#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
20#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
21#define DM646X_EMAC_MDIO_OFFSET (0x4000)
22#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
23
24void __init dm646x_init(void);
25
26#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index f6fc5396dafc..24a379239d7f 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -208,10 +208,6 @@ void edma_clear_event(unsigned channel);
208void edma_pause(unsigned channel); 208void edma_pause(unsigned channel);
209void edma_resume(unsigned channel); 209void edma_resume(unsigned channel);
210 210
211/* UNRELATED TO DMA */
212int davinci_alloc_iram(unsigned size);
213void davinci_free_iram(unsigned addr, unsigned size);
214
215/* platform_data for EDMA driver */ 211/* platform_data for EDMA driver */
216struct edma_soc_info { 212struct edma_soc_info {
217 213
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
new file mode 100644
index 000000000000..beff4fb7c845
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/emac.h
@@ -0,0 +1,36 @@
1/*
2 * TI DaVinci EMAC platform support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef _MACH_DAVINCI_EMAC_H
12#define _MACH_DAVINCI_EMAC_H
13
14#include <linux/if_ether.h>
15#include <linux/memory.h>
16
17struct emac_platform_data {
18 char mac_addr[ETH_ALEN];
19 u32 ctrl_reg_offset;
20 u32 ctrl_mod_reg_offset;
21 u32 ctrl_ram_offset;
22 u32 mdio_reg_offset;
23 u32 ctrl_ram_size;
24 u32 phy_mask;
25 u32 mdio_max_freq;
26 u8 rmii_en;
27 u8 version;
28};
29
30enum {
31 EMAC_VERSION_1, /* DM644x */
32 EMAC_VERSION_2, /* DM646x */
33};
34
35void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
36#endif
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 039b84f933b3..fbdebc7cb409 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -15,17 +15,36 @@
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) 18 ldr \base, =davinci_intc_base
19 ldr \base, [\base]
19 .endm 20 .endm
20 21
21 .macro arch_ret_to_user, tmp1, tmp2 22 .macro arch_ret_to_user, tmp1, tmp2
22 .endm 23 .endm
23 24
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
27 ldr \tmp, =davinci_intc_type
28 ldr \tmp, [\tmp]
29 cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
30 beq 1001f
31#endif
32#if defined(CONFIG_AINTC)
25 ldr \tmp, [\base, #0x14] 33 ldr \tmp, [\base, #0x14]
26 mov \tmp, \tmp, lsr #2 34 movs \tmp, \tmp, lsr #2
27 sub \irqnr, \tmp, #1 35 sub \irqnr, \tmp, #1
28 cmp \tmp, #0 36 b 1002f
37#endif
38#if defined(CONFIG_CP_INTC)
391001: ldr \irqnr, [\base, #0x80] /* get irq number */
40 and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
41 mov \tmp, \irqnr, lsr #3
42 and \tmp, \tmp, #0xfc
43 add \tmp, \tmp, #0x280 /* get the register offset */
44 ldr \irqstat, [\base, \tmp] /* get the intc status */
45 cmp \irqstat, #0x0
46#endif
471002:
29 .endm 48 .endm
30 49
31 .macro irq_prio_table 50 .macro irq_prio_table
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index efe3281364e6..ae0745568316 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -17,6 +17,7 @@
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18 18
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20#include <mach/common.h>
20 21
21#define DAVINCI_GPIO_BASE 0x01C67000 22#define DAVINCI_GPIO_BASE 0x01C67000
22 23
@@ -67,15 +68,16 @@ static inline struct gpio_controller *__iomem
67__gpio_to_controller(unsigned gpio) 68__gpio_to_controller(unsigned gpio)
68{ 69{
69 void *__iomem ptr; 70 void *__iomem ptr;
71 void __iomem *base = davinci_soc_info.gpio_base;
70 72
71 if (gpio < 32 * 1) 73 if (gpio < 32 * 1)
72 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); 74 ptr = base + 0x10;
73 else if (gpio < 32 * 2) 75 else if (gpio < 32 * 2)
74 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); 76 ptr = base + 0x38;
75 else if (gpio < 32 * 3) 77 else if (gpio < 32 * 3)
76 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); 78 ptr = base + 0x60;
77 else if (gpio < 32 * 4) 79 else if (gpio < 32 * 4)
78 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); 80 ptr = base + 0x88;
79 else 81 else
80 ptr = NULL; 82 ptr = NULL;
81 return ptr; 83 return ptr;
@@ -142,13 +144,13 @@ static inline int gpio_to_irq(unsigned gpio)
142{ 144{
143 if (gpio >= DAVINCI_N_GPIO) 145 if (gpio >= DAVINCI_N_GPIO)
144 return -EINVAL; 146 return -EINVAL;
145 return DAVINCI_N_AINTC_IRQ + gpio; 147 return davinci_soc_info.intc_irq_num + gpio;
146} 148}
147 149
148static inline int irq_to_gpio(unsigned irq) 150static inline int irq_to_gpio(unsigned irq)
149{ 151{
150 /* caller guarantees gpio_to_irq() succeeded */ 152 /* caller guarantees gpio_to_irq() succeeded */
151 return irq - DAVINCI_N_AINTC_IRQ; 153 return irq - davinci_soc_info.intc_irq_num;
152} 154}
153 155
154#endif /* __DAVINCI_GPIO_H */ 156#endif /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 18066074c995..bc5d6aaa69a3 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -30,6 +30,9 @@
30/* Base address */ 30/* Base address */
31#define DAVINCI_ARM_INTC_BASE 0x01C48000 31#define DAVINCI_ARM_INTC_BASE 0x01C48000
32 32
33#define DAVINCI_INTC_TYPE_AINTC 0
34#define DAVINCI_INTC_TYPE_CP_INTC 1
35
33/* Interrupt lines */ 36/* Interrupt lines */
34#define IRQ_VDINT0 0 37#define IRQ_VDINT0 0
35#define IRQ_VDINT1 1 38#define IRQ_VDINT1 1
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 86c25c7f3ce3..c712c7cdf38f 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -21,7 +21,6 @@
21 * Definitions 21 * Definitions
22 **************************************************************************/ 22 **************************************************************************/
23#define DAVINCI_DDR_BASE 0x80000000 23#define DAVINCI_DDR_BASE 0x80000000
24#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */
25 24
26#define PHYS_OFFSET DAVINCI_DDR_BASE 25#define PHYS_OFFSET DAVINCI_DDR_BASE
27 26
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
new file mode 100644
index 000000000000..5a85e24f3673
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/mmc.h
@@ -0,0 +1,33 @@
1/*
2 * Board-specific MMC configuration
3 */
4
5#ifndef _DAVINCI_MMC_H
6#define _DAVINCI_MMC_H
7
8#include <linux/types.h>
9#include <linux/mmc/host.h>
10
11struct davinci_mmc_config {
12 /* get_cd()/get_wp() may sleep */
13 int (*get_cd)(int module);
14 int (*get_ro)(int module);
15 /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
16 u8 wires;
17
18 u32 max_freq;
19
20 /* any additional host capabilities: OR'd in to mmc->f_caps */
21 u32 caps;
22
23 /* Version of the MMC/SD controller */
24 u8 version;
25};
26void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
27
28enum {
29 MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
30 MMC_CTLR_VERSION_2, /* DA830 */
31};
32
33#endif
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bae22cb3e27b..27378458542f 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -19,16 +19,6 @@
19#ifndef __INC_MACH_MUX_H 19#ifndef __INC_MACH_MUX_H
20#define __INC_MACH_MUX_H 20#define __INC_MACH_MUX_H
21 21
22/* System module registers */
23#define PINMUX0 0x00
24#define PINMUX1 0x04
25/* dm355 only */
26#define PINMUX2 0x08
27#define PINMUX3 0x0c
28#define PINMUX4 0x10
29#define INTMUX 0x18
30#define EVTMUX 0x1c
31
32struct mux_config { 22struct mux_config {
33 const char *name; 23 const char *name;
34 const char *mux_reg_name; 24 const char *mux_reg_name;
@@ -168,15 +158,9 @@ enum davinci_dm355_index {
168 158
169#ifdef CONFIG_DAVINCI_MUX 159#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */ 160/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg); 161extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else 162#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ 163/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } 164static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif 165#endif
182 166
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 55a90d419fac..ab8a2586d1cc 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -27,6 +27,8 @@
27#ifndef __ASM_ARCH_PSC_H 27#ifndef __ASM_ARCH_PSC_H
28#define __ASM_ARCH_PSC_H 28#define __ASM_ARCH_PSC_H
29 29
30#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
31
30/* Power and Sleep Controller (PSC) Domains */ 32/* Power and Sleep Controller (PSC) Domains */
31#define DAVINCI_GPSC_ARMDOMAIN 0 33#define DAVINCI_GPSC_ARMDOMAIN 0
32#define DAVINCI_GPSC_DSPDOMAIN 1 34#define DAVINCI_GPSC_DSPDOMAIN 1
@@ -116,8 +118,8 @@
116#define DM646X_LPSC_TIMER1 35 118#define DM646X_LPSC_TIMER1 35
117#define DM646X_LPSC_ARM_INTC 45 119#define DM646X_LPSC_ARM_INTC 45
118 120
119extern int davinci_psc_is_clk_active(unsigned int id); 121extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
120extern void davinci_psc_config(unsigned int domain, unsigned int id, 122extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
121 char enable); 123 unsigned int id, char enable);
122 124
123#endif /* __ASM_ARCH_PSC_H */ 125#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 632847d74a1c..794fa5cf93c1 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,8 +18,6 @@
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20 20
21#define DM355_UART2_BASE (IO_PHYS + 0x206000)
22
23/* DaVinci UART register offsets */ 21/* DaVinci UART register offsets */
24#define UART_DAVINCI_PWREMU 0x0c 22#define UART_DAVINCI_PWREMU 0x0c
25#define UART_DM646X_SCR 0x10 23#define UART_DM646X_SCR 0x10
@@ -30,6 +28,6 @@ struct davinci_uart_config {
30 unsigned int enabled_uarts; 28 unsigned int enabled_uarts;
31}; 29};
32 30
33extern void davinci_serial_init(struct davinci_uart_config *); 31extern int davinci_serial_init(struct davinci_uart_config *);
34 32
35#endif /* __ASM_ARCH_SERIAL_H */ 33#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
new file mode 100644
index 000000000000..111f7cc71e07
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -0,0 +1,27 @@
1/*
2 * mach/sram.h - DaVinci simple SRAM allocator
3 *
4 * Copyright (C) 2009 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __MACH_SRAM_H
11#define __MACH_SRAM_H
12
13/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14#define SRAM_GRANULARITY 512
15
16/*
17 * SRAM allocations return a CPU virtual address, or NULL on error.
18 * If a DMA address is requested and the SRAM supports DMA, its
19 * mapped address is also returned.
20 *
21 * Errors include SRAM memory not being available, and requesting
22 * DMA mapped SRAM on systems which don't allow that.
23 */
24extern void *sram_alloc(size_t len, dma_addr_t *dma);
25extern void sram_free(void *addr, size_t len);
26
27#endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 000000000000..1c971d8d8ba8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,35 @@
1/*
2 * Local header file for DaVinci time code.
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
12#define __ARCH_ARM_MACH_DAVINCI_TIME_H
13
14#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
15#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
16#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
17
18enum {
19 T0_BOT,
20 T0_TOP,
21 T1_BOT,
22 T1_TOP,
23 NUM_TIMERS
24};
25
26#define IS_TIMER1(id) (id & 0x2)
27#define IS_TIMER0(id) (!IS_TIMER1(id))
28#define IS_TIMER_TOP(id) ((id & 0x1))
29#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
30
31#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
32
33extern struct davinci_timer_instance davinci_timer_instance[];
34
35#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 8c165def37b6..1e27475f9a23 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -13,11 +13,24 @@
13#include <linux/serial_reg.h> 13#include <linux/serial_reg.h>
14#include <mach/serial.h> 14#include <mach/serial.h>
15 15
16#include <asm/mach-types.h>
17
18extern unsigned int __machine_arch_type;
19
20static u32 *uart;
21
22static u32 *get_uart_base(void)
23{
24 /* Add logic here for new platforms, using __macine_arch_type */
25 return (u32 *)DAVINCI_UART0_BASE;
26}
27
16/* PORT_16C550A, in polled non-fifo mode */ 28/* PORT_16C550A, in polled non-fifo mode */
17 29
18static void putc(char c) 30static void putc(char c)
19{ 31{
20 volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 32 if (!uart)
33 uart = get_uart_base();
21 34
22 while (!(uart[UART_LSR] & UART_LSR_THRE)) 35 while (!(uart[UART_LSR] & UART_LSR_THRE))
23 barrier(); 36 barrier();
@@ -26,7 +39,9 @@ static void putc(char c)
26 39
27static inline void flush(void) 40static inline void flush(void)
28{ 41{
29 volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; 42 if (!uart)
43 uart = get_uart_base();
44
30 while (!(uart[UART_LSR] & UART_LSR_THRE)) 45 while (!(uart[UART_LSR] & UART_LSR_THRE))
31 barrier(); 46 barrier();
32} 47}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 07:30:14 -0500