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-rw-r--r--arch/arm/mach-davinci/include/mach/common.h32
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h72
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h97
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h290
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h55
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h5
14 files changed, 527 insertions, 82 deletions
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 50a955f05ef9..a57cba21e21e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
12#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H 12#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
13#define __ARCH_ARM_MACH_DAVINCI_COMMON_H 13#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
14 14
15#include <linux/compiler.h>
16#include <linux/types.h>
17
15struct sys_timer; 18struct sys_timer;
16 19
17extern struct sys_timer davinci_timer; 20extern struct sys_timer davinci_timer;
@@ -21,7 +24,7 @@ extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type; 24extern int davinci_intc_type;
22 25
23struct davinci_timer_instance { 26struct davinci_timer_instance {
24 void __iomem *base; 27 u32 base;
25 u32 bottom_irq; 28 u32 bottom_irq;
26 u32 top_irq; 29 u32 top_irq;
27 unsigned long cmp_off; 30 unsigned long cmp_off;
@@ -34,39 +37,54 @@ struct davinci_timer_info {
34 unsigned int clocksource_id; 37 unsigned int clocksource_id;
35}; 38};
36 39
37/* SoC specific init support */ 40struct davinci_gpio_controller;
41
42/*
43 * SoC info passed into common davinci modules.
44 *
45 * Base addresses in this structure should be physical and not virtual.
46 * Modules that take such base addresses, should internally ioremap() them to
47 * use.
48 */
38struct davinci_soc_info { 49struct davinci_soc_info {
39 struct map_desc *io_desc; 50 struct map_desc *io_desc;
40 unsigned long io_desc_num; 51 unsigned long io_desc_num;
41 u32 cpu_id; 52 u32 cpu_id;
42 u32 jtag_id; 53 u32 jtag_id;
43 void __iomem *jtag_id_base; 54 u32 jtag_id_reg;
44 struct davinci_id *ids; 55 struct davinci_id *ids;
45 unsigned long ids_num; 56 unsigned long ids_num;
46 struct clk_lookup *cpu_clks; 57 struct clk_lookup *cpu_clks;
47 void __iomem **psc_bases; 58 u32 *psc_bases;
48 unsigned long psc_bases_num; 59 unsigned long psc_bases_num;
49 void __iomem *pinmux_base; 60 u32 pinmux_base;
50 const struct mux_config *pinmux_pins; 61 const struct mux_config *pinmux_pins;
51 unsigned long pinmux_pins_num; 62 unsigned long pinmux_pins_num;
52 void __iomem *intc_base; 63 u32 intc_base;
53 int intc_type; 64 int intc_type;
54 u8 *intc_irq_prios; 65 u8 *intc_irq_prios;
55 unsigned long intc_irq_num; 66 unsigned long intc_irq_num;
67 u32 *intc_host_map;
56 struct davinci_timer_info *timer_info; 68 struct davinci_timer_info *timer_info;
57 void __iomem *gpio_base; 69 int gpio_type;
70 u32 gpio_base;
58 unsigned gpio_num; 71 unsigned gpio_num;
59 unsigned gpio_irq; 72 unsigned gpio_irq;
60 unsigned gpio_unbanked; 73 unsigned gpio_unbanked;
74 struct davinci_gpio_controller *gpio_ctlrs;
75 int gpio_ctlrs_num;
61 struct platform_device *serial_dev; 76 struct platform_device *serial_dev;
62 struct emac_platform_data *emac_pdata; 77 struct emac_platform_data *emac_pdata;
63 dma_addr_t sram_dma; 78 dma_addr_t sram_dma;
64 unsigned sram_len; 79 unsigned sram_len;
80 struct platform_device *reset_device;
81 void (*reset)(struct platform_device *);
65}; 82};
66 83
67extern struct davinci_soc_info davinci_soc_info; 84extern struct davinci_soc_info davinci_soc_info;
68 85
69extern void davinci_common_init(struct davinci_soc_info *soc_info); 86extern void davinci_common_init(struct davinci_soc_info *soc_info);
87extern void davinci_init_ide(void);
70 88
71/* standard place to map on-chip SRAMs; they *may* support DMA */ 89/* standard place to map on-chip SRAMs; they *may* support DMA */
72#define SRAM_VIRT 0xfffe0000 90#define SRAM_VIRT 0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27eec8064..4e8190eed673 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,6 @@
51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) 51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) 52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53 53
54void __init cp_intc_init(void __iomem *base, unsigned short num_irq, 54void __init cp_intc_init(void);
55 u8 *irq_prio);
56 55
57#endif /* __ASM_HARDWARE_CP_INTC_H */ 56#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 189b1ff13642..cea6b8972043 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,6 +33,7 @@ struct davinci_id {
33#define DAVINCI_CPU_ID_DM365 0x03650000 33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000 34#define DAVINCI_CPU_ID_DA830 0x08300000
35#define DAVINCI_CPU_ID_DA850 0x08500000 35#define DAVINCI_CPU_ID_DA850 0x08500000
36#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
36 37
37#define IS_DAVINCI_CPU(type, id) \ 38#define IS_DAVINCI_CPU(type, id) \
38static inline int is_davinci_ ##type(void) \ 39static inline int is_davinci_ ##type(void) \
@@ -46,6 +47,7 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
46IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) 47IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
47IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) 48IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
48IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) 49IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
50IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
49 51
50#ifdef CONFIG_ARCH_DAVINCI_DM644x 52#ifdef CONFIG_ARCH_DAVINCI_DM644x
51#define cpu_is_davinci_dm644x() is_davinci_dm644x() 53#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -83,4 +85,10 @@ IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
83#define cpu_is_davinci_da850() 0 85#define cpu_is_davinci_da850() 0
84#endif 86#endif
85 87
88#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
89#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
90#else
91#define cpu_is_davinci_tnetv107x() 0
92#endif
93
86#endif 94#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 03acfd39042b..1b31a9aa8fba 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,27 +64,6 @@ extern void __iomem *da8xx_syscfg1_base;
64#define DA8XX_DDR2_CTL_BASE 0xb0000000 64#define DA8XX_DDR2_CTL_BASE 0xb0000000
65#define DA8XX_ARM_RAM_BASE 0xffff0000 65#define DA8XX_ARM_RAM_BASE 0xffff0000
66 66
67#define PINMUX0 0x00
68#define PINMUX1 0x04
69#define PINMUX2 0x08
70#define PINMUX3 0x0c
71#define PINMUX4 0x10
72#define PINMUX5 0x14
73#define PINMUX6 0x18
74#define PINMUX7 0x1c
75#define PINMUX8 0x20
76#define PINMUX9 0x24
77#define PINMUX10 0x28
78#define PINMUX11 0x2c
79#define PINMUX12 0x30
80#define PINMUX13 0x34
81#define PINMUX14 0x38
82#define PINMUX15 0x3c
83#define PINMUX16 0x40
84#define PINMUX17 0x44
85#define PINMUX18 0x48
86#define PINMUX19 0x4c
87
88void __init da830_init(void); 67void __init da830_init(void);
89void __init da850_init(void); 68void __init da850_init(void);
90 69
@@ -108,6 +87,8 @@ extern struct emac_platform_data da8xx_emac_pdata;
108extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; 87extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
109extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; 88extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
110 89
90extern struct platform_device da8xx_wdt_device;
91
111extern const short da830_emif25_pins[]; 92extern const short da830_emif25_pins[];
112extern const short da830_spi0_pins[]; 93extern const short da830_spi0_pins[];
113extern const short da830_spi1_pins[]; 94extern const short da830_spi1_pins[];
@@ -146,10 +127,4 @@ extern const short da850_mmcsd0_pins[];
146extern const short da850_nand_pins[]; 127extern const short da850_nand_pins[];
147extern const short da850_nor_pins[]; 128extern const short da850_nor_pins[];
148 129
149#ifdef CONFIG_DAVINCI_MUX
150int da8xx_pinmux_setup(const short pins[]);
151#else
152static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
153#endif
154
155#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ 130#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 85536d8e8336..36dff4a0ce3f 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -15,6 +15,9 @@
15#include <mach/asp.h> 15#include <mach/asp.h>
16#include <media/davinci/vpfe_capture.h> 16#include <media/davinci/vpfe_capture.h>
17 17
18#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
19#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
20
18#define ASP1_TX_EVT_EN 1 21#define ASP1_TX_EVT_EN 1
19#define ASP1_RX_EVT_EN 2 22#define ASP1_RX_EVT_EN 2
20 23
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 3a37b5a6983c..ea5df3b49ec4 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -36,6 +36,10 @@
36#define DAVINCI_DMA_VC_TX 2 36#define DAVINCI_DMA_VC_TX 2
37#define DAVINCI_DMA_VC_RX 3 37#define DAVINCI_DMA_VC_RX 3
38 38
39#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
40#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
41#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
42
39void __init dm365_init(void); 43void __init dm365_init(void);
40void __init dm365_init_asp(struct snd_platform_data *pdata); 44void __init dm365_init_asp(struct snd_platform_data *pdata);
41void __init dm365_init_vc(struct snd_platform_data *pdata); 45void __init dm365_init_vc(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 1a8b09ccc3c8..6fca568a0fd2 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -34,6 +34,12 @@
34#define DM644X_EMAC_MDIO_OFFSET (0x4000) 34#define DM644X_EMAC_MDIO_OFFSET (0x4000)
35#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) 35#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
36 36
37#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
38#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
39#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
40#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
41#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
42
37void __init dm644x_init(void); 43void __init dm644x_init(void);
38void __init dm644x_init_asp(struct snd_platform_data *pdata); 44void __init dm644x_init_asp(struct snd_platform_data *pdata);
39void dm644x_set_vpfe_config(struct vpfe_config *cfg); 45void dm644x_set_vpfe_config(struct vpfe_config *cfg);
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 846da98b619a..add6f794a362 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -25,10 +25,10 @@
25#define DM646X_EMAC_MDIO_OFFSET (0x4000) 25#define DM646X_EMAC_MDIO_OFFSET (0x4000)
26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) 26#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
27 27
28#define DM646X_ATA_REG_BASE (0x01C66000) 28#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
29#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
29 30
30void __init dm646x_init(void); 31void __init dm646x_init(void);
31void __init dm646x_init_ide(void);
32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk); 34void __init dm646x_board_setup_refclk(struct clk *clk);
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef878158..504cc180a60b 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
14#define __DAVINCI_GPIO_H 14#define __DAVINCI_GPIO_H
15 15
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/spinlock.h>
18
17#include <asm-generic/gpio.h> 19#include <asm-generic/gpio.h>
18 20
19#include <mach/irqs.h> 21#include <mach/irqs.h>
@@ -21,6 +23,10 @@
21 23
22#define DAVINCI_GPIO_BASE 0x01C67000 24#define DAVINCI_GPIO_BASE 0x01C67000
23 25
26enum davinci_gpio_type {
27 GPIO_TYPE_DAVINCI = 0,
28};
29
24/* 30/*
25 * basic gpio routines 31 * basic gpio routines
26 * 32 *
@@ -45,17 +51,14 @@
45/* Convert GPIO signal to GPIO pin number */ 51/* Convert GPIO signal to GPIO pin number */
46#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) 52#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
47 53
48struct gpio_controller { 54struct davinci_gpio_controller {
49 u32 dir; 55 struct gpio_chip chip;
50 u32 out_data; 56 int irq_base;
51 u32 set_data; 57 spinlock_t lock;
52 u32 clr_data; 58 void __iomem *regs;
53 u32 in_data; 59 void __iomem *set_data;
54 u32 set_rising; 60 void __iomem *clr_data;
55 u32 clr_rising; 61 void __iomem *in_data;
56 u32 set_falling;
57 u32 clr_falling;
58 u32 intstat;
59}; 62};
60 63
61/* The __gpio_to_controller() and __gpio_mask() functions inline to constants 64/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
@@ -67,25 +70,16 @@ struct gpio_controller {
67 * 70 *
68 * These are NOT part of the cross-platform GPIO interface 71 * These are NOT part of the cross-platform GPIO interface
69 */ 72 */
70static inline struct gpio_controller *__iomem 73static inline struct davinci_gpio_controller *
71__gpio_to_controller(unsigned gpio) 74__gpio_to_controller(unsigned gpio)
72{ 75{
73 void *__iomem ptr; 76 struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
74 void __iomem *base = davinci_soc_info.gpio_base; 77 int index = gpio / 32;
75 78
76 if (gpio < 32 * 1) 79 if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
77 ptr = base + 0x10; 80 return NULL;
78 else if (gpio < 32 * 2) 81
79 ptr = base + 0x38; 82 return ctlrs + index;
80 else if (gpio < 32 * 3)
81 ptr = base + 0x60;
82 else if (gpio < 32 * 4)
83 ptr = base + 0x88;
84 else if (gpio < 32 * 5)
85 ptr = base + 0xb0;
86 else
87 ptr = NULL;
88 return ptr;
89} 83}
90 84
91static inline u32 __gpio_mask(unsigned gpio) 85static inline u32 __gpio_mask(unsigned gpio)
@@ -101,16 +95,16 @@ static inline u32 __gpio_mask(unsigned gpio)
101 */ 95 */
102static inline void gpio_set_value(unsigned gpio, int value) 96static inline void gpio_set_value(unsigned gpio, int value)
103{ 97{
104 if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) { 98 if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) {
105 struct gpio_controller *__iomem g; 99 struct davinci_gpio_controller *ctlr;
106 u32 mask; 100 u32 mask;
107 101
108 g = __gpio_to_controller(gpio); 102 ctlr = __gpio_to_controller(gpio);
109 mask = __gpio_mask(gpio); 103 mask = __gpio_mask(gpio);
110 if (value) 104 if (value)
111 __raw_writel(mask, &g->set_data); 105 __raw_writel(mask, ctlr->set_data);
112 else 106 else
113 __raw_writel(mask, &g->clr_data); 107 __raw_writel(mask, ctlr->clr_data);
114 return; 108 return;
115 } 109 }
116 110
@@ -128,18 +122,18 @@ static inline void gpio_set_value(unsigned gpio, int value)
128 */ 122 */
129static inline int gpio_get_value(unsigned gpio) 123static inline int gpio_get_value(unsigned gpio)
130{ 124{
131 struct gpio_controller *__iomem g; 125 struct davinci_gpio_controller *ctlr;
132 126
133 if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO) 127 if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num)
134 return __gpio_get_value(gpio); 128 return __gpio_get_value(gpio);
135 129
136 g = __gpio_to_controller(gpio); 130 ctlr = __gpio_to_controller(gpio);
137 return __gpio_mask(gpio) & __raw_readl(&g->in_data); 131 return __gpio_mask(gpio) & __raw_readl(ctlr->in_data);
138} 132}
139 133
140static inline int gpio_cansleep(unsigned gpio) 134static inline int gpio_cansleep(unsigned gpio)
141{ 135{
142 if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO) 136 if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num)
143 return 0; 137 return 0;
144 else 138 else
145 return __gpio_cansleep(gpio); 139 return __gpio_cansleep(gpio);
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dc..ec76c7775c2e 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,6 +401,103 @@
401 401
402#define DA850_N_CP_INTC_IRQ 101 402#define DA850_N_CP_INTC_IRQ 101
403 403
404
405/* TNETV107X specific interrupts */
406#define IRQ_TNETV107X_TDM1_TXDMA 0
407#define IRQ_TNETV107X_EXT_INT_0 1
408#define IRQ_TNETV107X_EXT_INT_1 2
409#define IRQ_TNETV107X_GPIO_INT12 3
410#define IRQ_TNETV107X_GPIO_INT13 4
411#define IRQ_TNETV107X_TIMER_0_TINT12 5
412#define IRQ_TNETV107X_TIMER_1_TINT12 6
413#define IRQ_TNETV107X_UART0 7
414#define IRQ_TNETV107X_TDM1_RXDMA 8
415#define IRQ_TNETV107X_MCDMA_INT0 9
416#define IRQ_TNETV107X_MCDMA_INT1 10
417#define IRQ_TNETV107X_TPCC 11
418#define IRQ_TNETV107X_TPCC_INT0 12
419#define IRQ_TNETV107X_TPCC_INT1 13
420#define IRQ_TNETV107X_TPCC_INT2 14
421#define IRQ_TNETV107X_TPCC_INT3 15
422#define IRQ_TNETV107X_TPTC0 16
423#define IRQ_TNETV107X_TPTC1 17
424#define IRQ_TNETV107X_TIMER_0_TINT34 18
425#define IRQ_TNETV107X_ETHSS 19
426#define IRQ_TNETV107X_TIMER_1_TINT34 20
427#define IRQ_TNETV107X_DSP2ARM_INT0 21
428#define IRQ_TNETV107X_DSP2ARM_INT1 22
429#define IRQ_TNETV107X_ARM_NPMUIRQ 23
430#define IRQ_TNETV107X_USB1 24
431#define IRQ_TNETV107X_VLYNQ 25
432#define IRQ_TNETV107X_UART0_DMATX 26
433#define IRQ_TNETV107X_UART0_DMARX 27
434#define IRQ_TNETV107X_TDM1_TXMCSP 28
435#define IRQ_TNETV107X_SSP 29
436#define IRQ_TNETV107X_MCDMA_INT2 30
437#define IRQ_TNETV107X_MCDMA_INT3 31
438#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
439#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
440#define IRQ_TNETV107X_USB0 34
441#define IRQ_TNETV107X_USB_CDMA 35
442#define IRQ_TNETV107X_LCD 36
443#define IRQ_TNETV107X_KEYPAD 37
444#define IRQ_TNETV107X_KEYPAD_FREE 38
445#define IRQ_TNETV107X_RNG 39
446#define IRQ_TNETV107X_PKA 40
447#define IRQ_TNETV107X_TDM0_TXDMA 41
448#define IRQ_TNETV107X_TDM0_RXDMA 42
449#define IRQ_TNETV107X_TDM0_TXMCSP 43
450#define IRQ_TNETV107X_TDM0_RXMCSP 44
451#define IRQ_TNETV107X_TDM1_RXMCSP 45
452#define IRQ_TNETV107X_SDIO1 46
453#define IRQ_TNETV107X_SDIO0 47
454#define IRQ_TNETV107X_TSC 48
455#define IRQ_TNETV107X_TS 49
456#define IRQ_TNETV107X_UART1 50
457#define IRQ_TNETV107X_MBX_LITE 51
458#define IRQ_TNETV107X_GPIO_INT00 52
459#define IRQ_TNETV107X_GPIO_INT01 53
460#define IRQ_TNETV107X_GPIO_INT02 54
461#define IRQ_TNETV107X_GPIO_INT03 55
462#define IRQ_TNETV107X_UART2 56
463#define IRQ_TNETV107X_UART2_DMATX 57
464#define IRQ_TNETV107X_UART2_DMARX 58
465#define IRQ_TNETV107X_IMCOP_IMX 59
466#define IRQ_TNETV107X_IMCOP_VLCD 60
467#define IRQ_TNETV107X_AES 61
468#define IRQ_TNETV107X_DES 62
469#define IRQ_TNETV107X_SHAMD5 63
470#define IRQ_TNETV107X_TPCC_ERR 68
471#define IRQ_TNETV107X_TPCC_PROT 69
472#define IRQ_TNETV107X_TPTC0_ERR 70
473#define IRQ_TNETV107X_TPTC1_ERR 71
474#define IRQ_TNETV107X_UART0_ERR 72
475#define IRQ_TNETV107X_UART1_ERR 73
476#define IRQ_TNETV107X_AEMIF_ERR 74
477#define IRQ_TNETV107X_DDR_ERR 75
478#define IRQ_TNETV107X_WDTARM_INT0 76
479#define IRQ_TNETV107X_MCDMA_ERR 77
480#define IRQ_TNETV107X_GPIO_ERR 78
481#define IRQ_TNETV107X_MPU_ADDR 79
482#define IRQ_TNETV107X_MPU_PROT 80
483#define IRQ_TNETV107X_IOPU_ADDR 81
484#define IRQ_TNETV107X_IOPU_PROT 82
485#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
486#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
487#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
488#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
489#define IRQ_TNETV107X_PLL_UNLOCK 87
490#define IRQ_TNETV107X_WDTDSP_INT0 88
491#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
492#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
493#define IRQ_TNETV107X_PBIST_CPU 91
494#define IRQ_TNETV107X_WDTARM 92
495#define IRQ_TNETV107X_PSC 93
496#define IRQ_TNETV107X_MMC0 94
497#define IRQ_TNETV107X_MMC1 95
498
499#define TNETV107X_N_CP_INTC_IRQ 96
500
404/* da850 currently has the most gpio pins (144) */ 501/* da850 currently has the most gpio pins (144) */
405#define DAVINCI_N_GPIO 144 502#define DAVINCI_N_GPIO 144
406/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ 503/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 2a68c1d8a24b..de11aac76a80 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -194,11 +194,14 @@ enum davinci_dm365_index {
194 DM365_I2C_SCL, 194 DM365_I2C_SCL,
195 195
196 /* AEMIF */ 196 /* AEMIF */
197 DM365_AEMIF_AR, 197 DM365_AEMIF_AR_A14,
198 DM365_AEMIF_AR_BA0,
198 DM365_AEMIF_A3, 199 DM365_AEMIF_A3,
199 DM365_AEMIF_A7, 200 DM365_AEMIF_A7,
200 DM365_AEMIF_D15_8, 201 DM365_AEMIF_D15_8,
201 DM365_AEMIF_CE0, 202 DM365_AEMIF_CE0,
203 DM365_AEMIF_CE1,
204 DM365_AEMIF_WE_OE,
202 205
203 /* ASP0 function */ 206 /* ASP0 function */
204 DM365_MCBSP0_BDX, 207 DM365_MCBSP0_BDX,
@@ -287,10 +290,19 @@ enum davinci_dm365_index {
287 DM365_SPI4_SDENA0, 290 DM365_SPI4_SDENA0,
288 DM365_SPI4_SDENA1, 291 DM365_SPI4_SDENA1,
289 292
293 /* Clock */
294 DM365_CLKOUT0,
295 DM365_CLKOUT1,
296 DM365_CLKOUT2,
297
290 /* GPIO */ 298 /* GPIO */
291 DM365_GPIO20, 299 DM365_GPIO20,
300 DM365_GPIO30,
301 DM365_GPIO31,
302 DM365_GPIO32,
292 DM365_GPIO33, 303 DM365_GPIO33,
293 DM365_GPIO40, 304 DM365_GPIO40,
305 DM365_GPIO64_57,
294 306
295 /* Video */ 307 /* Video */
296 DM365_VOUT_FIELD, 308 DM365_VOUT_FIELD,
@@ -904,12 +916,288 @@ enum davinci_da850_index {
904 DA850_RTC_ALARM, 916 DA850_RTC_ALARM,
905}; 917};
906 918
919enum davinci_tnetv107x_index {
920 TNETV107X_ASR_A00,
921 TNETV107X_GPIO32,
922 TNETV107X_ASR_A01,
923 TNETV107X_GPIO33,
924 TNETV107X_ASR_A02,
925 TNETV107X_GPIO34,
926 TNETV107X_ASR_A03,
927 TNETV107X_GPIO35,
928 TNETV107X_ASR_A04,
929 TNETV107X_GPIO36,
930 TNETV107X_ASR_A05,
931 TNETV107X_GPIO37,
932 TNETV107X_ASR_A06,
933 TNETV107X_GPIO38,
934 TNETV107X_ASR_A07,
935 TNETV107X_GPIO39,
936 TNETV107X_ASR_A08,
937 TNETV107X_GPIO40,
938 TNETV107X_ASR_A09,
939 TNETV107X_GPIO41,
940 TNETV107X_ASR_A10,
941 TNETV107X_GPIO42,
942 TNETV107X_ASR_A11,
943 TNETV107X_BOOT_STRP_0,
944 TNETV107X_ASR_A12,
945 TNETV107X_BOOT_STRP_1,
946 TNETV107X_ASR_A13,
947 TNETV107X_GPIO43,
948 TNETV107X_ASR_A14,
949 TNETV107X_GPIO44,
950 TNETV107X_ASR_A15,
951 TNETV107X_GPIO45,
952 TNETV107X_ASR_A16,
953 TNETV107X_GPIO46,
954 TNETV107X_ASR_A17,
955 TNETV107X_GPIO47,
956 TNETV107X_ASR_A18,
957 TNETV107X_GPIO48,
958 TNETV107X_SDIO1_DATA3_0,
959 TNETV107X_ASR_A19,
960 TNETV107X_GPIO49,
961 TNETV107X_SDIO1_DATA2_0,
962 TNETV107X_ASR_A20,
963 TNETV107X_GPIO50,
964 TNETV107X_SDIO1_DATA1_0,
965 TNETV107X_ASR_A21,
966 TNETV107X_GPIO51,
967 TNETV107X_SDIO1_DATA0_0,
968 TNETV107X_ASR_A22,
969 TNETV107X_GPIO52,
970 TNETV107X_SDIO1_CMD_0,
971 TNETV107X_ASR_A23,
972 TNETV107X_GPIO53,
973 TNETV107X_SDIO1_CLK_0,
974 TNETV107X_ASR_BA_1,
975 TNETV107X_GPIO54,
976 TNETV107X_SYS_PLL_CLK,
977 TNETV107X_ASR_CS0,
978 TNETV107X_ASR_CS1,
979 TNETV107X_ASR_CS2,
980 TNETV107X_TDM_PLL_CLK,
981 TNETV107X_ASR_CS3,
982 TNETV107X_ETH_PHY_CLK,
983 TNETV107X_ASR_D00,
984 TNETV107X_GPIO55,
985 TNETV107X_ASR_D01,
986 TNETV107X_GPIO56,
987 TNETV107X_ASR_D02,
988 TNETV107X_GPIO57,
989 TNETV107X_ASR_D03,
990 TNETV107X_GPIO58,
991 TNETV107X_ASR_D04,
992 TNETV107X_GPIO59_0,
993 TNETV107X_ASR_D05,
994 TNETV107X_GPIO60_0,
995 TNETV107X_ASR_D06,
996 TNETV107X_GPIO61_0,
997 TNETV107X_ASR_D07,
998 TNETV107X_GPIO62_0,
999 TNETV107X_ASR_D08,
1000 TNETV107X_GPIO63_0,
1001 TNETV107X_ASR_D09,
1002 TNETV107X_GPIO64_0,
1003 TNETV107X_ASR_D10,
1004 TNETV107X_SDIO1_DATA3_1,
1005 TNETV107X_ASR_D11,
1006 TNETV107X_SDIO1_DATA2_1,
1007 TNETV107X_ASR_D12,
1008 TNETV107X_SDIO1_DATA1_1,
1009 TNETV107X_ASR_D13,
1010 TNETV107X_SDIO1_DATA0_1,
1011 TNETV107X_ASR_D14,
1012 TNETV107X_SDIO1_CMD_1,
1013 TNETV107X_ASR_D15,
1014 TNETV107X_SDIO1_CLK_1,
1015 TNETV107X_ASR_OE,
1016 TNETV107X_BOOT_STRP_2,
1017 TNETV107X_ASR_RNW,
1018 TNETV107X_GPIO29_0,
1019 TNETV107X_ASR_WAIT,
1020 TNETV107X_GPIO30_0,
1021 TNETV107X_ASR_WE,
1022 TNETV107X_BOOT_STRP_3,
1023 TNETV107X_ASR_WE_DQM0,
1024 TNETV107X_GPIO31,
1025 TNETV107X_LCD_PD17_0,
1026 TNETV107X_ASR_WE_DQM1,
1027 TNETV107X_ASR_BA0_0,
1028 TNETV107X_VLYNQ_CLK,
1029 TNETV107X_GPIO14,
1030 TNETV107X_LCD_PD19_0,
1031 TNETV107X_VLYNQ_RXD0,
1032 TNETV107X_GPIO15,
1033 TNETV107X_LCD_PD20_0,
1034 TNETV107X_VLYNQ_RXD1,
1035 TNETV107X_GPIO16,
1036 TNETV107X_LCD_PD21_0,
1037 TNETV107X_VLYNQ_TXD0,
1038 TNETV107X_GPIO17,
1039 TNETV107X_LCD_PD22_0,
1040 TNETV107X_VLYNQ_TXD1,
1041 TNETV107X_GPIO18,
1042 TNETV107X_LCD_PD23_0,
1043 TNETV107X_SDIO0_CLK,
1044 TNETV107X_GPIO19,
1045 TNETV107X_SDIO0_CMD,
1046 TNETV107X_GPIO20,
1047 TNETV107X_SDIO0_DATA0,
1048 TNETV107X_GPIO21,
1049 TNETV107X_SDIO0_DATA1,
1050 TNETV107X_GPIO22,
1051 TNETV107X_SDIO0_DATA2,
1052 TNETV107X_GPIO23,
1053 TNETV107X_SDIO0_DATA3,
1054 TNETV107X_GPIO24,
1055 TNETV107X_EMU0,
1056 TNETV107X_EMU1,
1057 TNETV107X_RTCK,
1058 TNETV107X_TRST_N,
1059 TNETV107X_TCK,
1060 TNETV107X_TDI,
1061 TNETV107X_TDO,
1062 TNETV107X_TMS,
1063 TNETV107X_TDM1_CLK,
1064 TNETV107X_TDM1_RX,
1065 TNETV107X_TDM1_TX,
1066 TNETV107X_TDM1_FS,
1067 TNETV107X_KEYPAD_R0,
1068 TNETV107X_KEYPAD_R1,
1069 TNETV107X_KEYPAD_R2,
1070 TNETV107X_KEYPAD_R3,
1071 TNETV107X_KEYPAD_R4,
1072 TNETV107X_KEYPAD_R5,
1073 TNETV107X_KEYPAD_R6,
1074 TNETV107X_GPIO12,
1075 TNETV107X_KEYPAD_R7,
1076 TNETV107X_GPIO10,
1077 TNETV107X_KEYPAD_C0,
1078 TNETV107X_KEYPAD_C1,
1079 TNETV107X_KEYPAD_C2,
1080 TNETV107X_KEYPAD_C3,
1081 TNETV107X_KEYPAD_C4,
1082 TNETV107X_KEYPAD_C5,
1083 TNETV107X_KEYPAD_C6,
1084 TNETV107X_GPIO13,
1085 TNETV107X_TEST_CLK_IN,
1086 TNETV107X_KEYPAD_C7,
1087 TNETV107X_GPIO11,
1088 TNETV107X_SSP0_0,
1089 TNETV107X_SCC_DCLK,
1090 TNETV107X_LCD_PD20_1,
1091 TNETV107X_SSP0_1,
1092 TNETV107X_SCC_CS_N,
1093 TNETV107X_LCD_PD21_1,
1094 TNETV107X_SSP0_2,
1095 TNETV107X_SCC_D,
1096 TNETV107X_LCD_PD22_1,
1097 TNETV107X_SSP0_3,
1098 TNETV107X_SCC_RESETN,
1099 TNETV107X_LCD_PD23_1,
1100 TNETV107X_SSP1_0,
1101 TNETV107X_GPIO25,
1102 TNETV107X_UART2_CTS,
1103 TNETV107X_SSP1_1,
1104 TNETV107X_GPIO26,
1105 TNETV107X_UART2_RD,
1106 TNETV107X_SSP1_2,
1107 TNETV107X_GPIO27,
1108 TNETV107X_UART2_RTS,
1109 TNETV107X_SSP1_3,
1110 TNETV107X_GPIO28,
1111 TNETV107X_UART2_TD,
1112 TNETV107X_UART0_CTS,
1113 TNETV107X_UART0_RD,
1114 TNETV107X_UART0_RTS,
1115 TNETV107X_UART0_TD,
1116 TNETV107X_UART1_RD,
1117 TNETV107X_UART1_TD,
1118 TNETV107X_LCD_AC_NCS,
1119 TNETV107X_LCD_HSYNC_RNW,
1120 TNETV107X_LCD_VSYNC_A0,
1121 TNETV107X_LCD_MCLK,
1122 TNETV107X_LCD_PD16_0,
1123 TNETV107X_LCD_PCLK_E,
1124 TNETV107X_LCD_PD00,
1125 TNETV107X_LCD_PD01,
1126 TNETV107X_LCD_PD02,
1127 TNETV107X_LCD_PD03,
1128 TNETV107X_LCD_PD04,
1129 TNETV107X_LCD_PD05,
1130 TNETV107X_LCD_PD06,
1131 TNETV107X_LCD_PD07,
1132 TNETV107X_LCD_PD08,
1133 TNETV107X_GPIO59_1,
1134 TNETV107X_LCD_PD09,
1135 TNETV107X_GPIO60_1,
1136 TNETV107X_LCD_PD10,
1137 TNETV107X_ASR_BA0_1,
1138 TNETV107X_GPIO61_1,
1139 TNETV107X_LCD_PD11,
1140 TNETV107X_GPIO62_1,
1141 TNETV107X_LCD_PD12,
1142 TNETV107X_GPIO63_1,
1143 TNETV107X_LCD_PD13,
1144 TNETV107X_GPIO64_1,
1145 TNETV107X_LCD_PD14,
1146 TNETV107X_GPIO29_1,
1147 TNETV107X_LCD_PD15,
1148 TNETV107X_GPIO30_1,
1149 TNETV107X_EINT0,
1150 TNETV107X_GPIO08,
1151 TNETV107X_EINT1,
1152 TNETV107X_GPIO09,
1153 TNETV107X_GPIO00,
1154 TNETV107X_LCD_PD20_2,
1155 TNETV107X_TDM_CLK_IN_2,
1156 TNETV107X_GPIO01,
1157 TNETV107X_LCD_PD21_2,
1158 TNETV107X_24M_CLK_OUT_1,
1159 TNETV107X_GPIO02,
1160 TNETV107X_LCD_PD22_2,
1161 TNETV107X_GPIO03,
1162 TNETV107X_LCD_PD23_2,
1163 TNETV107X_GPIO04,
1164 TNETV107X_LCD_PD16_1,
1165 TNETV107X_USB0_RXERR,
1166 TNETV107X_GPIO05,
1167 TNETV107X_LCD_PD17_1,
1168 TNETV107X_TDM_CLK_IN_1,
1169 TNETV107X_GPIO06,
1170 TNETV107X_LCD_PD18,
1171 TNETV107X_24M_CLK_OUT_2,
1172 TNETV107X_GPIO07,
1173 TNETV107X_LCD_PD19_1,
1174 TNETV107X_USB1_RXERR,
1175 TNETV107X_ETH_PLL_CLK,
1176 TNETV107X_MDIO,
1177 TNETV107X_MDC,
1178 TNETV107X_AIC_MUTE_STAT_N,
1179 TNETV107X_TDM0_CLK,
1180 TNETV107X_AIC_HNS_EN_N,
1181 TNETV107X_TDM0_FS,
1182 TNETV107X_AIC_HDS_EN_STAT_N,
1183 TNETV107X_TDM0_TX,
1184 TNETV107X_AIC_HNF_EN_STAT_N,
1185 TNETV107X_TDM0_RX,
1186};
1187
1188#define PINMUX(x) (4 * (x))
1189
907#ifdef CONFIG_DAVINCI_MUX 1190#ifdef CONFIG_DAVINCI_MUX
908/* setup pin muxing */ 1191/* setup pin muxing */
909extern int davinci_cfg_reg(unsigned long reg_cfg); 1192extern int davinci_cfg_reg(unsigned long reg_cfg);
1193extern int davinci_cfg_reg_list(const short pins[]);
910#else 1194#else
911/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ 1195/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
912static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } 1196static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
1197static inline int davinci_cfg_reg_list(const short pins[])
1198{
1199 return 0;
1200}
913#endif 1201#endif
914 1202
915#endif /* __INC_MACH_MUX_H */ 1203#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8158fa..983da6e4554c 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,6 +180,53 @@
180#define DA8XX_LPSC1_CR_P3_SS 26 180#define DA8XX_LPSC1_CR_P3_SS 26
181#define DA8XX_LPSC1_L3_CBA_RAM 31 181#define DA8XX_LPSC1_L3_CBA_RAM 31
182 182
183/* TNETV107X LPSC Assignments */
184#define TNETV107X_LPSC_ARM 0
185#define TNETV107X_LPSC_GEM 1
186#define TNETV107X_LPSC_DDR2_PHY 2
187#define TNETV107X_LPSC_TPCC 3
188#define TNETV107X_LPSC_TPTC0 4
189#define TNETV107X_LPSC_TPTC1 5
190#define TNETV107X_LPSC_RAM 6
191#define TNETV107X_LPSC_MBX_LITE 7
192#define TNETV107X_LPSC_LCD 8
193#define TNETV107X_LPSC_ETHSS 9
194#define TNETV107X_LPSC_AEMIF 10
195#define TNETV107X_LPSC_CHIP_CFG 11
196#define TNETV107X_LPSC_TSC 12
197#define TNETV107X_LPSC_ROM 13
198#define TNETV107X_LPSC_UART2 14
199#define TNETV107X_LPSC_PKTSEC 15
200#define TNETV107X_LPSC_SECCTL 16
201#define TNETV107X_LPSC_KEYMGR 17
202#define TNETV107X_LPSC_KEYPAD 18
203#define TNETV107X_LPSC_GPIO 19
204#define TNETV107X_LPSC_MDIO 20
205#define TNETV107X_LPSC_SDIO0 21
206#define TNETV107X_LPSC_UART0 22
207#define TNETV107X_LPSC_UART1 23
208#define TNETV107X_LPSC_TIMER0 24
209#define TNETV107X_LPSC_TIMER1 25
210#define TNETV107X_LPSC_WDT_ARM 26
211#define TNETV107X_LPSC_WDT_DSP 27
212#define TNETV107X_LPSC_SSP 28
213#define TNETV107X_LPSC_TDM0 29
214#define TNETV107X_LPSC_VLYNQ 30
215#define TNETV107X_LPSC_MCDMA 31
216#define TNETV107X_LPSC_USB0 32
217#define TNETV107X_LPSC_TDM1 33
218#define TNETV107X_LPSC_DEBUGSS 34
219#define TNETV107X_LPSC_ETHSS_RGMII 35
220#define TNETV107X_LPSC_SYSTEM 36
221#define TNETV107X_LPSC_IMCOP 37
222#define TNETV107X_LPSC_SPARE 38
223#define TNETV107X_LPSC_SDIO1 39
224#define TNETV107X_LPSC_USB1 40
225#define TNETV107X_LPSC_USBSS 41
226#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
227#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
228#define TNETV107X_LPSC_MAX 44
229
183/* PSC register offsets */ 230/* PSC register offsets */
184#define EPCPR 0x070 231#define EPCPR 0x070
185#define PTCMD 0x120 232#define PTCMD 0x120
@@ -189,13 +236,19 @@
189#define MDSTAT 0x800 236#define MDSTAT 0x800
190#define MDCTL 0xA00 237#define MDCTL 0xA00
191 238
239/* PSC module states */
240#define PSC_STATE_SWRSTDISABLE 0
241#define PSC_STATE_SYNCRST 1
242#define PSC_STATE_DISABLE 2
243#define PSC_STATE_ENABLE 3
244
192#define MDSTAT_STATE_MASK 0x1f 245#define MDSTAT_STATE_MASK 0x1f
193 246
194#ifndef __ASSEMBLER__ 247#ifndef __ASSEMBLER__
195 248
196extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 249extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
197extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 250extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
198 unsigned int id, char enable); 251 unsigned int id, u32 next_state);
199 252
200#endif 253#endif
201 254
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index a584697a9e70..f6c4f34909a2 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,7 +13,6 @@
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 16#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 17#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 18#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 5a7d7581b8ce..e65629c20769 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H 12#define __ASM_ARCH_SYSTEM_H
13 13
14extern void davinci_watchdog_reset(void); 14#include <mach/common.h>
15 15
16static inline void arch_idle(void) 16static inline void arch_idle(void)
17{ 17{
@@ -20,7 +20,8 @@ static inline void arch_idle(void)
20 20
21static inline void arch_reset(char mode, const char *cmd) 21static inline void arch_reset(char mode, const char *cmd)
22{ 22{
23 davinci_watchdog_reset(); 23 if (davinci_soc_info.reset)
24 davinci_soc_info.reset(davinci_soc_info.reset_device);
24} 25}
25 26
26#endif /* __ASM_ARCH_SYSTEM_H */ 27#endif /* __ASM_ARCH_SYSTEM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 15:54:20 -0500