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-rw-r--r--arch/arm/mach-davinci/gpio.c286
1 files changed, 286 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
new file mode 100644
index 000000000000..9c67886e7189
--- /dev/null
+++ b/arch/arm/mach-davinci/gpio.c
@@ -0,0 +1,286 @@
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/bitops.h>
22
23#include <asm/arch/irqs.h>
24#include <asm/arch/hardware.h>
25#include <asm/arch/gpio.h>
26
27#include <asm/mach/irq.h>
28
29static DEFINE_SPINLOCK(gpio_lock);
30static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO);
31
32int gpio_request(unsigned gpio, const char *tag)
33{
34 if (gpio >= DAVINCI_N_GPIO)
35 return -EINVAL;
36
37 if (test_and_set_bit(gpio, gpio_in_use))
38 return -EBUSY;
39
40 return 0;
41}
42EXPORT_SYMBOL(gpio_request);
43
44void gpio_free(unsigned gpio)
45{
46 if (gpio >= DAVINCI_N_GPIO)
47 return;
48
49 clear_bit(gpio, gpio_in_use);
50}
51EXPORT_SYMBOL(gpio_free);
52
53/* create a non-inlined version */
54static struct gpio_controller *__iomem gpio2controller(unsigned gpio)
55{
56 return __gpio_to_controller(gpio);
57}
58
59/*
60 * Assuming the pin is muxed as a gpio output, set its output value.
61 */
62void __gpio_set(unsigned gpio, int value)
63{
64 struct gpio_controller *__iomem g = gpio2controller(gpio);
65
66 __raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data);
67}
68EXPORT_SYMBOL(__gpio_set);
69
70
71/*
72 * Read the pin's value (works even if it's set up as output);
73 * returns zero/nonzero.
74 *
75 * Note that changes are synched to the GPIO clock, so reading values back
76 * right after you've set them may give old values.
77 */
78int __gpio_get(unsigned gpio)
79{
80 struct gpio_controller *__iomem g = gpio2controller(gpio);
81
82 return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
83}
84EXPORT_SYMBOL(__gpio_get);
85
86
87/*--------------------------------------------------------------------------*/
88
89/*
90 * board setup code *MUST* set PINMUX0 and PINMUX1 as
91 * needed, and enable the GPIO clock.
92 */
93
94int gpio_direction_input(unsigned gpio)
95{
96 struct gpio_controller *__iomem g = gpio2controller(gpio);
97 u32 temp;
98 u32 mask;
99
100 if (!g)
101 return -EINVAL;
102
103 spin_lock(&gpio_lock);
104 mask = __gpio_mask(gpio);
105 temp = __raw_readl(&g->dir);
106 temp |= mask;
107 __raw_writel(temp, &g->dir);
108 spin_unlock(&gpio_lock);
109 return 0;
110}
111EXPORT_SYMBOL(gpio_direction_input);
112
113int gpio_direction_output(unsigned gpio, int value)
114{
115 struct gpio_controller *__iomem g = gpio2controller(gpio);
116 u32 temp;
117 u32 mask;
118
119 if (!g)
120 return -EINVAL;
121
122 spin_lock(&gpio_lock);
123 mask = __gpio_mask(gpio);
124 temp = __raw_readl(&g->dir);
125 temp &= ~mask;
126 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
127 __raw_writel(temp, &g->dir);
128 spin_unlock(&gpio_lock);
129 return 0;
130}
131EXPORT_SYMBOL(gpio_direction_output);
132
133/*
134 * We expect irqs will normally be set up as input pins, but they can also be
135 * used as output pins ... which is convenient for testing.
136 *
137 * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition
138 * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have
139 * a good way to hook those up ...
140 *
141 * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
142 * serve as EDMA event triggers.
143 */
144
145static void gpio_irq_disable(unsigned irq)
146{
147 struct gpio_controller *__iomem g = get_irq_chip_data(irq);
148 u32 mask = __gpio_mask(irq_to_gpio(irq));
149
150 __raw_writel(mask, &g->clr_falling);
151 __raw_writel(mask, &g->clr_rising);
152}
153
154static void gpio_irq_enable(unsigned irq)
155{
156 struct gpio_controller *__iomem g = get_irq_chip_data(irq);
157 u32 mask = __gpio_mask(irq_to_gpio(irq));
158
159 if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
160 __raw_writel(mask, &g->set_falling);
161 if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
162 __raw_writel(mask, &g->set_rising);
163}
164
165static int gpio_irq_type(unsigned irq, unsigned trigger)
166{
167 struct gpio_controller *__iomem g = get_irq_chip_data(irq);
168 u32 mask = __gpio_mask(irq_to_gpio(irq));
169
170 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
171 return -EINVAL;
172
173 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
174 irq_desc[irq].status |= trigger;
175
176 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
177 ? &g->set_falling : &g->clr_falling);
178 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
179 ? &g->set_rising : &g->clr_rising);
180 return 0;
181}
182
183static struct irq_chip gpio_irqchip = {
184 .name = "GPIO",
185 .enable = gpio_irq_enable,
186 .disable = gpio_irq_disable,
187 .set_type = gpio_irq_type,
188};
189
190static void
191gpio_irq_handler(unsigned irq, struct irq_desc *desc)
192{
193 struct gpio_controller *__iomem g = get_irq_chip_data(irq);
194 u32 mask = 0xffff;
195
196 /* we only care about one bank */
197 if (irq & 1)
198 mask <<= 16;
199
200 /* temporarily mask (level sensitive) parent IRQ */
201 desc->chip->ack(irq);
202 while (1) {
203 u32 status;
204 struct irq_desc *gpio;
205 int n;
206 int res;
207
208 /* ack any irqs */
209 status = __raw_readl(&g->intstat) & mask;
210 if (!status)
211 break;
212 __raw_writel(status, &g->intstat);
213 if (irq & 1)
214 status >>= 16;
215
216 /* now demux them to the right lowlevel handler */
217 n = (int)get_irq_data(irq);
218 gpio = &irq_desc[n];
219 while (status) {
220 res = ffs(status);
221 n += res;
222 gpio += res;
223 desc_handle_irq(n - 1, gpio - 1);
224 status >>= res;
225 }
226 }
227 desc->chip->unmask(irq);
228 /* now it may re-trigger */
229}
230
231/*
232 * NOTE: for suspend/resume, probably best to make a sysdev (and class)
233 * with its suspend/resume calls hooking into the results of the set_wake()
234 * calls ... so if no gpios are wakeup events the clock can be disabled,
235 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
236 * can be set appropriately for GPIOV33 pins.
237 */
238
239static int __init davinci_gpio_irq_setup(void)
240{
241 unsigned gpio, irq, bank;
242 struct clk *clk;
243
244 clk = clk_get(NULL, "gpio");
245 if (IS_ERR(clk)) {
246 printk(KERN_ERR "Error %ld getting gpio clock?\n",
247 PTR_ERR(clk));
248 return 0;
249 }
250
251 clk_enable(clk);
252
253 for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0;
254 gpio < DAVINCI_N_GPIO; bank++) {
255 struct gpio_controller *__iomem g = gpio2controller(gpio);
256 unsigned i;
257
258 __raw_writel(~0, &g->clr_falling);
259 __raw_writel(~0, &g->clr_rising);
260
261 /* set up all irqs in this bank */
262 set_irq_chained_handler(bank, gpio_irq_handler);
263 set_irq_chip_data(bank, g);
264 set_irq_data(bank, (void *)irq);
265
266 for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO;
267 i++, irq++, gpio++) {
268 set_irq_chip(irq, &gpio_irqchip);
269 set_irq_chip_data(irq, g);
270 set_irq_handler(irq, handle_simple_irq);
271 set_irq_flags(irq, IRQF_VALID);
272 }
273 }
274
275 /* BINTEN -- per-bank interrupt enable. genirq would also let these
276 * bits be set/cleared dynamically.
277 */
278 __raw_writel(0x1f, (void *__iomem)
279 IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
280
281 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
282
283 return 0;
284}
285
286arch_initcall(davinci_gpio_irq_setup);