1 files changed, 14 insertions, 25 deletions

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 40327b557d79..1b6532159c58 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -23,6 +23,7 @@
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <mach/gpio.h>
 
 #include <asm/mach/irq.h>
@@ -37,8 +38,6 @@ struct davinci_gpio {
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
-static unsigned __initdata ngpio;
-
 /* create a non-inlined version */
 static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
 {
@@ -116,23 +115,16 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 static int __init davinci_gpio_setup(void)
 {
         int i, base;
+        unsigned ngpio;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
 
-        /* The gpio banks conceptually expose a segmented bitmap,
+        /*
+         * The gpio banks conceptually expose a segmented bitmap,
          * and "ngpio" is one more than the largest zero-based
          * bit index that's valid.
          */
-        if (cpu_is_davinci_dm355()) {           /* or dm335() */
-                ngpio = 104;
-        } else if (cpu_is_davinci_dm644x()) {   /* or dm337() */
-                ngpio = 71;
-        } else if (cpu_is_davinci_dm646x()) {
-                /* NOTE:  each bank has several "reserved" bits,
-                 * unusable as GPIOs.  Only 33 of the GPIO numbers
-                 * are usable, and we're not rejecting the others.
-                 */
-                ngpio = 43;
-        } else {
-                /* if cpu_is_davinci_dm643x() ngpio = 111 */
+        ngpio = soc_info->gpio_num;
+        if (ngpio == 0) {
                 pr_err("GPIO setup:  how many GPIOs?\n");
                 return -EINVAL;
         }
@@ -279,17 +271,15 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 static int __init davinci_gpio_irq_setup(void)
 {
         unsigned        gpio, irq, bank;
-        unsigned        bank_irq;
         struct clk      *clk;
         u32             binten = 0;
+        unsigned        ngpio, bank_irq;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        ngpio = soc_info->gpio_num;
 
-        if (cpu_is_davinci_dm355()) {           /* or dm335() */
-                bank_irq = IRQ_DM355_GPIOBNK0;
-        } else if (cpu_is_davinci_dm644x()) {
-                bank_irq = IRQ_GPIOBNK0;
-        } else if (cpu_is_davinci_dm646x()) {
-                bank_irq = IRQ_DM646X_GPIOBNK0;
-        } else {
+        bank_irq = soc_info->gpio_irq;
+        if (bank_irq == 0) {
                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
                 return -EINVAL;
         }
@@ -329,8 +319,7 @@ static int __init davinci_gpio_irq_setup(void)
         /* BINTEN -- per-bank interrupt enable. genirq would also let these
          * bits be set/cleared dynamically.
          */
-        __raw_writel(binten, (void *__iomem)
-                     IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
+        __raw_writel(binten, soc_info->gpio_base + 0x08);
 
         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));