diff options
Diffstat (limited to 'arch/arm/mach-davinci/dma.c')
-rw-r--r-- | arch/arm/mach-davinci/dma.c | 234 |
1 files changed, 116 insertions, 118 deletions
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 53137387aee1..d33827aadda7 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c | |||
@@ -243,7 +243,7 @@ struct edma { | |||
243 | } intr_data[EDMA_MAX_DMACH]; | 243 | } intr_data[EDMA_MAX_DMACH]; |
244 | }; | 244 | }; |
245 | 245 | ||
246 | static struct edma *edma_info[EDMA_MAX_CC]; | 246 | static struct edma *edma_cc[EDMA_MAX_CC]; |
247 | static int arch_num_cc; | 247 | static int arch_num_cc; |
248 | 248 | ||
249 | /* dummy param set used to (re)initialize parameter RAM slots */ | 249 | /* dummy param set used to (re)initialize parameter RAM slots */ |
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, | |||
261 | 261 | ||
262 | /* default to low priority queue */ | 262 | /* default to low priority queue */ |
263 | if (queue_no == EVENTQ_DEFAULT) | 263 | if (queue_no == EVENTQ_DEFAULT) |
264 | queue_no = edma_info[ctlr]->default_queue; | 264 | queue_no = edma_cc[ctlr]->default_queue; |
265 | 265 | ||
266 | queue_no &= 7; | 266 | queue_no &= 7; |
267 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), | 267 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
@@ -310,29 +310,27 @@ setup_dma_interrupt(unsigned lch, | |||
310 | ctlr = EDMA_CTLR(lch); | 310 | ctlr = EDMA_CTLR(lch); |
311 | lch = EDMA_CHAN_SLOT(lch); | 311 | lch = EDMA_CHAN_SLOT(lch); |
312 | 312 | ||
313 | if (!callback) { | 313 | if (!callback) |
314 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, | 314 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
315 | (1 << (lch & 0x1f))); | 315 | BIT(lch & 0x1f)); |
316 | } | ||
317 | 316 | ||
318 | edma_info[ctlr]->intr_data[lch].callback = callback; | 317 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
319 | edma_info[ctlr]->intr_data[lch].data = data; | 318 | edma_cc[ctlr]->intr_data[lch].data = data; |
320 | 319 | ||
321 | if (callback) { | 320 | if (callback) { |
322 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, | 321 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
323 | (1 << (lch & 0x1f))); | 322 | BIT(lch & 0x1f)); |
324 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, | 323 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
325 | (1 << (lch & 0x1f))); | 324 | BIT(lch & 0x1f)); |
326 | } | 325 | } |
327 | } | 326 | } |
328 | 327 | ||
329 | static int irq2ctlr(int irq) | 328 | static int irq2ctlr(int irq) |
330 | { | 329 | { |
331 | if (irq >= edma_info[0]->irq_res_start && | 330 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
332 | irq <= edma_info[0]->irq_res_end) | ||
333 | return 0; | 331 | return 0; |
334 | else if (irq >= edma_info[1]->irq_res_start && | 332 | else if (irq >= edma_cc[1]->irq_res_start && |
335 | irq <= edma_info[1]->irq_res_end) | 333 | irq <= edma_cc[1]->irq_res_end) |
336 | return 1; | 334 | return 1; |
337 | 335 | ||
338 | return -1; | 336 | return -1; |
@@ -353,15 +351,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data) | |||
353 | 351 | ||
354 | dev_dbg(data, "dma_irq_handler\n"); | 352 | dev_dbg(data, "dma_irq_handler\n"); |
355 | 353 | ||
356 | if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) | 354 | if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && |
357 | && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) | 355 | (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) |
358 | return IRQ_NONE; | 356 | return IRQ_NONE; |
359 | 357 | ||
360 | while (1) { | 358 | while (1) { |
361 | int j; | 359 | int j; |
362 | if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) | 360 | if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & |
361 | edma_shadow0_read_array(ctlr, SH_IER, 0)) | ||
363 | j = 0; | 362 | j = 0; |
364 | else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) | 363 | else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & |
364 | edma_shadow0_read_array(ctlr, SH_IER, 1)) | ||
365 | j = 1; | 365 | j = 1; |
366 | else | 366 | else |
367 | break; | 367 | break; |
@@ -369,17 +369,17 @@ static irqreturn_t dma_irq_handler(int irq, void *data) | |||
369 | edma_shadow0_read_array(ctlr, SH_IPR, j)); | 369 | edma_shadow0_read_array(ctlr, SH_IPR, j)); |
370 | for (i = 0; i < 32; i++) { | 370 | for (i = 0; i < 32; i++) { |
371 | int k = (j << 5) + i; | 371 | int k = (j << 5) + i; |
372 | if (edma_shadow0_read_array(ctlr, SH_IPR, j) & | 372 | if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) |
373 | (1 << i)) { | 373 | && (edma_shadow0_read_array(ctlr, |
374 | SH_IER, j) & BIT(i))) { | ||
374 | /* Clear the corresponding IPR bits */ | 375 | /* Clear the corresponding IPR bits */ |
375 | edma_shadow0_write_array(ctlr, SH_ICR, j, | 376 | edma_shadow0_write_array(ctlr, SH_ICR, j, |
376 | (1 << i)); | 377 | BIT(i)); |
377 | if (edma_info[ctlr]->intr_data[k].callback) { | 378 | if (edma_cc[ctlr]->intr_data[k].callback) |
378 | edma_info[ctlr]->intr_data[k].callback( | 379 | edma_cc[ctlr]->intr_data[k].callback( |
379 | k, DMA_COMPLETE, | 380 | k, DMA_COMPLETE, |
380 | edma_info[ctlr]->intr_data[k]. | 381 | edma_cc[ctlr]->intr_data[k]. |
381 | data); | 382 | data); |
382 | } | ||
383 | } | 383 | } |
384 | } | 384 | } |
385 | cnt++; | 385 | cnt++; |
@@ -423,19 +423,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) | |||
423 | for (i = 0; i < 32; i++) { | 423 | for (i = 0; i < 32; i++) { |
424 | int k = (j << 5) + i; | 424 | int k = (j << 5) + i; |
425 | if (edma_read_array(ctlr, EDMA_EMR, j) & | 425 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
426 | (1 << i)) { | 426 | BIT(i)) { |
427 | /* Clear the corresponding EMR bits */ | 427 | /* Clear the corresponding EMR bits */ |
428 | edma_write_array(ctlr, EDMA_EMCR, j, | 428 | edma_write_array(ctlr, EDMA_EMCR, j, |
429 | 1 << i); | 429 | BIT(i)); |
430 | /* Clear any SER */ | 430 | /* Clear any SER */ |
431 | edma_shadow0_write_array(ctlr, SH_SECR, | 431 | edma_shadow0_write_array(ctlr, SH_SECR, |
432 | j, (1 << i)); | 432 | j, BIT(i)); |
433 | if (edma_info[ctlr]->intr_data[k]. | 433 | if (edma_cc[ctlr]->intr_data[k]. |
434 | callback) { | 434 | callback) { |
435 | edma_info[ctlr]->intr_data[k]. | 435 | edma_cc[ctlr]->intr_data[k]. |
436 | callback(k, | 436 | callback(k, |
437 | DMA_CC_ERROR, | 437 | DMA_CC_ERROR, |
438 | edma_info[ctlr]->intr_data | 438 | edma_cc[ctlr]->intr_data |
439 | [k].data); | 439 | [k].data); |
440 | } | 440 | } |
441 | } | 441 | } |
@@ -444,11 +444,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) | |||
444 | dev_dbg(data, "QEMR %02x\n", | 444 | dev_dbg(data, "QEMR %02x\n", |
445 | edma_read(ctlr, EDMA_QEMR)); | 445 | edma_read(ctlr, EDMA_QEMR)); |
446 | for (i = 0; i < 8; i++) { | 446 | for (i = 0; i < 8; i++) { |
447 | if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { | 447 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
448 | /* Clear the corresponding IPR bits */ | 448 | /* Clear the corresponding IPR bits */ |
449 | edma_write(ctlr, EDMA_QEMCR, 1 << i); | 449 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
450 | edma_shadow0_write(ctlr, SH_QSECR, | 450 | edma_shadow0_write(ctlr, SH_QSECR, |
451 | (1 << i)); | 451 | BIT(i)); |
452 | 452 | ||
453 | /* NOTE: not reported!! */ | 453 | /* NOTE: not reported!! */ |
454 | } | 454 | } |
@@ -460,20 +460,19 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) | |||
460 | * to just write CCERRCLR with CCERR value... | 460 | * to just write CCERRCLR with CCERR value... |
461 | */ | 461 | */ |
462 | for (i = 0; i < 8; i++) { | 462 | for (i = 0; i < 8; i++) { |
463 | if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { | 463 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
464 | /* Clear the corresponding IPR bits */ | 464 | /* Clear the corresponding IPR bits */ |
465 | edma_write(ctlr, EDMA_CCERRCLR, 1 << i); | 465 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
466 | 466 | ||
467 | /* NOTE: not reported!! */ | 467 | /* NOTE: not reported!! */ |
468 | } | 468 | } |
469 | } | 469 | } |
470 | } | 470 | } |
471 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) | 471 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
472 | && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) | 472 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && |
473 | && (edma_read(ctlr, EDMA_QEMR) == 0) | 473 | (edma_read(ctlr, EDMA_QEMR) == 0) && |
474 | && (edma_read(ctlr, EDMA_CCERR) == 0)) { | 474 | (edma_read(ctlr, EDMA_CCERR) == 0)) |
475 | break; | 475 | break; |
476 | } | ||
477 | cnt++; | 476 | cnt++; |
478 | if (cnt > 10) | 477 | if (cnt > 10) |
479 | break; | 478 | break; |
@@ -511,9 +510,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, | |||
511 | int stop_slot = start_slot; | 510 | int stop_slot = start_slot; |
512 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); | 511 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
513 | 512 | ||
514 | for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) { | 513 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
515 | j = EDMA_CHAN_SLOT(i); | 514 | j = EDMA_CHAN_SLOT(i); |
516 | if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) { | 515 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
517 | /* Record our current beginning slot */ | 516 | /* Record our current beginning slot */ |
518 | if (count == num_slots) | 517 | if (count == num_slots) |
519 | stop_slot = i; | 518 | stop_slot = i; |
@@ -529,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, | |||
529 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | 528 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { |
530 | stop_slot = i; | 529 | stop_slot = i; |
531 | break; | 530 | break; |
532 | } else | 531 | } else { |
533 | count = num_slots; | 532 | count = num_slots; |
533 | } | ||
534 | } | 534 | } |
535 | } | 535 | } |
536 | 536 | ||
@@ -540,12 +540,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id, | |||
540 | * of contiguous parameter RAM slots but do not find the exact number | 540 | * of contiguous parameter RAM slots but do not find the exact number |
541 | * requested as we may reach the total number of parameter RAM slots | 541 | * requested as we may reach the total number of parameter RAM slots |
542 | */ | 542 | */ |
543 | if (i == edma_info[ctlr]->num_slots) | 543 | if (i == edma_cc[ctlr]->num_slots) |
544 | stop_slot = i; | 544 | stop_slot = i; |
545 | 545 | ||
546 | for (j = start_slot; j < stop_slot; j++) | 546 | for (j = start_slot; j < stop_slot; j++) |
547 | if (test_bit(j, tmp_inuse)) | 547 | if (test_bit(j, tmp_inuse)) |
548 | clear_bit(j, edma_info[ctlr]->edma_inuse); | 548 | clear_bit(j, edma_cc[ctlr]->edma_inuse); |
549 | 549 | ||
550 | if (count) | 550 | if (count) |
551 | return -EBUSY; | 551 | return -EBUSY; |
@@ -567,7 +567,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) | |||
567 | (int)pdev->resource[i].start >= 0) { | 567 | (int)pdev->resource[i].start >= 0) { |
568 | ctlr = EDMA_CTLR(pdev->resource[i].start); | 568 | ctlr = EDMA_CTLR(pdev->resource[i].start); |
569 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | 569 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), |
570 | edma_info[ctlr]->edma_unused); | 570 | edma_cc[ctlr]->edma_unused); |
571 | } | 571 | } |
572 | } | 572 | } |
573 | 573 | ||
@@ -641,14 +641,13 @@ int edma_alloc_channel(int channel, | |||
641 | for (i = 0; i < arch_num_cc; i++) { | 641 | for (i = 0; i < arch_num_cc; i++) { |
642 | channel = 0; | 642 | channel = 0; |
643 | for (;;) { | 643 | for (;;) { |
644 | channel = find_next_bit(edma_info[i]-> | 644 | channel = find_next_bit(edma_cc[i]->edma_unused, |
645 | edma_unused, | 645 | edma_cc[i]->num_channels, |
646 | edma_info[i]->num_channels, | ||
647 | channel); | 646 | channel); |
648 | if (channel == edma_info[i]->num_channels) | 647 | if (channel == edma_cc[i]->num_channels) |
649 | break; | 648 | break; |
650 | if (!test_and_set_bit(channel, | 649 | if (!test_and_set_bit(channel, |
651 | edma_info[i]->edma_inuse)) { | 650 | edma_cc[i]->edma_inuse)) { |
652 | done = 1; | 651 | done = 1; |
653 | ctlr = i; | 652 | ctlr = i; |
654 | break; | 653 | break; |
@@ -660,14 +659,14 @@ int edma_alloc_channel(int channel, | |||
660 | } | 659 | } |
661 | if (!done) | 660 | if (!done) |
662 | return -ENOMEM; | 661 | return -ENOMEM; |
663 | } else if (channel >= edma_info[ctlr]->num_channels) { | 662 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
664 | return -EINVAL; | 663 | return -EINVAL; |
665 | } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { | 664 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
666 | return -EBUSY; | 665 | return -EBUSY; |
667 | } | 666 | } |
668 | 667 | ||
669 | /* ensure access through shadow region 0 */ | 668 | /* ensure access through shadow region 0 */ |
670 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); | 669 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
671 | 670 | ||
672 | /* ensure no events are pending */ | 671 | /* ensure no events are pending */ |
673 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); | 672 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
@@ -703,7 +702,7 @@ void edma_free_channel(unsigned channel) | |||
703 | ctlr = EDMA_CTLR(channel); | 702 | ctlr = EDMA_CTLR(channel); |
704 | channel = EDMA_CHAN_SLOT(channel); | 703 | channel = EDMA_CHAN_SLOT(channel); |
705 | 704 | ||
706 | if (channel >= edma_info[ctlr]->num_channels) | 705 | if (channel >= edma_cc[ctlr]->num_channels) |
707 | return; | 706 | return; |
708 | 707 | ||
709 | setup_dma_interrupt(channel, NULL, NULL); | 708 | setup_dma_interrupt(channel, NULL, NULL); |
@@ -711,7 +710,7 @@ void edma_free_channel(unsigned channel) | |||
711 | 710 | ||
712 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | 711 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
713 | &dummy_paramset, PARM_SIZE); | 712 | &dummy_paramset, PARM_SIZE); |
714 | clear_bit(channel, edma_info[ctlr]->edma_inuse); | 713 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
715 | } | 714 | } |
716 | EXPORT_SYMBOL(edma_free_channel); | 715 | EXPORT_SYMBOL(edma_free_channel); |
717 | 716 | ||
@@ -735,20 +734,19 @@ int edma_alloc_slot(unsigned ctlr, int slot) | |||
735 | slot = EDMA_CHAN_SLOT(slot); | 734 | slot = EDMA_CHAN_SLOT(slot); |
736 | 735 | ||
737 | if (slot < 0) { | 736 | if (slot < 0) { |
738 | slot = edma_info[ctlr]->num_channels; | 737 | slot = edma_cc[ctlr]->num_channels; |
739 | for (;;) { | 738 | for (;;) { |
740 | slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, | 739 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
741 | edma_info[ctlr]->num_slots, slot); | 740 | edma_cc[ctlr]->num_slots, slot); |
742 | if (slot == edma_info[ctlr]->num_slots) | 741 | if (slot == edma_cc[ctlr]->num_slots) |
743 | return -ENOMEM; | 742 | return -ENOMEM; |
744 | if (!test_and_set_bit(slot, | 743 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
745 | edma_info[ctlr]->edma_inuse)) | ||
746 | break; | 744 | break; |
747 | } | 745 | } |
748 | } else if (slot < edma_info[ctlr]->num_channels || | 746 | } else if (slot < edma_cc[ctlr]->num_channels || |
749 | slot >= edma_info[ctlr]->num_slots) { | 747 | slot >= edma_cc[ctlr]->num_slots) { |
750 | return -EINVAL; | 748 | return -EINVAL; |
751 | } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { | 749 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
752 | return -EBUSY; | 750 | return -EBUSY; |
753 | } | 751 | } |
754 | 752 | ||
@@ -774,13 +772,13 @@ void edma_free_slot(unsigned slot) | |||
774 | ctlr = EDMA_CTLR(slot); | 772 | ctlr = EDMA_CTLR(slot); |
775 | slot = EDMA_CHAN_SLOT(slot); | 773 | slot = EDMA_CHAN_SLOT(slot); |
776 | 774 | ||
777 | if (slot < edma_info[ctlr]->num_channels || | 775 | if (slot < edma_cc[ctlr]->num_channels || |
778 | slot >= edma_info[ctlr]->num_slots) | 776 | slot >= edma_cc[ctlr]->num_slots) |
779 | return; | 777 | return; |
780 | 778 | ||
781 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), | 779 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
782 | &dummy_paramset, PARM_SIZE); | 780 | &dummy_paramset, PARM_SIZE); |
783 | clear_bit(slot, edma_info[ctlr]->edma_inuse); | 781 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
784 | } | 782 | } |
785 | EXPORT_SYMBOL(edma_free_slot); | 783 | EXPORT_SYMBOL(edma_free_slot); |
786 | 784 | ||
@@ -818,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |||
818 | * of slots | 816 | * of slots |
819 | */ | 817 | */ |
820 | if ((id != EDMA_CONT_PARAMS_ANY) && | 818 | if ((id != EDMA_CONT_PARAMS_ANY) && |
821 | (slot < edma_info[ctlr]->num_channels || | 819 | (slot < edma_cc[ctlr]->num_channels || |
822 | slot >= edma_info[ctlr]->num_slots)) | 820 | slot >= edma_cc[ctlr]->num_slots)) |
823 | return -EINVAL; | 821 | return -EINVAL; |
824 | 822 | ||
825 | /* | 823 | /* |
@@ -828,13 +826,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |||
828 | * channels | 826 | * channels |
829 | */ | 827 | */ |
830 | if (count < 1 || count > | 828 | if (count < 1 || count > |
831 | (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) | 829 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
832 | return -EINVAL; | 830 | return -EINVAL; |
833 | 831 | ||
834 | switch (id) { | 832 | switch (id) { |
835 | case EDMA_CONT_PARAMS_ANY: | 833 | case EDMA_CONT_PARAMS_ANY: |
836 | return reserve_contiguous_slots(ctlr, id, count, | 834 | return reserve_contiguous_slots(ctlr, id, count, |
837 | edma_info[ctlr]->num_channels); | 835 | edma_cc[ctlr]->num_channels); |
838 | case EDMA_CONT_PARAMS_FIXED_EXACT: | 836 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
839 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | 837 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: |
840 | return reserve_contiguous_slots(ctlr, id, count, slot); | 838 | return reserve_contiguous_slots(ctlr, id, count, slot); |
@@ -866,8 +864,8 @@ int edma_free_cont_slots(unsigned slot, int count) | |||
866 | ctlr = EDMA_CTLR(slot); | 864 | ctlr = EDMA_CTLR(slot); |
867 | slot = EDMA_CHAN_SLOT(slot); | 865 | slot = EDMA_CHAN_SLOT(slot); |
868 | 866 | ||
869 | if (slot < edma_info[ctlr]->num_channels || | 867 | if (slot < edma_cc[ctlr]->num_channels || |
870 | slot >= edma_info[ctlr]->num_slots || | 868 | slot >= edma_cc[ctlr]->num_slots || |
871 | count < 1) | 869 | count < 1) |
872 | return -EINVAL; | 870 | return -EINVAL; |
873 | 871 | ||
@@ -877,7 +875,7 @@ int edma_free_cont_slots(unsigned slot, int count) | |||
877 | 875 | ||
878 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), | 876 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
879 | &dummy_paramset, PARM_SIZE); | 877 | &dummy_paramset, PARM_SIZE); |
880 | clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse); | 878 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
881 | } | 879 | } |
882 | 880 | ||
883 | return 0; | 881 | return 0; |
@@ -907,7 +905,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, | |||
907 | ctlr = EDMA_CTLR(slot); | 905 | ctlr = EDMA_CTLR(slot); |
908 | slot = EDMA_CHAN_SLOT(slot); | 906 | slot = EDMA_CHAN_SLOT(slot); |
909 | 907 | ||
910 | if (slot < edma_info[ctlr]->num_slots) { | 908 | if (slot < edma_cc[ctlr]->num_slots) { |
911 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | 909 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
912 | 910 | ||
913 | if (mode) { | 911 | if (mode) { |
@@ -945,7 +943,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |||
945 | ctlr = EDMA_CTLR(slot); | 943 | ctlr = EDMA_CTLR(slot); |
946 | slot = EDMA_CHAN_SLOT(slot); | 944 | slot = EDMA_CHAN_SLOT(slot); |
947 | 945 | ||
948 | if (slot < edma_info[ctlr]->num_slots) { | 946 | if (slot < edma_cc[ctlr]->num_slots) { |
949 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | 947 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
950 | 948 | ||
951 | if (mode) { | 949 | if (mode) { |
@@ -1005,7 +1003,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |||
1005 | ctlr = EDMA_CTLR(slot); | 1003 | ctlr = EDMA_CTLR(slot); |
1006 | slot = EDMA_CHAN_SLOT(slot); | 1004 | slot = EDMA_CHAN_SLOT(slot); |
1007 | 1005 | ||
1008 | if (slot < edma_info[ctlr]->num_slots) { | 1006 | if (slot < edma_cc[ctlr]->num_slots) { |
1009 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | 1007 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
1010 | 0xffff0000, src_bidx); | 1008 | 0xffff0000, src_bidx); |
1011 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, | 1009 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
@@ -1031,7 +1029,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |||
1031 | ctlr = EDMA_CTLR(slot); | 1029 | ctlr = EDMA_CTLR(slot); |
1032 | slot = EDMA_CHAN_SLOT(slot); | 1030 | slot = EDMA_CHAN_SLOT(slot); |
1033 | 1031 | ||
1034 | if (slot < edma_info[ctlr]->num_slots) { | 1032 | if (slot < edma_cc[ctlr]->num_slots) { |
1035 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | 1033 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
1036 | 0x0000ffff, dest_bidx << 16); | 1034 | 0x0000ffff, dest_bidx << 16); |
1037 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, | 1035 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
@@ -1078,7 +1076,7 @@ void edma_set_transfer_params(unsigned slot, | |||
1078 | ctlr = EDMA_CTLR(slot); | 1076 | ctlr = EDMA_CTLR(slot); |
1079 | slot = EDMA_CHAN_SLOT(slot); | 1077 | slot = EDMA_CHAN_SLOT(slot); |
1080 | 1078 | ||
1081 | if (slot < edma_info[ctlr]->num_slots) { | 1079 | if (slot < edma_cc[ctlr]->num_slots) { |
1082 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, | 1080 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
1083 | 0x0000ffff, bcnt_rld << 16); | 1081 | 0x0000ffff, bcnt_rld << 16); |
1084 | if (sync_mode == ASYNC) | 1082 | if (sync_mode == ASYNC) |
@@ -1108,9 +1106,9 @@ void edma_link(unsigned from, unsigned to) | |||
1108 | ctlr_to = EDMA_CTLR(to); | 1106 | ctlr_to = EDMA_CTLR(to); |
1109 | to = EDMA_CHAN_SLOT(to); | 1107 | to = EDMA_CHAN_SLOT(to); |
1110 | 1108 | ||
1111 | if (from >= edma_info[ctlr_from]->num_slots) | 1109 | if (from >= edma_cc[ctlr_from]->num_slots) |
1112 | return; | 1110 | return; |
1113 | if (to >= edma_info[ctlr_to]->num_slots) | 1111 | if (to >= edma_cc[ctlr_to]->num_slots) |
1114 | return; | 1112 | return; |
1115 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, | 1113 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1116 | PARM_OFFSET(to)); | 1114 | PARM_OFFSET(to)); |
@@ -1131,7 +1129,7 @@ void edma_unlink(unsigned from) | |||
1131 | ctlr = EDMA_CTLR(from); | 1129 | ctlr = EDMA_CTLR(from); |
1132 | from = EDMA_CHAN_SLOT(from); | 1130 | from = EDMA_CHAN_SLOT(from); |
1133 | 1131 | ||
1134 | if (from >= edma_info[ctlr]->num_slots) | 1132 | if (from >= edma_cc[ctlr]->num_slots) |
1135 | return; | 1133 | return; |
1136 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); | 1134 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
1137 | } | 1135 | } |
@@ -1158,7 +1156,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |||
1158 | ctlr = EDMA_CTLR(slot); | 1156 | ctlr = EDMA_CTLR(slot); |
1159 | slot = EDMA_CHAN_SLOT(slot); | 1157 | slot = EDMA_CHAN_SLOT(slot); |
1160 | 1158 | ||
1161 | if (slot >= edma_info[ctlr]->num_slots) | 1159 | if (slot >= edma_cc[ctlr]->num_slots) |
1162 | return; | 1160 | return; |
1163 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, | 1161 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1164 | PARM_SIZE); | 1162 | PARM_SIZE); |
@@ -1180,7 +1178,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) | |||
1180 | ctlr = EDMA_CTLR(slot); | 1178 | ctlr = EDMA_CTLR(slot); |
1181 | slot = EDMA_CHAN_SLOT(slot); | 1179 | slot = EDMA_CHAN_SLOT(slot); |
1182 | 1180 | ||
1183 | if (slot >= edma_info[ctlr]->num_slots) | 1181 | if (slot >= edma_cc[ctlr]->num_slots) |
1184 | return; | 1182 | return; |
1185 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), | 1183 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1186 | PARM_SIZE); | 1184 | PARM_SIZE); |
@@ -1205,8 +1203,8 @@ void edma_pause(unsigned channel) | |||
1205 | ctlr = EDMA_CTLR(channel); | 1203 | ctlr = EDMA_CTLR(channel); |
1206 | channel = EDMA_CHAN_SLOT(channel); | 1204 | channel = EDMA_CHAN_SLOT(channel); |
1207 | 1205 | ||
1208 | if (channel < edma_info[ctlr]->num_channels) { | 1206 | if (channel < edma_cc[ctlr]->num_channels) { |
1209 | unsigned int mask = (1 << (channel & 0x1f)); | 1207 | unsigned int mask = BIT(channel & 0x1f); |
1210 | 1208 | ||
1211 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); | 1209 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
1212 | } | 1210 | } |
@@ -1226,8 +1224,8 @@ void edma_resume(unsigned channel) | |||
1226 | ctlr = EDMA_CTLR(channel); | 1224 | ctlr = EDMA_CTLR(channel); |
1227 | channel = EDMA_CHAN_SLOT(channel); | 1225 | channel = EDMA_CHAN_SLOT(channel); |
1228 | 1226 | ||
1229 | if (channel < edma_info[ctlr]->num_channels) { | 1227 | if (channel < edma_cc[ctlr]->num_channels) { |
1230 | unsigned int mask = (1 << (channel & 0x1f)); | 1228 | unsigned int mask = BIT(channel & 0x1f); |
1231 | 1229 | ||
1232 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); | 1230 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
1233 | } | 1231 | } |
@@ -1252,12 +1250,12 @@ int edma_start(unsigned channel) | |||
1252 | ctlr = EDMA_CTLR(channel); | 1250 | ctlr = EDMA_CTLR(channel); |
1253 | channel = EDMA_CHAN_SLOT(channel); | 1251 | channel = EDMA_CHAN_SLOT(channel); |
1254 | 1252 | ||
1255 | if (channel < edma_info[ctlr]->num_channels) { | 1253 | if (channel < edma_cc[ctlr]->num_channels) { |
1256 | int j = channel >> 5; | 1254 | int j = channel >> 5; |
1257 | unsigned int mask = (1 << (channel & 0x1f)); | 1255 | unsigned int mask = BIT(channel & 0x1f); |
1258 | 1256 | ||
1259 | /* EDMA channels without event association */ | 1257 | /* EDMA channels without event association */ |
1260 | if (test_bit(channel, edma_info[ctlr]->edma_unused)) { | 1258 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
1261 | pr_debug("EDMA: ESR%d %08x\n", j, | 1259 | pr_debug("EDMA: ESR%d %08x\n", j, |
1262 | edma_shadow0_read_array(ctlr, SH_ESR, j)); | 1260 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1263 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | 1261 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); |
@@ -1298,9 +1296,9 @@ void edma_stop(unsigned channel) | |||
1298 | ctlr = EDMA_CTLR(channel); | 1296 | ctlr = EDMA_CTLR(channel); |
1299 | channel = EDMA_CHAN_SLOT(channel); | 1297 | channel = EDMA_CHAN_SLOT(channel); |
1300 | 1298 | ||
1301 | if (channel < edma_info[ctlr]->num_channels) { | 1299 | if (channel < edma_cc[ctlr]->num_channels) { |
1302 | int j = channel >> 5; | 1300 | int j = channel >> 5; |
1303 | unsigned int mask = (1 << (channel & 0x1f)); | 1301 | unsigned int mask = BIT(channel & 0x1f); |
1304 | 1302 | ||
1305 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); | 1303 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1306 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | 1304 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); |
@@ -1337,9 +1335,9 @@ void edma_clean_channel(unsigned channel) | |||
1337 | ctlr = EDMA_CTLR(channel); | 1335 | ctlr = EDMA_CTLR(channel); |
1338 | channel = EDMA_CHAN_SLOT(channel); | 1336 | channel = EDMA_CHAN_SLOT(channel); |
1339 | 1337 | ||
1340 | if (channel < edma_info[ctlr]->num_channels) { | 1338 | if (channel < edma_cc[ctlr]->num_channels) { |
1341 | int j = (channel >> 5); | 1339 | int j = (channel >> 5); |
1342 | unsigned int mask = 1 << (channel & 0x1f); | 1340 | unsigned int mask = BIT(channel & 0x1f); |
1343 | 1341 | ||
1344 | pr_debug("EDMA: EMR%d %08x\n", j, | 1342 | pr_debug("EDMA: EMR%d %08x\n", j, |
1345 | edma_read_array(ctlr, EDMA_EMR, j)); | 1343 | edma_read_array(ctlr, EDMA_EMR, j)); |
@@ -1348,7 +1346,7 @@ void edma_clean_channel(unsigned channel) | |||
1348 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | 1346 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
1349 | /* Clear any SER */ | 1347 | /* Clear any SER */ |
1350 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | 1348 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1351 | edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); | 1349 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
1352 | } | 1350 | } |
1353 | } | 1351 | } |
1354 | EXPORT_SYMBOL(edma_clean_channel); | 1352 | EXPORT_SYMBOL(edma_clean_channel); |
@@ -1365,12 +1363,12 @@ void edma_clear_event(unsigned channel) | |||
1365 | ctlr = EDMA_CTLR(channel); | 1363 | ctlr = EDMA_CTLR(channel); |
1366 | channel = EDMA_CHAN_SLOT(channel); | 1364 | channel = EDMA_CHAN_SLOT(channel); |
1367 | 1365 | ||
1368 | if (channel >= edma_info[ctlr]->num_channels) | 1366 | if (channel >= edma_cc[ctlr]->num_channels) |
1369 | return; | 1367 | return; |
1370 | if (channel < 32) | 1368 | if (channel < 32) |
1371 | edma_write(ctlr, EDMA_ECR, 1 << channel); | 1369 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
1372 | else | 1370 | else |
1373 | edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); | 1371 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
1374 | } | 1372 | } |
1375 | EXPORT_SYMBOL(edma_clear_event); | 1373 | EXPORT_SYMBOL(edma_clear_event); |
1376 | 1374 | ||
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev) | |||
1402 | break; | 1400 | break; |
1403 | else | 1401 | else |
1404 | return -ENODEV; | 1402 | return -ENODEV; |
1405 | } else | 1403 | } else { |
1406 | found = 1; | 1404 | found = 1; |
1405 | } | ||
1407 | 1406 | ||
1408 | len[j] = resource_size(r[j]); | 1407 | len[j] = resource_size(r[j]); |
1409 | 1408 | ||
@@ -1420,38 +1419,37 @@ static int __init edma_probe(struct platform_device *pdev) | |||
1420 | goto fail1; | 1419 | goto fail1; |
1421 | } | 1420 | } |
1422 | 1421 | ||
1423 | edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); | 1422 | edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); |
1424 | if (!edma_info[j]) { | 1423 | if (!edma_cc[j]) { |
1425 | status = -ENOMEM; | 1424 | status = -ENOMEM; |
1426 | goto fail1; | 1425 | goto fail1; |
1427 | } | 1426 | } |
1428 | memset(edma_info[j], 0, sizeof(struct edma)); | 1427 | memset(edma_cc[j], 0, sizeof(struct edma)); |
1429 | 1428 | ||
1430 | edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, | 1429 | edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel, |
1431 | EDMA_MAX_DMACH); | 1430 | EDMA_MAX_DMACH); |
1432 | edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, | 1431 | edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot, |
1433 | EDMA_MAX_PARAMENTRY); | 1432 | EDMA_MAX_PARAMENTRY); |
1434 | edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, | 1433 | edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC); |
1435 | EDMA_MAX_CC); | ||
1436 | 1434 | ||
1437 | edma_info[j]->default_queue = info[j].default_queue; | 1435 | edma_cc[j]->default_queue = info[j].default_queue; |
1438 | if (!edma_info[j]->default_queue) | 1436 | if (!edma_cc[j]->default_queue) |
1439 | edma_info[j]->default_queue = EVENTQ_1; | 1437 | edma_cc[j]->default_queue = EVENTQ_1; |
1440 | 1438 | ||
1441 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", | 1439 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1442 | edmacc_regs_base[j]); | 1440 | edmacc_regs_base[j]); |
1443 | 1441 | ||
1444 | for (i = 0; i < edma_info[j]->num_slots; i++) | 1442 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
1445 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), | 1443 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
1446 | &dummy_paramset, PARM_SIZE); | 1444 | &dummy_paramset, PARM_SIZE); |
1447 | 1445 | ||
1448 | /* Mark all channels as unused */ | 1446 | /* Mark all channels as unused */ |
1449 | memset(edma_info[j]->edma_unused, 0xff, | 1447 | memset(edma_cc[j]->edma_unused, 0xff, |
1450 | sizeof(edma_info[j]->edma_unused)); | 1448 | sizeof(edma_cc[j]->edma_unused)); |
1451 | 1449 | ||
1452 | sprintf(irq_name, "edma%d", j); | 1450 | sprintf(irq_name, "edma%d", j); |
1453 | irq[j] = platform_get_irq_byname(pdev, irq_name); | 1451 | irq[j] = platform_get_irq_byname(pdev, irq_name); |
1454 | edma_info[j]->irq_res_start = irq[j]; | 1452 | edma_cc[j]->irq_res_start = irq[j]; |
1455 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", | 1453 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", |
1456 | &pdev->dev); | 1454 | &pdev->dev); |
1457 | if (status < 0) { | 1455 | if (status < 0) { |
@@ -1462,7 +1460,7 @@ static int __init edma_probe(struct platform_device *pdev) | |||
1462 | 1460 | ||
1463 | sprintf(irq_name, "edma%d_err", j); | 1461 | sprintf(irq_name, "edma%d_err", j); |
1464 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | 1462 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); |
1465 | edma_info[j]->irq_res_end = err_irq[j]; | 1463 | edma_cc[j]->irq_res_end = err_irq[j]; |
1466 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, | 1464 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, |
1467 | "edma_error", &pdev->dev); | 1465 | "edma_error", &pdev->dev); |
1468 | if (status < 0) { | 1466 | if (status < 0) { |
@@ -1475,7 +1473,7 @@ static int __init edma_probe(struct platform_device *pdev) | |||
1475 | * specified. This way, long transfers on the low priority queue | 1473 | * specified. This way, long transfers on the low priority queue |
1476 | * started by the codec engine will not cause audio defects. | 1474 | * started by the codec engine will not cause audio defects. |
1477 | */ | 1475 | */ |
1478 | for (i = 0; i < edma_info[j]->num_channels; i++) | 1476 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
1479 | map_dmach_queue(j, i, EVENTQ_1); | 1477 | map_dmach_queue(j, i, EVENTQ_1); |
1480 | 1478 | ||
1481 | queue_tc_mapping = info[j].queue_tc_mapping; | 1479 | queue_tc_mapping = info[j].queue_tc_mapping; |
@@ -1538,7 +1536,7 @@ fail1: | |||
1538 | release_mem_region(r[i]->start, len[i]); | 1536 | release_mem_region(r[i]->start, len[i]); |
1539 | if (edmacc_regs_base[i]) | 1537 | if (edmacc_regs_base[i]) |
1540 | iounmap(edmacc_regs_base[i]); | 1538 | iounmap(edmacc_regs_base[i]); |
1541 | kfree(edma_info[i]); | 1539 | kfree(edma_cc[i]); |
1542 | } | 1540 | } |
1543 | return status; | 1541 | return status; |
1544 | } | 1542 | } |