1 files changed, 310 insertions, 11 deletions

diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 334f0711e0f5..0976049c7b3b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -27,10 +27,20 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
+#include <mach/asp.h>
 
 #include "clock.h"
 #include "mux.h"
 
+#define DAVINCI_VPIF_BASE       (0x01C12000)
+#define VDD3P3V_PWDN_OFFSET     (0x48)
+#define VSCLKDIS_OFFSET         (0x6C)
+
+#define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
+                                        BIT_MASK(0))
+#define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
+                                        BIT_MASK(8))
+
 /*
  * Device specific clocks
  */
@@ -162,6 +172,41 @@ static struct clk arm_clk = {
         .flags = ALWAYS_ENABLED,
 };
 
+static struct clk edma_cc_clk = {
+        .name = "edma_cc",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPCC,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc0_clk = {
+        .name = "edma_tc0",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC0,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc1_clk = {
+        .name = "edma_tc1",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC1,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc2_clk = {
+        .name = "edma_tc2",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC2,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc3_clk = {
+        .name = "edma_tc3",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC3,
+        .flags = ALWAYS_ENABLED,
+};
+
 static struct clk uart0_clk = {
         .name = "uart0",
         .parent = &aux_clkin,
@@ -192,6 +237,18 @@ static struct clk gpio_clk = {
         .lpsc = DM646X_LPSC_GPIO,
 };
 
+static struct clk mcasp0_clk = {
+        .name = "mcasp0",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_McASP0,
+};
+
+static struct clk mcasp1_clk = {
+        .name = "mcasp1",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_McASP1,
+};
+
 static struct clk aemif_clk = {
         .name = "aemif",
         .parent = &pll1_sysclk3,
@@ -237,6 +294,13 @@ static struct clk timer2_clk = {
         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 };
 
+
+static struct clk ide_clk = {
+        .name = "ide",
+        .parent = &pll1_sysclk4,
+        .lpsc = DAVINCI_LPSC_ATA,
+};
+
 static struct clk vpif0_clk = {
         .name = "vpif0",
         .parent = &ref_clk,
@@ -269,11 +333,18 @@ struct davinci_clk dm646x_clks[] = {
         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
         CLK(NULL, "dsp", &dsp_clk),
         CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "edma_cc", &edma_cc_clk),
+        CLK(NULL, "edma_tc0", &edma_tc0_clk),
+        CLK(NULL, "edma_tc1", &edma_tc1_clk),
+        CLK(NULL, "edma_tc2", &edma_tc2_clk),
+        CLK(NULL, "edma_tc3", &edma_tc3_clk),
         CLK(NULL, "uart0", &uart0_clk),
         CLK(NULL, "uart1", &uart1_clk),
         CLK(NULL, "uart2", &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK(NULL, "gpio", &gpio_clk),
+        CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
+        CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
         CLK(NULL, "aemif", &aemif_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
         CLK(NULL, "pwm0", &pwm0_clk),
@@ -281,6 +352,7 @@ struct davinci_clk dm646x_clks[] = {
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
         CLK("watchdog", NULL, &timer2_clk),
+        CLK("palm_bk3710", NULL, &ide_clk),
         CLK(NULL, "vpif0", &vpif0_clk),
         CLK(NULL, "vpif1", &vpif1_clk),
         CLK(NULL, NULL, NULL),
@@ -344,7 +416,7 @@ static struct platform_device dm646x_emac_device = {
  */
 static const struct mux_config dm646x_pins[] = {
 #ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
+MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 
 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 
@@ -451,17 +523,43 @@ static const s8 dma_chan_dm646x_no_event[] = {
         -1
 };
 
-static struct edma_soc_info dm646x_edma_info = {
-        .n_channel      = 64,
-        .n_region       = 6,    /* 0-1, 4-7 */
-        .n_slot         = 512,
-        .n_tc           = 4,
-        .noevent        = dma_chan_dm646x_no_event,
+/* Four Transfer Controllers on DM646x */
+static const s8
+dm646x_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {2, 2},
+        {3, 3},
+        {-1, -1},
+};
+
+static const s8
+dm646x_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 4},
+        {1, 0},
+        {2, 5},
+        {3, 1},
+        {-1, -1},
+};
+
+static struct edma_soc_info dm646x_edma_info[] = {
+        {
+                .n_channel              = 64,
+                .n_region               = 6,    /* 0-1, 4-7 */
+                .n_slot                 = 512,
+                .n_tc                   = 4,
+                .n_cc                   = 1,
+                .noevent                = dma_chan_dm646x_no_event,
+                .queue_tc_mapping       = dm646x_queue_tc_mapping,
+                .queue_priority_mapping = dm646x_queue_priority_mapping,
+        },
 };
 
 static struct resource edma_resources[] = {
         {
-                .name   = "edma_cc",
+                .name   = "edma_cc0",
                 .start  = 0x01c00000,
                 .end    = 0x01c00000 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
@@ -491,10 +589,12 @@ static struct resource edma_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
+                .name   = "edma0",
                 .start  = IRQ_CCINT0,
                 .flags  = IORESOURCE_IRQ,
         },
         {
+                .name   = "edma0_err",
                 .start  = IRQ_CCERRINT,
                 .flags  = IORESOURCE_IRQ,
         },
@@ -503,12 +603,167 @@ static struct resource edma_resources[] = {
 
 static struct platform_device dm646x_edma_device = {
         .name                   = "edma",
-        .id                     = -1,
-        .dev.platform_data      = &dm646x_edma_info,
+        .id                     = 0,
+        .dev.platform_data      = dm646x_edma_info,
         .num_resources          = ARRAY_SIZE(edma_resources),
         .resource               = edma_resources,
 };
 
+static struct resource ide_resources[] = {
+        {
+                .start          = DM646X_ATA_REG_BASE,
+                .end            = DM646X_ATA_REG_BASE + 0x7ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IRQ_DM646X_IDE,
+                .end            = IRQ_DM646X_IDE,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ide_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_dev = {
+        .name           = "palm_bk3710",
+        .id             = -1,
+        .resource       = ide_resources,
+        .num_resources  = ARRAY_SIZE(ide_resources),
+        .dev = {
+                .dma_mask               = &ide_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource dm646x_mcasp0_resources[] = {
+        {
+                .name   = "mcasp0",
+                .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
+                .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* first TX, then RX */
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
+                .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
+                .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource dm646x_mcasp1_resources[] = {
+        {
+                .name   = "mcasp1",
+                .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
+                .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* DIT mode, only TX event */
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
+                .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
+                .flags  = IORESOURCE_DMA,
+        },
+        /* DIT mode, dummy entry */
+        {
+                .start  = -1,
+                .end    = -1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm646x_mcasp0_device = {
+        .name           = "davinci-mcasp",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
+        .resource       = dm646x_mcasp0_resources,
+};
+
+static struct platform_device dm646x_mcasp1_device = {
+        .name           = "davinci-mcasp",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
+        .resource       = dm646x_mcasp1_resources,
+};
+
+static struct platform_device dm646x_dit_device = {
+        .name   = "spdif-dit",
+        .id     = -1,
+};
+
+static u64 vpif_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource vpif_resource[] = {
+        {
+                .start  = DAVINCI_VPIF_BASE,
+                .end    = DAVINCI_VPIF_BASE + 0x03ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device vpif_dev = {
+        .name           = "vpif",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_resource,
+        .num_resources  = ARRAY_SIZE(vpif_resource),
+};
+
+static struct resource vpif_display_resource[] = {
+        {
+                .start = IRQ_DM646X_VP_VERTINT2,
+                .end   = IRQ_DM646X_VP_VERTINT2,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_DM646X_VP_VERTINT3,
+                .end   = IRQ_DM646X_VP_VERTINT3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device vpif_display_dev = {
+        .name           = "vpif_display",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_display_resource,
+        .num_resources  = ARRAY_SIZE(vpif_display_resource),
+};
+
+static struct resource vpif_capture_resource[] = {
+        {
+                .start = IRQ_DM646X_VP_VERTINT0,
+                .end   = IRQ_DM646X_VP_VERTINT0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_DM646X_VP_VERTINT1,
+                .end   = IRQ_DM646X_VP_VERTINT1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device vpif_capture_dev = {
+        .name           = "vpif_capture",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_capture_resource,
+        .num_resources  = ARRAY_SIZE(vpif_capture_resource),
+};
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm646x_io_desc[] = {
@@ -609,7 +864,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
         .intc_irq_prios         = dm646x_default_priorities,
         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm646x_timer_info,
-        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
         .gpio_num               = 43, /* Only 33 usable */
         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
@@ -619,6 +873,51 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
         .sram_len               = SZ_32K,
 };
 
+void __init dm646x_init_ide()
+{
+        davinci_cfg_reg(DM646X_ATAEN);
+        platform_device_register(&ide_dev);
+}
+
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
+{
+        dm646x_mcasp0_device.dev.platform_data = pdata;
+        platform_device_register(&dm646x_mcasp0_device);
+}
+
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
+{
+        dm646x_mcasp1_device.dev.platform_data = pdata;
+        platform_device_register(&dm646x_mcasp1_device);
+        platform_device_register(&dm646x_dit_device);
+}
+
+void dm646x_setup_vpif(struct vpif_display_config *display_config,
+                       struct vpif_capture_config *capture_config)
+{
+        unsigned int value;
+        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+
+        value = __raw_readl(base + VSCLKDIS_OFFSET);
+        value &= ~VSCLKDIS_MASK;
+        __raw_writel(value, base + VSCLKDIS_OFFSET);
+
+        value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
+        value &= ~VDD3P3V_VID_MASK;
+        __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
+
+        davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
+        davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
+        davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
+        davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
+
+        vpif_display_dev.dev.platform_data = display_config;
+        vpif_capture_dev.dev.platform_data = capture_config;
+        platform_device_register(&vpif_dev);
+        platform_device_register(&vpif_display_dev);
+        platform_device_register(&vpif_capture_dev);
+}
+
 void __init dm646x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm646x);