diff options
Diffstat (limited to 'arch/arm/mach-davinci/dm646x.c')
-rw-r--r-- | arch/arm/mach-davinci/dm646x.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 299d8d9d26e0..beb522e8a1a5 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c | |||
@@ -358,6 +358,73 @@ MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) | |||
358 | #endif | 358 | #endif |
359 | }; | 359 | }; |
360 | 360 | ||
361 | static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { | ||
362 | [IRQ_DM646X_VP_VERTINT0] = 7, | ||
363 | [IRQ_DM646X_VP_VERTINT1] = 7, | ||
364 | [IRQ_DM646X_VP_VERTINT2] = 7, | ||
365 | [IRQ_DM646X_VP_VERTINT3] = 7, | ||
366 | [IRQ_DM646X_VP_ERRINT] = 7, | ||
367 | [IRQ_DM646X_RESERVED_1] = 7, | ||
368 | [IRQ_DM646X_RESERVED_2] = 7, | ||
369 | [IRQ_DM646X_WDINT] = 7, | ||
370 | [IRQ_DM646X_CRGENINT0] = 7, | ||
371 | [IRQ_DM646X_CRGENINT1] = 7, | ||
372 | [IRQ_DM646X_TSIFINT0] = 7, | ||
373 | [IRQ_DM646X_TSIFINT1] = 7, | ||
374 | [IRQ_DM646X_VDCEINT] = 7, | ||
375 | [IRQ_DM646X_USBINT] = 7, | ||
376 | [IRQ_DM646X_USBDMAINT] = 7, | ||
377 | [IRQ_DM646X_PCIINT] = 7, | ||
378 | [IRQ_CCINT0] = 7, /* dma */ | ||
379 | [IRQ_CCERRINT] = 7, /* dma */ | ||
380 | [IRQ_TCERRINT0] = 7, /* dma */ | ||
381 | [IRQ_TCERRINT] = 7, /* dma */ | ||
382 | [IRQ_DM646X_TCERRINT2] = 7, | ||
383 | [IRQ_DM646X_TCERRINT3] = 7, | ||
384 | [IRQ_DM646X_IDE] = 7, | ||
385 | [IRQ_DM646X_HPIINT] = 7, | ||
386 | [IRQ_DM646X_EMACRXTHINT] = 7, | ||
387 | [IRQ_DM646X_EMACRXINT] = 7, | ||
388 | [IRQ_DM646X_EMACTXINT] = 7, | ||
389 | [IRQ_DM646X_EMACMISCINT] = 7, | ||
390 | [IRQ_DM646X_MCASP0TXINT] = 7, | ||
391 | [IRQ_DM646X_MCASP0RXINT] = 7, | ||
392 | [IRQ_AEMIFINT] = 7, | ||
393 | [IRQ_DM646X_RESERVED_3] = 7, | ||
394 | [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ | ||
395 | [IRQ_TINT0_TINT34] = 7, /* clocksource */ | ||
396 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | ||
397 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | ||
398 | [IRQ_PWMINT0] = 7, | ||
399 | [IRQ_PWMINT1] = 7, | ||
400 | [IRQ_DM646X_VLQINT] = 7, | ||
401 | [IRQ_I2C] = 7, | ||
402 | [IRQ_UARTINT0] = 7, | ||
403 | [IRQ_UARTINT1] = 7, | ||
404 | [IRQ_DM646X_UARTINT2] = 7, | ||
405 | [IRQ_DM646X_SPINT0] = 7, | ||
406 | [IRQ_DM646X_SPINT1] = 7, | ||
407 | [IRQ_DM646X_DSP2ARMINT] = 7, | ||
408 | [IRQ_DM646X_RESERVED_4] = 7, | ||
409 | [IRQ_DM646X_PSCINT] = 7, | ||
410 | [IRQ_DM646X_GPIO0] = 7, | ||
411 | [IRQ_DM646X_GPIO1] = 7, | ||
412 | [IRQ_DM646X_GPIO2] = 7, | ||
413 | [IRQ_DM646X_GPIO3] = 7, | ||
414 | [IRQ_DM646X_GPIO4] = 7, | ||
415 | [IRQ_DM646X_GPIO5] = 7, | ||
416 | [IRQ_DM646X_GPIO6] = 7, | ||
417 | [IRQ_DM646X_GPIO7] = 7, | ||
418 | [IRQ_DM646X_GPIOBNK0] = 7, | ||
419 | [IRQ_DM646X_GPIOBNK1] = 7, | ||
420 | [IRQ_DM646X_GPIOBNK2] = 7, | ||
421 | [IRQ_DM646X_DDRINT] = 7, | ||
422 | [IRQ_DM646X_AEMIFINT] = 7, | ||
423 | [IRQ_COMMTX] = 7, | ||
424 | [IRQ_COMMRX] = 7, | ||
425 | [IRQ_EMUINT] = 7, | ||
426 | }; | ||
427 | |||
361 | /*----------------------------------------------------------------------*/ | 428 | /*----------------------------------------------------------------------*/ |
362 | 429 | ||
363 | static const s8 dma_chan_dm646x_no_event[] = { | 430 | static const s8 dma_chan_dm646x_no_event[] = { |
@@ -483,6 +550,10 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { | |||
483 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), | 550 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), |
484 | .pinmux_pins = dm646x_pins, | 551 | .pinmux_pins = dm646x_pins, |
485 | .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), | 552 | .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), |
553 | .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), | ||
554 | .intc_type = DAVINCI_INTC_TYPE_AINTC, | ||
555 | .intc_irq_prios = dm646x_default_priorities, | ||
556 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | ||
486 | }; | 557 | }; |
487 | 558 | ||
488 | void __init dm646x_init(void) | 559 | void __init dm646x_init(void) |