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Diffstat (limited to 'arch/arm/mach-davinci/dm365.c')
-rw-r--r--arch/arm/mach-davinci/dm365.c34
1 files changed, 20 insertions, 14 deletions
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee583f65c..a146849d78f0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -467,11 +467,6 @@ static struct clk_lookup dm365_clks[] = {
467 467
468/*----------------------------------------------------------------------*/ 468/*----------------------------------------------------------------------*/
469 469
470#define PINMUX0 0x00
471#define PINMUX1 0x04
472#define PINMUX2 0x08
473#define PINMUX3 0x0c
474#define PINMUX4 0x10
475#define INTMUX 0x18 470#define INTMUX 0x18
476#define EVTMUX 0x1c 471#define EVTMUX 0x1c
477 472
@@ -490,11 +485,14 @@ MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
490MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) 485MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
491MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) 486MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
492 487
493MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) 488MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
489MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
494MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) 490MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
495MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) 491MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
496MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) 492MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
497MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) 493MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
494MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
495MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
498 496
499MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) 497MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
500MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) 498MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
@@ -573,9 +571,17 @@ MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
573MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) 571MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
574MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) 572MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
575 573
574MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
575MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
576MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
577
576MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) 578MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
579MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
580MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
581MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
577MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) 582MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
578MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) 583MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
584MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
579 585
580MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) 586MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
581MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) 587MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
@@ -1006,11 +1012,9 @@ static struct davinci_id dm365_ids[] = {
1006 }, 1012 },
1007}; 1013};
1008 1014
1009static void __iomem *dm365_psc_bases[] = { 1015static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1010 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
1011};
1012 1016
1013struct davinci_timer_info dm365_timer_info = { 1017static struct davinci_timer_info dm365_timer_info = {
1014 .timers = davinci_timer_instance, 1018 .timers = davinci_timer_instance,
1015 .clockevent_id = T0_BOT, 1019 .clockevent_id = T0_BOT,
1016 .clocksource_id = T0_TOP, 1020 .clocksource_id = T0_TOP,
@@ -1049,21 +1053,22 @@ static struct platform_device dm365_serial_device = {
1049static struct davinci_soc_info davinci_soc_info_dm365 = { 1053static struct davinci_soc_info davinci_soc_info_dm365 = {
1050 .io_desc = dm365_io_desc, 1054 .io_desc = dm365_io_desc,
1051 .io_desc_num = ARRAY_SIZE(dm365_io_desc), 1055 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
1052 .jtag_id_base = IO_ADDRESS(0x01c40028), 1056 .jtag_id_reg = 0x01c40028,
1053 .ids = dm365_ids, 1057 .ids = dm365_ids,
1054 .ids_num = ARRAY_SIZE(dm365_ids), 1058 .ids_num = ARRAY_SIZE(dm365_ids),
1055 .cpu_clks = dm365_clks, 1059 .cpu_clks = dm365_clks,
1056 .psc_bases = dm365_psc_bases, 1060 .psc_bases = dm365_psc_bases,
1057 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), 1061 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
1058 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), 1062 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1059 .pinmux_pins = dm365_pins, 1063 .pinmux_pins = dm365_pins,
1060 .pinmux_pins_num = ARRAY_SIZE(dm365_pins), 1064 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
1061 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), 1065 .intc_base = DAVINCI_ARM_INTC_BASE,
1062 .intc_type = DAVINCI_INTC_TYPE_AINTC, 1066 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1063 .intc_irq_prios = dm365_default_priorities, 1067 .intc_irq_prios = dm365_default_priorities,
1064 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 1068 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1065 .timer_info = &dm365_timer_info, 1069 .timer_info = &dm365_timer_info,
1066 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 1070 .gpio_type = GPIO_TYPE_DAVINCI,
1071 .gpio_base = DAVINCI_GPIO_BASE,
1067 .gpio_num = 104, 1072 .gpio_num = 104,
1068 .gpio_irq = IRQ_DM365_GPIO0, 1073 .gpio_irq = IRQ_DM365_GPIO0,
1069 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ 1074 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
@@ -1071,6 +1076,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
1071 .emac_pdata = &dm365_emac_pdata, 1076 .emac_pdata = &dm365_emac_pdata,
1072 .sram_dma = 0x00010000, 1077 .sram_dma = 0x00010000,
1073 .sram_len = SZ_32K, 1078 .sram_len = SZ_32K,
1079 .reset_device = &davinci_wdt_device,
1074}; 1080};
1075 1081
1076void __init dm365_init_asp(struct snd_platform_data *pdata) 1082void __init dm365_init_asp(struct snd_platform_data *pdata)