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-rw-r--r--arch/arm/mach-davinci/da850.c39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index c5efc515df4f..e440c09c5576 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -290,6 +290,13 @@ static struct clk emac_clk = {
290 .psc_ctlr = 1, 290 .psc_ctlr = 1,
291}; 291};
292 292
293static struct clk mcasp_clk = {
294 .name = "mcasp",
295 .parent = &pll0_sysclk2,
296 .lpsc = DA8XX_LPSC1_McASP0,
297 .psc_ctlr = 1,
298};
299
293static struct davinci_clk da850_clks[] = { 300static struct davinci_clk da850_clks[] = {
294 CLK(NULL, "ref", &ref_clk), 301 CLK(NULL, "ref", &ref_clk),
295 CLK(NULL, "pll0", &pll0_clk), 302 CLK(NULL, "pll0", &pll0_clk),
@@ -327,6 +334,7 @@ static struct davinci_clk da850_clks[] = {
327 CLK(NULL, "arm", &arm_clk), 334 CLK(NULL, "arm", &arm_clk),
328 CLK(NULL, "rmii", &rmii_clk), 335 CLK(NULL, "rmii", &rmii_clk),
329 CLK("davinci_emac.1", NULL, &emac_clk), 336 CLK("davinci_emac.1", NULL, &emac_clk),
337 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
330 CLK(NULL, NULL, NULL), 338 CLK(NULL, NULL, NULL),
331}; 339};
332 340
@@ -373,6 +381,30 @@ static const struct mux_config da850_pins[] = {
373 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 381 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
374 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 382 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
375 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 383 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
384 /* McASP function */
385 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
386 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
387 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
388 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
389 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
390 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
391 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
392 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
393 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
394 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
395 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
396 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
397 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
398 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
399 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
400 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
401 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
402 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
403 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
404 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
405 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
406 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
407 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
376#endif 408#endif
377}; 409};
378 410
@@ -410,6 +442,13 @@ const short da850_cpgmac_pins[] __initdata = {
410 -1 442 -1
411}; 443};
412 444
445const short da850_mcasp_pins[] __initdata = {
446 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
447 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
448 DA850_AXR_11, DA850_AXR_12,
449 -1
450};
451
413/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 452/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
414static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { 453static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
415 [IRQ_DA8XX_COMMTX] = 7, 454 [IRQ_DA8XX_COMMTX] = 7,