1 files changed, 74 insertions, 16 deletions

diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 717806c6cef9..d0fd7566712a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -26,6 +26,7 @@
 #include <mach/time.h>
 #include <mach/da8xx.h>
 #include <mach/cpufreq.h>
+#include <mach/pm.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -40,6 +41,7 @@
 #define DA850_REF_FREQ          24000000
 
 #define CFGCHIP3_ASYNC3_CLKSRC  BIT(4)
+#define CFGCHIP3_PLL1_MASTER_LOCK       BIT(5)
 #define CFGCHIP0_PLL_MASTER_LOCK        BIT(4)
 
 static int da850_set_armrate(struct clk *clk, unsigned long rate);
@@ -333,7 +335,7 @@ static struct clk aemif_clk = {
         .flags          = ALWAYS_ENABLED,
 };
 
-static struct davinci_clk da850_clks[] = {
+static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
         CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
@@ -535,6 +537,7 @@ static const struct mux_config da850_pins[] = {
         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+        MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 #endif
 };
 
@@ -770,6 +773,12 @@ static struct map_desc da850_io_desc[] = {
                 .length         = DA8XX_CP_INTC_SIZE,
                 .type           = MT_DEVICE
         },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE
+        },
 };
 
 static void __iomem *da850_psc_bases[] = {
@@ -825,12 +834,12 @@ static struct davinci_timer_info da850_timer_info = {
 static void da850_set_async3_src(int pllnum)
 {
         struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
-        struct davinci_clk *c;
+        struct clk_lookup *c;
         unsigned int v;
         int ret;
 
-        for (c = da850_clks; c->lk.clk; c++) {
-                clk = c->lk.clk;
+        for (c = da850_clks; c->clk; c++) {
+                clk = c->clk;
                 if (clk->flags & DA850_CLK_ASYNC3) {
                         ret = clk_set_parent(clk, newparent);
                         WARN(ret, "DA850: unable to re-parent clock %s",
@@ -838,12 +847,12 @@ static void da850_set_async3_src(int pllnum)
                 }
        }
 
-        v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
         if (pllnum)
                 v |= CFGCHIP3_ASYNC3_CLKSRC;
         else
                 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
-        __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 }
 
 #ifdef CONFIG_CPU_FREQ
@@ -987,7 +996,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         unsigned int prediv, mult, postdiv;
         struct da850_opp *opp;
         struct pll_data *pll = clk->pll_data;
-        unsigned int v;
         int ret;
 
         opp = (struct da850_opp *) da850_freq_table[index].index;
@@ -995,11 +1003,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         mult = opp->mult;
         postdiv = opp->postdiv;
 
-        /* Unlock writing to PLL registers */
-        v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
-        v &= ~CFGCHIP0_PLL_MASTER_LOCK;
-        __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
-
         ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
         if (WARN_ON(ret))
                 return ret;
@@ -1028,6 +1031,43 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 }
 #endif
 
+int da850_register_pm(struct platform_device *pdev)
+{
+        int ret;
+        struct davinci_pm_config *pdata = pdev->dev.platform_data;
+
+        ret = davinci_cfg_reg(DA850_RTC_ALARM);
+        if (ret)
+                return ret;
+
+        pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
+        pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
+        pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
+
+        pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+        if (!pdata->cpupll_reg_base)
+                return -ENOMEM;
+
+        pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
+        if (!pdata->ddrpll_reg_base) {
+                ret = -ENOMEM;
+                goto no_ddrpll_mem;
+        }
+
+        pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
+        if (!pdata->ddrpsc_reg_base) {
+                ret = -ENOMEM;
+                goto no_ddrpsc_mem;
+        }
+
+        return platform_device_register(pdev);
+
+no_ddrpsc_mem:
+        iounmap(pdata->ddrpll_reg_base);
+no_ddrpll_mem:
+        iounmap(pdata->cpupll_reg_base);
+        return ret;
+}
 
 static struct davinci_soc_info davinci_soc_info_da850 = {
         .io_desc                = da850_io_desc,
@@ -1049,17 +1089,25 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
         .gpio_irq               = IRQ_DA8XX_GPIO0,
         .serial_dev             = &da8xx_serial_device,
         .emac_pdata             = &da8xx_emac_pdata,
+        .sram_dma               = DA8XX_ARM_RAM_BASE,
+        .sram_len               = SZ_8K,
 };
 
 void __init da850_init(void)
 {
-        da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
-        if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
+        unsigned int v;
+
+        da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+        if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
+                return;
+
+        da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
+        if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
                 return;
 
         davinci_soc_info_da850.jtag_id_base =
-                                        DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
-        davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
+                                        DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
+        davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
         davinci_common_init(&davinci_soc_info_da850);
 
@@ -1071,4 +1119,14 @@ void __init da850_init(void)
          * be any noticible change even in non-DVFS use cases.
          */
         da850_set_async3_src(1);
+
+        /* Unlock writing to PLL0 registers */
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
+        v &= ~CFGCHIP0_PLL_MASTER_LOCK;
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
+
+        /* Unlock writing to PLL1 registers */
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+        v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 }