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-rw-r--r--arch/arm/mach-davinci/clock.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a61150325..01e36483ac3d 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
76 u32 num; 76 u32 num;
77 u32 flags; 77 u32 flags;
78 u32 input_rate; 78 u32 input_rate;
79 u32 div_ratio_mask;
79}; 80};
80#define PLL_HAS_PREDIV 0x01 81#define PLL_HAS_PREDIV 0x01
81#define PLL_HAS_POSTDIV 0x02 82#define PLL_HAS_POSTDIV 0x02
@@ -101,10 +102,11 @@ struct clk {
101 102
102/* Clock flags: SoC-specific flags start at BIT(16) */ 103/* Clock flags: SoC-specific flags start at BIT(16) */
103#define ALWAYS_ENABLED BIT(1) 104#define ALWAYS_ENABLED BIT(1)
104#define CLK_PSC BIT(2) 105#define CLK_PSC BIT(2)
105#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 106#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
106#define CLK_PLL BIT(4) /* PLL-derived clock */ 107#define CLK_PLL BIT(4) /* PLL-derived clock */
107#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 108#define PRE_PLL BIT(5) /* source is before PLL mult/div */
109#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
108 110
109#define CLK(dev, con, ck) \ 111#define CLK(dev, con, ck) \
110 { \ 112 { \
@@ -118,6 +120,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
118 unsigned int mult, unsigned int postdiv); 120 unsigned int mult, unsigned int postdiv);
119 121
120extern struct platform_device davinci_wdt_device; 122extern struct platform_device davinci_wdt_device;
123extern void davinci_watchdog_reset(struct platform_device *);
121 124
122#endif 125#endif
123 126