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-rw-r--r--arch/arm/mach-davinci/clock.c385
1 files changed, 228 insertions, 157 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index abb92b7eca0c..f0baaa15a57e 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -1,7 +1,8 @@
1/* 1/*
2 * TI DaVinci clock config file 2 * Clock and PLL control for DaVinci devices
3 * 3 *
4 * Copyright (C) 2006 Texas Instruments. 4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/clk.h>
16#include <linux/err.h> 18#include <linux/err.h>
17#include <linux/mutex.h> 19#include <linux/mutex.h>
18#include <linux/platform_device.h> 20#include <linux/platform_device.h>
@@ -21,98 +23,50 @@
21#include <mach/hardware.h> 23#include <mach/hardware.h>
22 24
23#include <mach/psc.h> 25#include <mach/psc.h>
26#include <mach/cputype.h>
24#include "clock.h" 27#include "clock.h"
25 28
26/* PLL/Reset register offsets */
27#define PLLM 0x110
28
29static LIST_HEAD(clocks); 29static LIST_HEAD(clocks);
30static DEFINE_MUTEX(clocks_mutex); 30static DEFINE_MUTEX(clocks_mutex);
31static DEFINE_SPINLOCK(clockfw_lock); 31static DEFINE_SPINLOCK(clockfw_lock);
32 32
33static unsigned int commonrate; 33static unsigned psc_domain(struct clk *clk)
34static unsigned int armrate;
35static unsigned int fixedrate = 27000000; /* 27 MHZ */
36
37extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable);
38
39/*
40 * Returns a clock. Note that we first try to use device id on the bus
41 * and clock name. If this fails, we try to use clock name only.
42 */
43struct clk *clk_get(struct device *dev, const char *id)
44{ 34{
45 struct clk *p, *clk = ERR_PTR(-ENOENT); 35 return (clk->flags & PSC_DSP)
46 int idno; 36 ? DAVINCI_GPSC_DSPDOMAIN
47 37 : DAVINCI_GPSC_ARMDOMAIN;
48 if (dev == NULL || dev->bus != &platform_bus_type)
49 idno = -1;
50 else
51 idno = to_platform_device(dev)->id;
52
53 mutex_lock(&clocks_mutex);
54
55 list_for_each_entry(p, &clocks, node) {
56 if (p->id == idno &&
57 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
58 clk = p;
59 goto found;
60 }
61 }
62
63 list_for_each_entry(p, &clocks, node) {
64 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
65 clk = p;
66 break;
67 }
68 }
69
70found:
71 mutex_unlock(&clocks_mutex);
72
73 return clk;
74} 38}
75EXPORT_SYMBOL(clk_get);
76 39
77void clk_put(struct clk *clk) 40static void __clk_enable(struct clk *clk)
78{ 41{
79 if (clk && !IS_ERR(clk)) 42 if (clk->parent)
80 module_put(clk->owner); 43 __clk_enable(clk->parent);
81} 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
82EXPORT_SYMBOL(clk_put); 45 davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
83
84static int __clk_enable(struct clk *clk)
85{
86 if (clk->flags & ALWAYS_ENABLED)
87 return 0;
88
89 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
90 return 0;
91} 46}
92 47
93static void __clk_disable(struct clk *clk) 48static void __clk_disable(struct clk *clk)
94{ 49{
95 if (clk->usecount) 50 if (WARN_ON(clk->usecount == 0))
96 return; 51 return;
97 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
98 davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); 53 davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
54 if (clk->parent)
55 __clk_disable(clk->parent);
99} 56}
100 57
101int clk_enable(struct clk *clk) 58int clk_enable(struct clk *clk)
102{ 59{
103 unsigned long flags; 60 unsigned long flags;
104 int ret = 0;
105 61
106 if (clk == NULL || IS_ERR(clk)) 62 if (clk == NULL || IS_ERR(clk))
107 return -EINVAL; 63 return -EINVAL;
108 64
109 if (clk->usecount++ == 0) { 65 spin_lock_irqsave(&clockfw_lock, flags);
110 spin_lock_irqsave(&clockfw_lock, flags); 66 __clk_enable(clk);
111 ret = __clk_enable(clk); 67 spin_unlock_irqrestore(&clockfw_lock, flags);
112 spin_unlock_irqrestore(&clockfw_lock, flags);
113 }
114 68
115 return ret; 69 return 0;
116} 70}
117EXPORT_SYMBOL(clk_enable); 71EXPORT_SYMBOL(clk_enable);
118 72
@@ -123,11 +77,9 @@ void clk_disable(struct clk *clk)
123 if (clk == NULL || IS_ERR(clk)) 77 if (clk == NULL || IS_ERR(clk))
124 return; 78 return;
125 79
126 if (clk->usecount > 0 && !(--clk->usecount)) { 80 spin_lock_irqsave(&clockfw_lock, flags);
127 spin_lock_irqsave(&clockfw_lock, flags); 81 __clk_disable(clk);
128 __clk_disable(clk); 82 spin_unlock_irqrestore(&clockfw_lock, flags);
129 spin_unlock_irqrestore(&clockfw_lock, flags);
130 }
131} 83}
132EXPORT_SYMBOL(clk_disable); 84EXPORT_SYMBOL(clk_disable);
133 85
@@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk)
136 if (clk == NULL || IS_ERR(clk)) 88 if (clk == NULL || IS_ERR(clk))
137 return -EINVAL; 89 return -EINVAL;
138 90
139 return *(clk->rate); 91 return clk->rate;
140} 92}
141EXPORT_SYMBOL(clk_get_rate); 93EXPORT_SYMBOL(clk_get_rate);
142 94
@@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
145 if (clk == NULL || IS_ERR(clk)) 97 if (clk == NULL || IS_ERR(clk))
146 return -EINVAL; 98 return -EINVAL;
147 99
148 return *(clk->rate); 100 return clk->rate;
149} 101}
150EXPORT_SYMBOL(clk_round_rate); 102EXPORT_SYMBOL(clk_round_rate);
151 103
@@ -164,10 +116,23 @@ int clk_register(struct clk *clk)
164 if (clk == NULL || IS_ERR(clk)) 116 if (clk == NULL || IS_ERR(clk))
165 return -EINVAL; 117 return -EINVAL;
166 118
119 if (WARN(clk->parent && !clk->parent->rate,
120 "CLK: %s parent %s has no rate!\n",
121 clk->name, clk->parent->name))
122 return -EINVAL;
123
167 mutex_lock(&clocks_mutex); 124 mutex_lock(&clocks_mutex);
168 list_add(&clk->node, &clocks); 125 list_add_tail(&clk->node, &clocks);
169 mutex_unlock(&clocks_mutex); 126 mutex_unlock(&clocks_mutex);
170 127
128 /* If rate is already set, use it */
129 if (clk->rate)
130 return 0;
131
132 /* Otherwise, default to parent rate */
133 if (clk->parent)
134 clk->rate = clk->parent->rate;
135
171 return 0; 136 return 0;
172} 137}
173EXPORT_SYMBOL(clk_register); 138EXPORT_SYMBOL(clk_register);
@@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk)
183} 148}
184EXPORT_SYMBOL(clk_unregister); 149EXPORT_SYMBOL(clk_unregister);
185 150
186static struct clk davinci_clks[] = { 151#ifdef CONFIG_DAVINCI_RESET_CLOCKS
187 { 152/*
188 .name = "ARMCLK", 153 * Disable any unused clocks left on by the bootloader
189 .rate = &armrate, 154 */
190 .lpsc = -1, 155static int __init clk_disable_unused(void)
191 .flags = ALWAYS_ENABLED, 156{
192 }, 157 struct clk *ck;
193 { 158
194 .name = "UART", 159 spin_lock_irq(&clockfw_lock);
195 .rate = &fixedrate, 160 list_for_each_entry(ck, &clocks, node) {
196 .lpsc = DAVINCI_LPSC_UART0, 161 if (ck->usecount > 0)
197 }, 162 continue;
198 { 163 if (!(ck->flags & CLK_PSC))
199 .name = "EMACCLK", 164 continue;
200 .rate = &commonrate, 165
201 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, 166 /* ignore if in Disabled or SwRstDisable states */
202 }, 167 if (!davinci_psc_is_clk_active(ck->lpsc))
203 { 168 continue;
204 .name = "I2CCLK", 169
205 .rate = &fixedrate, 170 pr_info("Clocks: disable unused %s\n", ck->name);
206 .lpsc = DAVINCI_LPSC_I2C, 171 davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
207 },
208 {
209 .name = "IDECLK",
210 .rate = &commonrate,
211 .lpsc = DAVINCI_LPSC_ATA,
212 },
213 {
214 .name = "McBSPCLK",
215 .rate = &commonrate,
216 .lpsc = DAVINCI_LPSC_McBSP,
217 },
218 {
219 .name = "MMCSDCLK",
220 .rate = &commonrate,
221 .lpsc = DAVINCI_LPSC_MMC_SD,
222 },
223 {
224 .name = "SPICLK",
225 .rate = &commonrate,
226 .lpsc = DAVINCI_LPSC_SPI,
227 },
228 {
229 .name = "gpio",
230 .rate = &commonrate,
231 .lpsc = DAVINCI_LPSC_GPIO,
232 },
233 {
234 .name = "usb",
235 .rate = &commonrate,
236 .lpsc = DAVINCI_LPSC_USB,
237 },
238 {
239 .name = "AEMIFCLK",
240 .rate = &commonrate,
241 .lpsc = DAVINCI_LPSC_AEMIF,
242 .usecount = 1,
243 } 172 }
244}; 173 spin_unlock_irq(&clockfw_lock);
174
175 return 0;
176}
177late_initcall(clk_disable_unused);
178#endif
245 179
246int __init davinci_clk_init(void) 180static void clk_sysclk_recalc(struct clk *clk)
247{ 181{
248 struct clk *clkp; 182 u32 v, plldiv;
249 int count = 0; 183 struct pll_data *pll;
250 u32 pll_mult; 184
251 185 /* If this is the PLL base clock, no more calculations needed */
252 pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); 186 if (clk->pll_data)
253 commonrate = ((pll_mult + 1) * 27000000) / 6; 187 return;
254 armrate = ((pll_mult + 1) * 27000000) / 2; 188
255 189 if (WARN_ON(!clk->parent))
256 for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); 190 return;
257 count++, clkp++) { 191
258 clk_register(clkp); 192 clk->rate = clk->parent->rate;
259 193
260 /* Turn on clocks that have been enabled in the 194 /* Otherwise, the parent must be a PLL */
261 * table above */ 195 if (WARN_ON(!clk->parent->pll_data))
262 if (clkp->usecount) 196 return;
263 clk_enable(clkp); 197
198 pll = clk->parent->pll_data;
199
200 /* If pre-PLL, source clock is before the multiplier and divider(s) */
201 if (clk->flags & PRE_PLL)
202 clk->rate = pll->input_rate;
203
204 if (!clk->div_reg)
205 return;
206
207 v = __raw_readl(pll->base + clk->div_reg);
208 if (v & PLLDIV_EN) {
209 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
210 if (plldiv)
211 clk->rate /= plldiv;
212 }
213}
214
215static void __init clk_pll_init(struct clk *clk)
216{
217 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
218 u8 bypass;
219 struct pll_data *pll = clk->pll_data;
220
221 pll->base = IO_ADDRESS(pll->phys_base);
222 ctrl = __raw_readl(pll->base + PLLCTL);
223 clk->rate = pll->input_rate = clk->parent->rate;
224
225 if (ctrl & PLLCTL_PLLEN) {
226 bypass = 0;
227 mult = __raw_readl(pll->base + PLLM);
228 mult = (mult & PLLM_PLLM_MASK) + 1;
229 } else
230 bypass = 1;
231
232 if (pll->flags & PLL_HAS_PREDIV) {
233 prediv = __raw_readl(pll->base + PREDIV);
234 if (prediv & PLLDIV_EN)
235 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
236 else
237 prediv = 1;
238 }
239
240 /* pre-divider is fixed, but (some?) chips won't report that */
241 if (cpu_is_davinci_dm355() && pll->num == 1)
242 prediv = 8;
243
244 if (pll->flags & PLL_HAS_POSTDIV) {
245 postdiv = __raw_readl(pll->base + POSTDIV);
246 if (postdiv & PLLDIV_EN)
247 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
248 else
249 postdiv = 1;
250 }
251
252 if (!bypass) {
253 clk->rate /= prediv;
254 clk->rate *= mult;
255 clk->rate /= postdiv;
256 }
257
258 pr_debug("PLL%d: input = %lu MHz [ ",
259 pll->num, clk->parent->rate / 1000000);
260 if (bypass)
261 pr_debug("bypass ");
262 if (prediv > 1)
263 pr_debug("/ %d ", prediv);
264 if (mult > 1)
265 pr_debug("* %d ", mult);
266 if (postdiv > 1)
267 pr_debug("/ %d ", postdiv);
268 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
269}
270
271int __init davinci_clk_init(struct davinci_clk *clocks)
272 {
273 struct davinci_clk *c;
274 struct clk *clk;
275
276 for (c = clocks; c->lk.clk; c++) {
277 clk = c->lk.clk;
278
279 if (clk->pll_data)
280 clk_pll_init(clk);
281
282 /* Calculate rates for PLL-derived clocks */
283 else if (clk->flags & CLK_PLL)
284 clk_sysclk_recalc(clk);
285
286 if (clk->lpsc)
287 clk->flags |= CLK_PSC;
288
289 clkdev_add(&c->lk);
290 clk_register(clk);
291
292 /* Turn on clocks that Linux doesn't otherwise manage */
293 if (clk->flags & ALWAYS_ENABLED)
294 clk_enable(clk);
264 } 295 }
265 296
266 return 0; 297 return 0;
@@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v)
285{ 316{
286} 317}
287 318
288static int davinci_ck_show(struct seq_file *m, void *v) 319#define CLKNAME_MAX 10 /* longest clock name */
320#define NEST_DELTA 2
321#define NEST_MAX 4
322
323static void
324dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
289{ 325{
290 struct clk *cp; 326 char *state;
327 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
328 struct clk *clk;
329 unsigned i;
330
331 if (parent->flags & CLK_PLL)
332 state = "pll";
333 else if (parent->flags & CLK_PSC)
334 state = "psc";
335 else
336 state = "";
337
338 /* <nest spaces> name <pad to end> */
339 memset(buf, ' ', sizeof(buf) - 1);
340 buf[sizeof(buf) - 1] = 0;
341 i = strlen(parent->name);
342 memcpy(buf + nest, parent->name,
343 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
344
345 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
346 buf, parent->usecount, state, clk_get_rate(parent));
347 /* REVISIT show device associations too */
348
349 /* cost is now small, but not linear... */
350 list_for_each_entry(clk, &clocks, node) {
351 if (clk->parent == parent)
352 dump_clock(s, nest + NEST_DELTA, clk);
353 }
354}
291 355
292 list_for_each_entry(cp, &clocks, node) 356static int davinci_ck_show(struct seq_file *m, void *v)
293 seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); 357{
358 /* Show clock tree; we know the main oscillator is first.
359 * We trust nonzero usecounts equate to PSC enables...
360 */
361 mutex_lock(&clocks_mutex);
362 if (!list_empty(&clocks))
363 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
364 mutex_unlock(&clocks_mutex);
294 365
295 return 0; 366 return 0;
296} 367}
@@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void)
321 392
322} 393}
323__initcall(davinci_ck_proc_init); 394__initcall(davinci_ck_proc_init);
324#endif /* CONFIG_DEBUG_PROC_FS */ 395#endif /* CONFIG_DEBUG_PROC_FS */