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-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c32
1 files changed, 11 insertions, 21 deletions
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 872ac69fa049..d72ab948d630 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -36,7 +36,6 @@
36#include <asm/mach-types.h> 36#include <asm/mach-types.h>
37#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
38 38
39#include <mach/dm646x.h>
40#include <mach/common.h> 39#include <mach/common.h>
41#include <mach/serial.h> 40#include <mach/serial.h>
42#include <mach/i2c.h> 41#include <mach/i2c.h>
@@ -45,6 +44,7 @@
45#include <mach/cdce949.h> 44#include <mach/cdce949.h>
46#include <mach/aemif.h> 45#include <mach/aemif.h>
47 46
47#include "davinci.h"
48#include "clock.h" 48#include "clock.h"
49 49
50#define NAND_BLOCK_SIZE SZ_128K 50#define NAND_BLOCK_SIZE SZ_128K
@@ -410,8 +410,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
410 .bus_delay = 0 /* usec */, 410 .bus_delay = 0 /* usec */,
411}; 411};
412 412
413#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
414#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
415#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) 413#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
416#define VCH2CLK_SYSCLK8 (BIT(9)) 414#define VCH2CLK_SYSCLK8 (BIT(9))
417#define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) 415#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
@@ -429,8 +427,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
429#define TVP5147_CH0 "tvp514x-0" 427#define TVP5147_CH0 "tvp514x-0"
430#define TVP5147_CH1 "tvp514x-1" 428#define TVP5147_CH1 "tvp514x-1"
431 429
432static void __iomem *vpif_vidclkctl_reg;
433static void __iomem *vpif_vsclkdis_reg;
434/* spin lock for updating above registers */ 430/* spin lock for updating above registers */
435static spinlock_t vpif_reg_lock; 431static spinlock_t vpif_reg_lock;
436 432
@@ -441,14 +437,14 @@ static int set_vpif_clock(int mux_mode, int hd)
441 int val = 0; 437 int val = 0;
442 int err = 0; 438 int err = 0;
443 439
444 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client) 440 if (!cpld_client)
445 return -ENXIO; 441 return -ENXIO;
446 442
447 /* disable the clock */ 443 /* disable the clock */
448 spin_lock_irqsave(&vpif_reg_lock, flags); 444 spin_lock_irqsave(&vpif_reg_lock, flags);
449 value = __raw_readl(vpif_vsclkdis_reg); 445 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
450 value |= (VIDCH3CLK | VIDCH2CLK); 446 value |= (VIDCH3CLK | VIDCH2CLK);
451 __raw_writel(value, vpif_vsclkdis_reg); 447 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
452 spin_unlock_irqrestore(&vpif_reg_lock, flags); 448 spin_unlock_irqrestore(&vpif_reg_lock, flags);
453 449
454 val = i2c_smbus_read_byte(cpld_client); 450 val = i2c_smbus_read_byte(cpld_client);
@@ -464,7 +460,7 @@ static int set_vpif_clock(int mux_mode, int hd)
464 if (err) 460 if (err)
465 return err; 461 return err;
466 462
467 value = __raw_readl(vpif_vidclkctl_reg); 463 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
468 value &= ~(VCH2CLK_MASK); 464 value &= ~(VCH2CLK_MASK);
469 value &= ~(VCH3CLK_MASK); 465 value &= ~(VCH3CLK_MASK);
470 466
@@ -473,13 +469,13 @@ static int set_vpif_clock(int mux_mode, int hd)
473 else 469 else
474 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); 470 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
475 471
476 __raw_writel(value, vpif_vidclkctl_reg); 472 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
477 473
478 spin_lock_irqsave(&vpif_reg_lock, flags); 474 spin_lock_irqsave(&vpif_reg_lock, flags);
479 value = __raw_readl(vpif_vsclkdis_reg); 475 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
480 /* enable the clock */ 476 /* enable the clock */
481 value &= ~(VIDCH3CLK | VIDCH2CLK); 477 value &= ~(VIDCH3CLK | VIDCH2CLK);
482 __raw_writel(value, vpif_vsclkdis_reg); 478 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
483 spin_unlock_irqrestore(&vpif_reg_lock, flags); 479 spin_unlock_irqrestore(&vpif_reg_lock, flags);
484 480
485 return 0; 481 return 0;
@@ -564,7 +560,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
564 int val; 560 int val;
565 u32 value; 561 u32 value;
566 562
567 if (!vpif_vidclkctl_reg || !cpld_client) 563 if (!cpld_client)
568 return -ENXIO; 564 return -ENXIO;
569 565
570 val = i2c_smbus_read_byte(cpld_client); 566 val = i2c_smbus_read_byte(cpld_client);
@@ -572,7 +568,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
572 return val; 568 return val;
573 569
574 spin_lock_irqsave(&vpif_reg_lock, flags); 570 spin_lock_irqsave(&vpif_reg_lock, flags);
575 value = __raw_readl(vpif_vidclkctl_reg); 571 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
576 if (mux_mode) { 572 if (mux_mode) {
577 val &= VPIF_INPUT_TWO_CHANNEL; 573 val &= VPIF_INPUT_TWO_CHANNEL;
578 value |= VIDCH1CLK; 574 value |= VIDCH1CLK;
@@ -580,7 +576,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
580 val |= VPIF_INPUT_ONE_CHANNEL; 576 val |= VPIF_INPUT_ONE_CHANNEL;
581 value &= ~VIDCH1CLK; 577 value &= ~VIDCH1CLK;
582 } 578 }
583 __raw_writel(value, vpif_vidclkctl_reg); 579 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
584 spin_unlock_irqrestore(&vpif_reg_lock, flags); 580 spin_unlock_irqrestore(&vpif_reg_lock, flags);
585 581
586 err = i2c_smbus_write_byte(cpld_client, val); 582 err = i2c_smbus_write_byte(cpld_client, val);
@@ -674,12 +670,6 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
674 670
675static void __init evm_init_video(void) 671static void __init evm_init_video(void)
676{ 672{
677 vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
678 vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
679 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
680 pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
681 return;
682 }
683 spin_lock_init(&vpif_reg_lock); 673 spin_lock_init(&vpif_reg_lock);
684 674
685 dm646x_setup_vpif(&dm646x_vpif_display_config, 675 dm646x_setup_vpif(&dm646x_vpif_display_config,