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-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c33
1 files changed, 1 insertions, 32 deletions
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d028bab6f981..73c0b04a75ff 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -41,8 +41,6 @@
41#define DM644X_EVM_PHY_MASK (0x2) 41#define DM644X_EVM_PHY_MASK (0x2)
42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
43 43
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define LXT971_PHY_ID (0x001378e2) 44#define LXT971_PHY_ID (0x001378e2)
47#define LXT971_PHY_MASK (0xfffffff0) 45#define LXT971_PHY_MASK (0xfffffff0)
48 46
@@ -252,32 +250,6 @@ static struct platform_device rtc_dev = {
252 .id = -1, 250 .id = -1,
253}; 251};
254 252
255static struct resource ide_resources[] = {
256 {
257 .start = DAVINCI_CFC_ATA_BASE,
258 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
259 .flags = IORESOURCE_MEM,
260 },
261 {
262 .start = IRQ_IDE,
263 .end = IRQ_IDE,
264 .flags = IORESOURCE_IRQ,
265 },
266};
267
268static u64 ide_dma_mask = DMA_BIT_MASK(32);
269
270static struct platform_device ide_dev = {
271 .name = "palm_bk3710",
272 .id = -1,
273 .resource = ide_resources,
274 .num_resources = ARRAY_SIZE(ide_resources),
275 .dev = {
276 .dma_mask = &ide_dma_mask,
277 .coherent_dma_mask = DMA_BIT_MASK(32),
278 },
279};
280
281static struct snd_platform_data dm644x_evm_snd_data; 253static struct snd_platform_data dm644x_evm_snd_data;
282 254
283/*----------------------------------------------------------------------*/ 255/*----------------------------------------------------------------------*/
@@ -698,10 +670,7 @@ static __init void davinci_evm_init(void)
698 pr_warning("WARNING: both IDE and Flash are " 670 pr_warning("WARNING: both IDE and Flash are "
699 "enabled, but they share AEMIF pins.\n" 671 "enabled, but they share AEMIF pins.\n"
700 "\tDisable IDE for NAND/NOR support.\n"); 672 "\tDisable IDE for NAND/NOR support.\n");
701 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 673 davinci_init_ide();
702 davinci_cfg_reg(DM644X_ATAEN);
703 davinci_cfg_reg(DM644X_HDIREN);
704 platform_device_register(&ide_dev);
705 } else if (HAS_NAND || HAS_NOR) { 674 } else if (HAS_NAND || HAS_NOR) {
706 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 675 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
707 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 676 davinci_cfg_reg(DM644X_ATAEN_DISABLE);