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-rw-r--r--arch/arm/mach-clps711x/include/mach/debug-macro.S5
-rw-r--r--arch/arm/mach-clps711x/include/mach/entry-macro.S3
-rw-r--r--arch/arm/mach-clps711x/include/mach/hardware.h36
-rw-r--r--arch/arm/mach-clps711x/include/mach/time.h2
-rw-r--r--arch/arm/mach-clps711x/include/mach/uncompress.h19
5 files changed, 26 insertions, 39 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index b802e8a51831..118b3d930573 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -12,7 +12,6 @@
12*/ 12*/
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <asm/hardware/clps7111.h>
16 15
17 .macro addruart, rp, rv, tmp 16 .macro addruart, rp, rv, tmp
18#ifndef CONFIG_DEBUG_CLPS711X_UART2 17#ifndef CONFIG_DEBUG_CLPS711X_UART2
@@ -20,8 +19,8 @@
20#else 19#else
21 mov \rp, #0x1000 @ UART2 20 mov \rp, #0x1000 @ UART2
22#endif 21#endif
23 orr \rv, \rp, #CLPS7111_VIRT_BASE 22 orr \rv, \rp, #CLPS711X_VIRT_BASE
24 orr \rp, \rp, #CLPS7111_PHYS_BASE 23 orr \rp, \rp, #CLPS711X_PHYS_BASE
25 .endm 24 .endm
26 25
27 .macro senduart,rd,rx 26 .macro senduart,rd,rx
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
index 125af59d7a29..56e5c2c23504 100644
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <mach/hardware.h> 10#include <mach/hardware.h>
11#include <asm/hardware/clps7111.h>
12 11
13 .macro get_irqnr_preamble, base, tmp 12 .macro get_irqnr_preamble, base, tmp
14 .endm 13 .endm
@@ -18,7 +17,7 @@
18#endif 17#endif
19 18
20 .macro get_irqnr_and_base, irqnr, stat, base, mask 19 .macro get_irqnr_and_base, irqnr, stat, base, mask
21 mov \base, #CLPS7111_BASE 20 mov \base, #CLPS711X_VIRT_BASE
22 ldr \stat, [\base, #INTSR1] 21 ldr \stat, [\base, #INTSR1]
23 ldr \mask, [\base, #INTMR1] 22 ldr \mask, [\base, #INTMR1]
24 mov \irqnr, #4 23 mov \irqnr, #4
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index d0b7d870be9c..1026ac968706 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -19,12 +19,21 @@
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 21 */
22#ifndef __ASM_ARCH_HARDWARE_H 22#ifndef __MACH_HARDWARE_H
23#define __ASM_ARCH_HARDWARE_H 23#define __MACH_HARDWARE_H
24 24
25#include <asm/hardware/clps7111.h>
26
27#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
25 28
26#define CLPS7111_VIRT_BASE 0xff000000 29#ifndef __ASSEMBLY__
27#define CLPS7111_BASE CLPS7111_VIRT_BASE 30#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
31#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off))
32#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off))
33#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off))
34#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off))
35#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off))
36#endif
28 37
29/* 38/*
30 * The physical addresses that the external chip select signals map to is 39 * The physical addresses that the external chip select signals map to is
@@ -54,14 +63,10 @@
54 63
55#if defined (CONFIG_ARCH_EP7211) 64#if defined (CONFIG_ARCH_EP7211)
56 65
57#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
58#define EP7211_BASE CLPS7111_VIRT_BASE
59#include <asm/hardware/ep7211.h> 66#include <asm/hardware/ep7211.h>
60 67
61#elif defined (CONFIG_ARCH_EP7212) 68#elif defined (CONFIG_ARCH_EP7212)
62 69
63#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
64#define EP7212_BASE CLPS7111_VIRT_BASE
65#include <asm/hardware/ep7212.h> 70#include <asm/hardware/ep7212.h>
66 71
67#endif 72#endif
@@ -71,10 +76,6 @@
71 76
72#if defined (CONFIG_ARCH_AUTCPU12) 77#if defined (CONFIG_ARCH_AUTCPU12)
73 78
74#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
75#define CS89712_BASE CLPS7111_VIRT_BASE
76
77#include <asm/hardware/clps7111.h>
78#include <asm/hardware/ep7212.h> 79#include <asm/hardware/ep7212.h>
79#include <asm/hardware/cs89712.h> 80#include <asm/hardware/cs89712.h>
80 81
@@ -83,15 +84,9 @@
83 84
84#if defined (CONFIG_ARCH_CDB89712) 85#if defined (CONFIG_ARCH_CDB89712)
85 86
86#include <asm/hardware/clps7111.h>
87#include <asm/hardware/ep7212.h> 87#include <asm/hardware/ep7212.h>
88#include <asm/hardware/cs89712.h> 88#include <asm/hardware/cs89712.h>
89 89
90/* static cdb89712_map_io() areas */
91#define REGISTER_START 0x80000000
92#define REGISTER_SIZE 0x4000
93#define REGISTER_BASE 0xff000000
94
95#define ETHER_START 0x20000000 90#define ETHER_START 0x20000000
96#define ETHER_SIZE 0x1000 91#define ETHER_SIZE 0x1000
97#define ETHER_BASE 0xfe000000 92#define ETHER_BASE 0xfe000000
@@ -154,13 +149,8 @@
154 149
155#if defined (CONFIG_ARCH_CEIVA) 150#if defined (CONFIG_ARCH_CEIVA)
156 151
157#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
158#define CEIVA_BASE CLPS7111_VIRT_BASE
159
160#include <asm/hardware/clps7111.h>
161#include <asm/hardware/ep7212.h> 152#include <asm/hardware/ep7212.h>
162 153
163
164/* 154/*
165 * The two flash banks are wired to chip selects 0 and 1. This is the mapping 155 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
166 * for them. 156 * for them.
diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h
index 61fef9129c6a..5f65865884ce 100644
--- a/arch/arm/mach-clps711x/include/mach/time.h
+++ b/arch/arm/mach-clps711x/include/mach/time.h
@@ -18,7 +18,7 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <asm/leds.h> 20#include <asm/leds.h>
21#include <asm/hardware/clps7111.h> 21#include <mach/hardware.h>
22 22
23extern void clps711x_setup_timer(void); 23extern void clps711x_setup_timer(void);
24 24
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 35ed731b9f16..263f8393ccb7 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,15 +17,8 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <mach/hardware.h>
21#include <asm/hardware/clps7111.h> 20#include <asm/hardware/clps7111.h>
22 21
23#undef CLPS7111_BASE
24#define CLPS7111_BASE CLPS7111_PHYS_BASE
25
26#define __raw_readl(p) (*(unsigned long *)(p))
27#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
28
29#ifdef CONFIG_DEBUG_CLPS711X_UART2 22#ifdef CONFIG_DEBUG_CLPS711X_UART2
30#define SYSFLGx SYSFLG2 23#define SYSFLGx SYSFLG2
31#define UARTDRx UARTDR2 24#define UARTDRx UARTDR2
@@ -34,19 +27,25 @@
34#define UARTDRx UARTDR1 27#define UARTDRx UARTDR1
35#endif 28#endif
36 29
30#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x)))
31
37/* 32/*
33 * The following code assumes the serial port has already been
34 * initialized by the bootloader. If you didn't setup a port in
35 * your bootloader then nothing will appear (which might be desired).
36 *
38 * This does not append a newline 37 * This does not append a newline
39 */ 38 */
40static inline void putc(int c) 39static inline void putc(int c)
41{ 40{
42 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) 41 while (phys_reg(SYSFLGx) & SYSFLG_UTXFF)
43 barrier(); 42 barrier();
44 clps_writel(c, UARTDRx); 43 phys_reg(UARTDRx) = c;
45} 44}
46 45
47static inline void flush(void) 46static inline void flush(void)
48{ 47{
49 while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) 48 while (phys_reg(SYSFLGx) & SYSFLG_UBUSY)
50 barrier(); 49 barrier();
51} 50}
52 51