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-rw-r--r--arch/arm/mach-bcmring/include/csp/cache.h35
-rw-r--r--arch/arm/mach-bcmring/include/csp/delay.h36
-rw-r--r--arch/arm/mach-bcmring/include/csp/errno.h32
-rw-r--r--arch/arm/mach-bcmring/include/csp/module.h32
-rw-r--r--arch/arm/mach-bcmring/include/csp/reg.h114
-rw-r--r--arch/arm/mach-bcmring/include/csp/stdint.h30
-rw-r--r--arch/arm/mach-bcmring/include/csp/string.h34
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h872
8 files changed, 1185 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
new file mode 100644
index 000000000000..caa20e59db99
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/cache.h
@@ -0,0 +1,35 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_CACHE_H
16#define CSP_CACHE_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#include <csp/stdint.h>
21
22/* ---- Public Constants and Types --------------------------------------- */
23
24#if defined(__KERNEL__) && !defined(STANDALONE)
25#include <asm/cacheflush.h>
26
27#define CSP_CACHE_FLUSH_ALL flush_cache_all()
28
29#else
30
31#define CSP_CACHE_FLUSH_ALL
32
33#endif
34
35#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
new file mode 100644
index 000000000000..8b3d80367293
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/delay.h
@@ -0,0 +1,36 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_DELAY_H
17#define CSP_DELAY_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21/* Some CSP routines require use of the following delay routines. Use the OS */
22/* version if available, otherwise use a CSP specific definition. */
23/* void udelay(unsigned long usecs); */
24/* void mdelay(unsigned long msecs); */
25
26#if defined(__KERNEL__) && !defined(STANDALONE)
27 #include <linux/delay.h>
28#else
29 #include <mach/csp/delay.h>
30#endif
31
32/* ---- Public Constants and Types --------------------------------------- */
33/* ---- Public Variable Externs ------------------------------------------ */
34/* ---- Public Function Prototypes --------------------------------------- */
35
36#endif /* CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
new file mode 100644
index 000000000000..51357dd5b666
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/errno.h
@@ -0,0 +1,32 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_ERRNO_H
16#define CSP_ERRNO_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#if defined(__KERNEL__)
21#include <linux/errno.h>
22#elif defined(CSP_SIMULATION)
23#include <asm-generic/errno.h>
24#else
25#include <errno.h>
26#endif
27
28/* ---- Public Constants and Types --------------------------------------- */
29/* ---- Public Variable Externs ------------------------------------------ */
30/* ---- Public Function Prototypes --------------------------------------- */
31
32#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
new file mode 100644
index 000000000000..c30d2a5975a6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/module.h
@@ -0,0 +1,32 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_MODULE_H
17#define CSP_MODULE_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21#ifdef __KERNEL__
22 #include <linux/module.h>
23#else
24 #define EXPORT_SYMBOL(symbol)
25#endif
26
27/* ---- Public Constants and Types --------------------------------------- */
28/* ---- Public Variable Externs ------------------------------------------ */
29/* ---- Public Function Prototypes --------------------------------------- */
30
31
32#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
new file mode 100644
index 000000000000..e5f60bf5a1f3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -0,0 +1,114 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file reg.h
18*
19* @brief Generic register defintions used in CSP
20*/
21/****************************************************************************/
22
23#ifndef CSP_REG_H
24#define CSP_REG_H
25
26/* ---- Include Files ---------------------------------------------------- */
27
28#include <csp/stdint.h>
29
30/* ---- Public Constants and Types --------------------------------------- */
31
32#define __REG32(x) (*((volatile uint32_t *)(x)))
33#define __REG16(x) (*((volatile uint16_t *)(x)))
34#define __REG8(x) (*((volatile uint8_t *) (x)))
35
36/* Macros used to define a sequence of reserved registers. The start / end */
37/* are byte offsets in the particular register definition, with the "end" */
38/* being the offset of the next un-reserved register. E.g. if offsets */
39/* 0x10 through to 0x1f are reserved, then this reserved area could be */
40/* specified as follows. */
41/* typedef struct */
42/* { */
43/* uint32_t reg1; offset 0x00 */
44/* uint32_t reg2; offset 0x04 */
45/* uint32_t reg3; offset 0x08 */
46/* uint32_t reg4; offset 0x0c */
47/* REG32_RSVD(0x10, 0x20); */
48/* uint32_t reg5; offset 0x20 */
49/* ... */
50/* } EXAMPLE_REG_t; */
51#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
52#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
53#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
54
55/* ---- Public Variable Externs ------------------------------------------ */
56/* ---- Public Function Prototypes --------------------------------------- */
57
58/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
59/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */
60/* flags variable to be declared locally. */
61/* e.g. */
62/* statement1; */
63/* { */
64/* REG_LOCAL_IRQ_SAVE; */
65/* <multiple statements here> */
66/* REG_LOCAL_IRQ_RESTORE; */
67/* } */
68/* statement2; */
69/* */
70
71#if defined(__KERNEL__) && !defined(STANDALONE)
72#include <mach/hardware.h>
73#include <linux/interrupt.h>
74
75#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \
76 unsigned long flags; HW_IRQ_SAVE(reg32, flags)
77
78#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags)
79
80#else
81
82#define REG_LOCAL_IRQ_SAVE
83#define REG_LOCAL_IRQ_RESTORE
84
85#endif
86
87static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
88{
89 REG_LOCAL_IRQ_SAVE;
90 *reg &= value;
91 REG_LOCAL_IRQ_RESTORE;
92}
93
94static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
95{
96 REG_LOCAL_IRQ_SAVE;
97 *reg |= value;
98 REG_LOCAL_IRQ_RESTORE;
99}
100
101static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
102 uint32_t value)
103{
104 REG_LOCAL_IRQ_SAVE;
105 *reg = (*reg & mask) | value;
106 REG_LOCAL_IRQ_RESTORE;
107}
108
109static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
110{
111 *reg = value;
112}
113
114#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
new file mode 100644
index 000000000000..3a8718bbf700
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/stdint.h
@@ -0,0 +1,30 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_STDINT_H
16#define CSP_STDINT_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#ifdef __KERNEL__
21#include <linux/types.h>
22#else
23#include <stdint.h>
24#endif
25
26/* ---- Public Constants and Types --------------------------------------- */
27/* ---- Public Variable Externs ------------------------------------------ */
28/* ---- Public Function Prototypes --------------------------------------- */
29
30#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
new file mode 100644
index 000000000000..ad9e4005f141
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/string.h
@@ -0,0 +1,34 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16
17#ifndef CSP_STRING_H
18#define CSP_STRING_H
19
20/* ---- Include Files ---------------------------------------------------- */
21
22#ifdef __KERNEL__
23 #include <linux/string.h>
24#else
25 #include <string.h>
26#endif
27
28/* ---- Public Constants and Types --------------------------------------- */
29/* ---- Public Variable Externs ------------------------------------------ */
30/* ---- Public Function Prototypes --------------------------------------- */
31
32
33#endif /* CSP_STRING_H */
34
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
new file mode 100644
index 000000000000..f1b68e26fa6d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -0,0 +1,872 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file ddrcReg.h
18*
19* @brief Register definitions for BCMRING DDR2 Controller and PHY
20*
21*/
22/****************************************************************************/
23
24#ifndef DDRC_REG_H
25#define DDRC_REG_H
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/* ---- Include Files ---------------------------------------------------- */
32
33#include <csp/reg.h>
34#include <csp/stdint.h>
35
36#include <mach/csp/mm_io.h>
37
38/* ---- Public Constants and Types --------------------------------------- */
39
40/*********************************************************************/
41/* DDR2 Controller (ARM PL341) register definitions */
42/*********************************************************************/
43
44/* -------------------------------------------------------------------- */
45/* -------------------------------------------------------------------- */
46/* ARM PL341 DDR2 configuration registers, offset 0x000 */
47/* -------------------------------------------------------------------- */
48/* -------------------------------------------------------------------- */
49
50 typedef struct {
51 uint32_t memcStatus;
52 uint32_t memcCmd;
53 uint32_t directCmd;
54 uint32_t memoryCfg;
55 uint32_t refreshPrd;
56 uint32_t casLatency;
57 uint32_t writeLatency;
58 uint32_t tMrd;
59 uint32_t tRas;
60 uint32_t tRc;
61 uint32_t tRcd;
62 uint32_t tRfc;
63 uint32_t tRp;
64 uint32_t tRrd;
65 uint32_t tWr;
66 uint32_t tWtr;
67 uint32_t tXp;
68 uint32_t tXsr;
69 uint32_t tEsr;
70 uint32_t memoryCfg2;
71 uint32_t memoryCfg3;
72 uint32_t tFaw;
73 } ddrcReg_CTLR_MEMC_REG_t;
74
75#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000
76#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
77
78/* ----------------------------------------------------- */
79
80#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12)
81#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12)
82#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12)
83
84#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10)
85#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10)
86#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10)
87#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10)
88#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10)
89
90#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7)
91#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7)
92#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7)
93#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7)
94#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7)
95
96#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4)
97#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4)
98
99#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2)
100#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2)
101#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2)
102#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2)
103#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2)
104
105#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0)
106#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0)
107#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0)
108#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0)
109#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0)
110
111/* ----------------------------------------------------- */
112
113#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0)
114#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0)
115#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0)
116#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0)
117#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0)
118#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0)
119#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0)
120
121/* ----------------------------------------------------- */
122
123#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20
124#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
125
126#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18)
127#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18)
128#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18)
129#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18)
130
131#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16
132#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
133
134#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0
135#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
136
137/* ----------------------------------------------------- */
138
139#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21)
140#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21)
141#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21)
142#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21)
143#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21)
144
145#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18)
146#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18)
147#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18)
148#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18)
149#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18)
150#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18)
151#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18)
152#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18)
153#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18)
154
155#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15)
156#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15)
157#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */
158
159#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13)
160
161#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7
162#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
163
164#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3)
165#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3)
166#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3)
167#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3)
168#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3)
169#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3)
170#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3)
171
172#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0)
173#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0)
174#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0)
175#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0)
176
177/* ----------------------------------------------------- */
178
179#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0
180#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
181
182/* ----------------------------------------------------- */
183
184#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1
185#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
186
187/* ----------------------------------------------------- */
188
189#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0
190#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
191
192/* ----------------------------------------------------- */
193
194#define ddrcReg_CTLR_T_MRD_SHIFT 0
195#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
196
197/* ----------------------------------------------------- */
198
199#define ddrcReg_CTLR_T_RAS_SHIFT 0
200#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
201
202/* ----------------------------------------------------- */
203
204#define ddrcReg_CTLR_T_RC_SHIFT 0
205#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
206
207/* ----------------------------------------------------- */
208
209#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8
210#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
211
212#define ddrcReg_CTLR_T_RCD_SHIFT 0
213#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
214
215/* ----------------------------------------------------- */
216
217#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8
218#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
219
220#define ddrcReg_CTLR_T_RFC_SHIFT 0
221#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
222
223/* ----------------------------------------------------- */
224
225#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8
226#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
227
228#define ddrcReg_CTLR_T_RP_SHIFT 0
229#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT)
230
231/* ----------------------------------------------------- */
232
233#define ddrcReg_CTLR_T_RRD_SHIFT 0
234#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
235
236/* ----------------------------------------------------- */
237
238#define ddrcReg_CTLR_T_WR_SHIFT 0
239#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
240
241/* ----------------------------------------------------- */
242
243#define ddrcReg_CTLR_T_WTR_SHIFT 0
244#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
245
246/* ----------------------------------------------------- */
247
248#define ddrcReg_CTLR_T_XP_SHIFT 0
249#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT)
250
251/* ----------------------------------------------------- */
252
253#define ddrcReg_CTLR_T_XSR_SHIFT 0
254#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
255
256/* ----------------------------------------------------- */
257
258#define ddrcReg_CTLR_T_ESR_SHIFT 0
259#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
260
261/* ----------------------------------------------------- */
262
263#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6)
264#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6)
265#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6)
266#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6)
267
268#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4)
269#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4)
270#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4)
271
272#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3)
273#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3)
274
275#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2)
276#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2)
277
278#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0)
279#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0)
280#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0)
281#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0)
282
283/* ----------------------------------------------------- */
284
285#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0
286#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
287
288/* ----------------------------------------------------- */
289
290#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8
291#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
292
293#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0
294#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
295
296/* -------------------------------------------------------------------- */
297/* -------------------------------------------------------------------- */
298/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
299/* -------------------------------------------------------------------- */
300/* -------------------------------------------------------------------- */
301
302#define ddrcReg_CTLR_QOS_CNT 16
303#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1)
304
305 typedef struct {
306 uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
307 } ddrcReg_CTLR_QOS_REG_t;
308
309#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100
310#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
311
312/* ----------------------------------------------------- */
313
314#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2
315#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
316
317#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1
318#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
319
320#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0)
321
322/* -------------------------------------------------------------------- */
323/* -------------------------------------------------------------------- */
324/* ARM PL341 Memory chip configuration registers, offset 0x200 */
325/* -------------------------------------------------------------------- */
326/* -------------------------------------------------------------------- */
327
328#define ddrcReg_CTLR_CHIP_CNT 4
329#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1)
330
331 typedef struct {
332 uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
333 } ddrcReg_CTLR_CHIP_REG_t;
334
335#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200
336#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
337
338/* ----------------------------------------------------- */
339
340#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16)
341#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16)
342#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16)
343
344#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8
345#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
346
347#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0
348#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
349
350/* -------------------------------------------------------------------- */
351/* -------------------------------------------------------------------- */
352/* ARM PL341 User configuration registers, offset 0x300 */
353/* -------------------------------------------------------------------- */
354/* -------------------------------------------------------------------- */
355
356#define ddrcReg_CTLR_USER_OUTPUT_CNT 2
357
358 typedef struct {
359 uint32_t input;
360 uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
361 uint32_t feature;
362 } ddrcReg_CTLR_USER_REG_t;
363
364#define ddrcReg_CTLR_USER_REG_OFFSET 0x300
365#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
366
367/* ----------------------------------------------------- */
368
369#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0
370#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
371
372/* ----------------------------------------------------- */
373
374#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0
375#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
376
377#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1
378#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
379#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
380#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
381#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
382
383/* ----------------------------------------------------- */
384
385#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2)
386#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0)
387
388/*********************************************************************/
389/* Broadcom DDR23 PHY register definitions */
390/*********************************************************************/
391
392/* -------------------------------------------------------------------- */
393/* -------------------------------------------------------------------- */
394/* Broadcom DDR23 PHY Address and Control register definitions */
395/* -------------------------------------------------------------------- */
396/* -------------------------------------------------------------------- */
397
398 typedef struct {
399 uint32_t revision;
400 uint32_t pmCtl;
401 REG32_RSVD(0x0008, 0x0010);
402 uint32_t pllStatus;
403 uint32_t pllCfg;
404 uint32_t pllPreDiv;
405 uint32_t pllDiv;
406 uint32_t pllCtl1;
407 uint32_t pllCtl2;
408 uint32_t ssCtl;
409 uint32_t ssCfg;
410 uint32_t vdlStatic;
411 uint32_t vdlDynamic;
412 uint32_t padIdle;
413 uint32_t pvtComp;
414 uint32_t padDrive;
415 uint32_t clkRgltrCtl;
416 } ddrcReg_PHY_ADDR_CTL_REG_t;
417
418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
420
421/* @todo These SS definitions are duplicates of ones below */
422
423#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001
424#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000
425#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16
426#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */
427#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF
428#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0
429
430/* ----------------------------------------------------- */
431
432#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8
433#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
434
435#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0
436#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
437
438/* ----------------------------------------------------- */
439
440#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
441
442/* ----------------------------------------------------- */
443
444#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0)
445
446/* ----------------------------------------------------- */
447
448#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31)
449
450#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17
451#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
452
453#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16)
454
455#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12
456#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
457
458#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7)
459#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6)
460#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5)
461#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4)
462#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3)
463#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2)
464#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0)
465
466/* ----------------------------------------------------- */
467
468#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26)
469#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25)
470
471#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20
472#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
473
474#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8
475#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
476
477#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4
478#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
479
480#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0
481#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
482
483/* ----------------------------------------------------- */
484
485#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24
486#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
487
488#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0
489#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
490
491/* ----------------------------------------------------- */
492
493#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30
494#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
495
496#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27
497#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
498
499#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24
500#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
501
502#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22
503#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
504
505#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21)
506
507#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19
508#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
509
510#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17
511#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
512
513#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15
514#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
515
516#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13
517#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
518
519#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10
520#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
521
522#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5
523#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
524
525#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0
526#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
527
528/* ----------------------------------------------------- */
529#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4
530#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
531
532#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2
533#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
534
535#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1)
536#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0)
537
538/* ----------------------------------------------------- */
539
540#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0)
541
542/* ----------------------------------------------------- */
543
544#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16
545#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
546
547#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0
548#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
549
550/* ----------------------------------------------------- */
551
552#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20)
553#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16)
554
555#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12
556#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
557
558#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8
559#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
560
561#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0
562#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
563
564/* ----------------------------------------------------- */
565
566#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16)
567
568#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12
569#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
570
571#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8
572#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
573
574#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0
575#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
576
577/* ----------------------------------------------------- */
578
579#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31)
580#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8)
581#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6)
582#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5)
583#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4)
584#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2)
585#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1)
586#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0)
587
588/* ----------------------------------------------------- */
589
590#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30)
591#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29)
592#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28)
593#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27)
594#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26)
595#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25)
596#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24)
597
598#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20
599#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
600
601#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16
602#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
603
604#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12
605#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
606
607#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8
608#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
609
610#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4
611#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
612
613#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0
614#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
615
616/* ----------------------------------------------------- */
617
618#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4)
619#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3)
620#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2)
621#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1)
622#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0)
623
624/* ----------------------------------------------------- */
625
626#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1)
627#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0)
628
629/* -------------------------------------------------------------------- */
630/* -------------------------------------------------------------------- */
631/* Broadcom DDR23 PHY Byte Lane register definitions */
632/* -------------------------------------------------------------------- */
633/* -------------------------------------------------------------------- */
634
635#define ddrcReg_PHY_BYTE_LANE_CNT 2
636#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
637
638#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8
639
640 typedef struct {
641 uint32_t revision;
642 uint32_t vdlCalibrate;
643 uint32_t vdlStatus;
644 REG32_RSVD(0x000c, 0x0010);
645 uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
646 uint32_t readCtl;
647 uint32_t readStatus;
648 uint32_t readClear;
649 uint32_t padIdleCtl;
650 uint32_t padDriveCtl;
651 uint32_t padClkCtl;
652 uint32_t writeCtl;
653 uint32_t clkRegCtl;
654 } ddrcReg_PHY_BYTE_LANE_REG_t;
655
656/* There are 2 instances of the byte Lane registers, one for each byte lane. */
657#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500
658#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600
659
660#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
661#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
662
663/* ----------------------------------------------------- */
664
665#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8
666#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
667
668#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0
669#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
670
671/* ----------------------------------------------------- */
672
673#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4)
674#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4)
675
676#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3)
677#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2)
678#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1)
679#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0)
680
681/* ----------------------------------------------------- */
682
683/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
684/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
685/* register. The fine rise and fall are no longer used, so add some definitions for just */
686/* the step setting to simplify things. */
687
688#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8
689#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
690
691#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4
692#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
693
694#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1)
695#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0)
696
697/* ----------------------------------------------------- */
698
699#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16)
700
701#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12
702#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
703
704#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8
705#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
706
707#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0
708#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
709
710#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0
711#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1
712#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2
713#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3
714#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4
715#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5
716#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6
717#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7
718
719/* ----------------------------------------------------- */
720
721#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8
722#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
723
724#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3)
725#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2)
726#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1)
727#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0)
728
729/* ----------------------------------------------------- */
730
731#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0
732#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
733
734/* ----------------------------------------------------- */
735
736#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0)
737
738/* ----------------------------------------------------- */
739
740#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31)
741#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19)
742#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18)
743#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17)
744#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16)
745#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15)
746#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14)
747#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13)
748#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12)
749#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11)
750#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10)
751#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9)
752#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8)
753#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7)
754#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6)
755#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5)
756#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4)
757#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3)
758#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2)
759#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1)
760#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0)
761
762/* ----------------------------------------------------- */
763
764#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5)
765#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4)
766#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3)
767#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2)
768#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1)
769#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0)
770
771/* ----------------------------------------------------- */
772
773#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0)
774
775/* ----------------------------------------------------- */
776
777#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0)
778
779/* ----------------------------------------------------- */
780
781#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1)
782#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0)
783
784/*********************************************************************/
785/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
786/*********************************************************************/
787
788 typedef struct {
789 uint32_t cfg;
790 uint32_t actMonCnt;
791 uint32_t ctl;
792 uint32_t lbistCtl;
793 uint32_t lbistSeed;
794 uint32_t lbistStatus;
795 uint32_t tieOff;
796 uint32_t actMonClear;
797 uint32_t status;
798 uint32_t user;
799 } ddrcReg_CTLR_PHY_GLUE_REG_t;
800
801#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700
802#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
803
804/* ----------------------------------------------------- */
805
806/* DDR2 / AXI block phase alignment interrupt control */
807#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18
808#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
809#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
810#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
811#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
812#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
813
814#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17
815#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
816#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
817#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
818
819#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16
820#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
821#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
822#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
823#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
824
825#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15
826#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
827#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
828#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
829#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
830
831/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
832/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
833/* controller. If 2 chips selects are being used, then software control must be enabled. */
834#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14)
835#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13)
836
837/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
838#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
839#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
840#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
841
842/* Chip select count */
843#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9
844#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
845#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
846#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
847
848#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8
849#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
850#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
851
852#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7
853#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
854#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
855
856#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6
857#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
858#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
859
860#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0
861#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
862
863/* ----------------------------------------------------- */
864#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0
865#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
866
867/* ---- Public Function Prototypes --------------------------------------- */
868
869#ifdef __cplusplus
870} /* end extern "C" */
871#endif
872#endif /* DDRC_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 17:09:20 -0500