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Diffstat (limited to 'arch/arm/mach-at91rm9200/at91rm9200.c')
-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c250
1 files changed, 196 insertions, 54 deletions
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index 0985b1c42c7c..dcf6136fedf9 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -17,6 +17,7 @@
17 17
18#include <asm/hardware.h> 18#include <asm/hardware.h>
19#include "generic.h" 19#include "generic.h"
20#include "clock.h"
20 21
21static struct map_desc at91rm9200_io_desc[] __initdata = { 22static struct map_desc at91rm9200_io_desc[] __initdata = {
22 { 23 {
@@ -26,87 +27,224 @@ static struct map_desc at91rm9200_io_desc[] __initdata = {
26 .type = MT_DEVICE, 27 .type = MT_DEVICE,
27 }, { 28 }, {
28 .virtual = AT91_VA_BASE_SPI, 29 .virtual = AT91_VA_BASE_SPI,
29 .pfn = __phys_to_pfn(AT91_BASE_SPI), 30 .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
30 .length = SZ_16K,
31 .type = MT_DEVICE,
32 }, {
33 .virtual = AT91_VA_BASE_SSC2,
34 .pfn = __phys_to_pfn(AT91_BASE_SSC2),
35 .length = SZ_16K,
36 .type = MT_DEVICE,
37 }, {
38 .virtual = AT91_VA_BASE_SSC1,
39 .pfn = __phys_to_pfn(AT91_BASE_SSC1),
40 .length = SZ_16K,
41 .type = MT_DEVICE,
42 }, {
43 .virtual = AT91_VA_BASE_SSC0,
44 .pfn = __phys_to_pfn(AT91_BASE_SSC0),
45 .length = SZ_16K,
46 .type = MT_DEVICE,
47 }, {
48 .virtual = AT91_VA_BASE_US3,
49 .pfn = __phys_to_pfn(AT91_BASE_US3),
50 .length = SZ_16K,
51 .type = MT_DEVICE,
52 }, {
53 .virtual = AT91_VA_BASE_US2,
54 .pfn = __phys_to_pfn(AT91_BASE_US2),
55 .length = SZ_16K,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = AT91_VA_BASE_US1,
59 .pfn = __phys_to_pfn(AT91_BASE_US1),
60 .length = SZ_16K,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = AT91_VA_BASE_US0,
64 .pfn = __phys_to_pfn(AT91_BASE_US0),
65 .length = SZ_16K, 31 .length = SZ_16K,
66 .type = MT_DEVICE, 32 .type = MT_DEVICE,
67 }, { 33 }, {
68 .virtual = AT91_VA_BASE_EMAC, 34 .virtual = AT91_VA_BASE_EMAC,
69 .pfn = __phys_to_pfn(AT91_BASE_EMAC), 35 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
70 .length = SZ_16K, 36 .length = SZ_16K,
71 .type = MT_DEVICE, 37 .type = MT_DEVICE,
72 }, { 38 }, {
73 .virtual = AT91_VA_BASE_TWI, 39 .virtual = AT91_VA_BASE_TWI,
74 .pfn = __phys_to_pfn(AT91_BASE_TWI), 40 .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
75 .length = SZ_16K, 41 .length = SZ_16K,
76 .type = MT_DEVICE, 42 .type = MT_DEVICE,
77 }, { 43 }, {
78 .virtual = AT91_VA_BASE_MCI, 44 .virtual = AT91_VA_BASE_MCI,
79 .pfn = __phys_to_pfn(AT91_BASE_MCI), 45 .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
80 .length = SZ_16K, 46 .length = SZ_16K,
81 .type = MT_DEVICE, 47 .type = MT_DEVICE,
82 }, { 48 }, {
83 .virtual = AT91_VA_BASE_UDP, 49 .virtual = AT91_VA_BASE_UDP,
84 .pfn = __phys_to_pfn(AT91_BASE_UDP), 50 .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
85 .length = SZ_16K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = AT91_VA_BASE_TCB1,
89 .pfn = __phys_to_pfn(AT91_BASE_TCB1),
90 .length = SZ_16K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = AT91_VA_BASE_TCB0,
94 .pfn = __phys_to_pfn(AT91_BASE_TCB0),
95 .length = SZ_16K, 51 .length = SZ_16K,
96 .type = MT_DEVICE, 52 .type = MT_DEVICE,
97 }, { 53 }, {
98 .virtual = AT91_SRAM_VIRT_BASE, 54 .virtual = AT91_SRAM_VIRT_BASE,
99 .pfn = __phys_to_pfn(AT91_SRAM_BASE), 55 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
100 .length = AT91_SRAM_SIZE, 56 .length = AT91RM9200_SRAM_SIZE,
101 .type = MT_DEVICE, 57 .type = MT_DEVICE,
102 }, 58 },
103}; 59};
104 60
105void __init at91rm9200_map_io(void) 61/* --------------------------------------------------------------------
62 * Clocks
63 * -------------------------------------------------------------------- */
64
65/*
66 * The peripheral clocks.
67 */
68static struct clk udc_clk = {
69 .name = "udc_clk",
70 .pmc_mask = 1 << AT91RM9200_ID_UDP,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk ohci_clk = {
74 .name = "ohci_clk",
75 .pmc_mask = 1 << AT91RM9200_ID_UHP,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk ether_clk = {
79 .name = "ether_clk",
80 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc_clk = {
84 .name = "mci_clk",
85 .pmc_mask = 1 << AT91RM9200_ID_MCI,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk twi_clk = {
89 .name = "twi_clk",
90 .pmc_mask = 1 << AT91RM9200_ID_TWI,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk usart0_clk = {
94 .name = "usart0_clk",
95 .pmc_mask = 1 << AT91RM9200_ID_US0,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk usart1_clk = {
99 .name = "usart1_clk",
100 .pmc_mask = 1 << AT91RM9200_ID_US1,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk usart2_clk = {
104 .name = "usart2_clk",
105 .pmc_mask = 1 << AT91RM9200_ID_US2,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk usart3_clk = {
109 .name = "usart3_clk",
110 .pmc_mask = 1 << AT91RM9200_ID_US3,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk spi_clk = {
114 .name = "spi_clk",
115 .pmc_mask = 1 << AT91RM9200_ID_SPI,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk pioA_clk = {
119 .name = "pioA_clk",
120 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk pioB_clk = {
124 .name = "pioB_clk",
125 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk pioC_clk = {
129 .name = "pioC_clk",
130 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk pioD_clk = {
134 .name = "pioD_clk",
135 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138
139static struct clk *periph_clocks[] __initdata = {
140 &pioA_clk,
141 &pioB_clk,
142 &pioC_clk,
143 &pioD_clk,
144 &usart0_clk,
145 &usart1_clk,
146 &usart2_clk,
147 &usart3_clk,
148 &mmc_clk,
149 &udc_clk,
150 &twi_clk,
151 &spi_clk,
152 // ssc 0 .. ssc2
153 // tc0 .. tc5
154 &ohci_clk,
155 &ether_clk,
156 // irq0 .. irq6
157};
158
159/*
160 * The four programmable clocks.
161 * You must configure pin multiplexing to bring these signals out.
162 */
163static struct clk pck0 = {
164 .name = "pck0",
165 .pmc_mask = AT91_PMC_PCK0,
166 .type = CLK_TYPE_PROGRAMMABLE,
167 .id = 0,
168};
169static struct clk pck1 = {
170 .name = "pck1",
171 .pmc_mask = AT91_PMC_PCK1,
172 .type = CLK_TYPE_PROGRAMMABLE,
173 .id = 1,
174};
175static struct clk pck2 = {
176 .name = "pck2",
177 .pmc_mask = AT91_PMC_PCK2,
178 .type = CLK_TYPE_PROGRAMMABLE,
179 .id = 2,
180};
181static struct clk pck3 = {
182 .name = "pck3",
183 .pmc_mask = AT91_PMC_PCK3,
184 .type = CLK_TYPE_PROGRAMMABLE,
185 .id = 3,
186};
187
188static void __init at91rm9200_register_clocks(void)
106{ 189{
190 int i;
191
192 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
193 clk_register(periph_clocks[i]);
194
195 clk_register(&pck0);
196 clk_register(&pck1);
197 clk_register(&pck2);
198 clk_register(&pck3);
199}
200
201/* --------------------------------------------------------------------
202 * GPIO
203 * -------------------------------------------------------------------- */
204
205static struct at91_gpio_bank at91rm9200_gpio[] = {
206 {
207 .id = AT91RM9200_ID_PIOA,
208 .offset = AT91_PIOA,
209 .clock = &pioA_clk,
210 }, {
211 .id = AT91RM9200_ID_PIOB,
212 .offset = AT91_PIOB,
213 .clock = &pioB_clk,
214 }, {
215 .id = AT91RM9200_ID_PIOC,
216 .offset = AT91_PIOC,
217 .clock = &pioC_clk,
218 }, {
219 .id = AT91RM9200_ID_PIOD,
220 .offset = AT91_PIOD,
221 .clock = &pioD_clk,
222 }
223};
224
225/* --------------------------------------------------------------------
226 * AT91RM9200 processor initialization
227 * -------------------------------------------------------------------- */
228void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
229{
230 /* Map peripherals */
107 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); 231 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
232
233 /* Init clock subsystem */
234 at91_clock_init(main_clock);
235
236 /* Register the processor-specific clocks */
237 at91rm9200_register_clocks();
238
239 /* Initialize GPIO subsystem */
240 at91_gpio_init(at91rm9200_gpio, banks);
108} 241}
109 242
243
244/* --------------------------------------------------------------------
245 * Interrupt initialization
246 * -------------------------------------------------------------------- */
247
110/* 248/*
111 * The default interrupt priority levels (0 = lowest, 7 = highest). 249 * The default interrupt priority levels (0 = lowest, 7 = highest).
112 */ 250 */
@@ -145,10 +283,14 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
145 0 /* Advanced Interrupt Controller (IRQ6) */ 283 0 /* Advanced Interrupt Controller (IRQ6) */
146}; 284};
147 285
148void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) 286void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])
149{ 287{
150 if (!priority) 288 if (!priority)
151 priority = at91rm9200_default_irq_priority; 289 priority = at91rm9200_default_irq_priority;
152 290
291 /* Initialize the AIC interrupt controller */
153 at91_aic_init(priority); 292 at91_aic_init(priority);
293
294 /* Enable GPIO interrupts */
295 at91_gpio_irq_setup();
154} 296}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 04:00:33 -0500