aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-at91
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig70
-rw-r--r--arch/arm/mach-at91/Makefile9
-rw-r--r--arch/arm/mach-at91/Makefile.boot4
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c116
-rw-r--r--arch/arm/mach-at91/at91sam9261.c22
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c14
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c360
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c1230
-rw-r--r--arch/arm/mach-at91/board-afeb-9260v1.c12
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c385
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c185
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c14
-rw-r--r--arch/arm/mach-at91/board-sam9263ek.c4
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c1
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c389
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c79
-rw-r--r--arch/arm/mach-at91/clock.c66
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/gpio.c15
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h3
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h155
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h153
-rw-r--r--arch/arm/mach-at91/include/mach/board.h14
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h23
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h10
-rw-r--r--arch/arm/mach-at91/pm.c3
27 files changed, 3296 insertions, 46 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 323b47f2b52f..a24d824c428b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,12 @@ config ARCH_AT91SAM9261
23 select GENERIC_TIME 23 select GENERIC_TIME
24 select GENERIC_CLOCKEVENTS 24 select GENERIC_CLOCKEVENTS
25 25
26config ARCH_AT91SAM9G10
27 bool "AT91SAM9G10"
28 select CPU_ARM926T
29 select GENERIC_TIME
30 select GENERIC_CLOCKEVENTS
31
26config ARCH_AT91SAM9263 32config ARCH_AT91SAM9263
27 bool "AT91SAM9263" 33 bool "AT91SAM9263"
28 select CPU_ARM926T 34 select CPU_ARM926T
@@ -41,6 +47,12 @@ config ARCH_AT91SAM9G20
41 select GENERIC_TIME 47 select GENERIC_TIME
42 select GENERIC_CLOCKEVENTS 48 select GENERIC_CLOCKEVENTS
43 49
50config ARCH_AT91SAM9G45
51 bool "AT91SAM9G45"
52 select CPU_ARM926T
53 select GENERIC_TIME
54 select GENERIC_CLOCKEVENTS
55
44config ARCH_AT91CAP9 56config ARCH_AT91CAP9
45 bool "AT91CAP9" 57 bool "AT91CAP9"
46 select CPU_ARM926T 58 select CPU_ARM926T
@@ -144,6 +156,13 @@ config MACH_YL9200
144 help 156 help
145 Select this if you are using the ucDragon YL-9200 board. 157 Select this if you are using the ucDragon YL-9200 board.
146 158
159config MACH_CPUAT91
160 bool "Eukrea CPUAT91"
161 depends on ARCH_AT91RM9200
162 help
163 Select this if you are using the Eukrea Electromatique's
164 CPUAT91 board <http://www.eukrea.com/>.
165
147endif 166endif
148 167
149# ---------------------------------------------------------- 168# ----------------------------------------------------------
@@ -205,6 +224,13 @@ config MACH_QIL_A9260
205 Select this if you are using a Calao Systems QIL-A9260 Board. 224 Select this if you are using a Calao Systems QIL-A9260 Board.
206 <http://www.calao-systems.com> 225 <http://www.calao-systems.com>
207 226
227config MACH_CPU9260
228 bool "Eukrea CPU9260 board"
229 depends on ARCH_AT91SAM9260
230 help
231 Select this if you are using a Eukrea Electromatique's
232 CPU9260 Board <http://www.eukrea.com/>
233
208endif 234endif
209 235
210# ---------------------------------------------------------- 236# ----------------------------------------------------------
@@ -224,6 +250,21 @@ endif
224 250
225# ---------------------------------------------------------- 251# ----------------------------------------------------------
226 252
253if ARCH_AT91SAM9G10
254
255comment "AT91SAM9G10 Board Type"
256
257config MACH_AT91SAM9G10EK
258 bool "Atmel AT91SAM9G10-EK Evaluation Kit"
259 depends on ARCH_AT91SAM9G10
260 help
261 Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
262 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
263
264endif
265
266# ----------------------------------------------------------
267
227if ARCH_AT91SAM9263 268if ARCH_AT91SAM9263
228 269
229comment "AT91SAM9263 Board Type" 270comment "AT91SAM9263 Board Type"
@@ -276,6 +317,29 @@ config MACH_AT91SAM9G20EK
276 help 317 help
277 Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit. 318 Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
278 319
320config MACH_CPU9G20
321 bool "Eukrea CPU9G20 board"
322 depends on ARCH_AT91SAM9G20
323 help
324 Select this if you are using a Eukrea Electromatique's
325 CPU9G20 Board <http://www.eukrea.com/>
326
327endif
328
329# ----------------------------------------------------------
330
331if ARCH_AT91SAM9G45
332
333comment "AT91SAM9G45 Board Type"
334
335config MACH_AT91SAM9G45EKES
336 bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
337 depends on ARCH_AT91SAM9G45
338 help
339 Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
340 "ES" at the end of the name means that this board is an
341 Engineering Sample.
342
279endif 343endif
280 344
281# ---------------------------------------------------------- 345# ----------------------------------------------------------
@@ -315,13 +379,13 @@ comment "AT91 Board Options"
315 379
316config MTD_AT91_DATAFLASH_CARD 380config MTD_AT91_DATAFLASH_CARD
317 bool "Enable DataFlash Card support" 381 bool "Enable DataFlash Card support"
318 depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) 382 depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
319 help 383 help
320 Enable support for the DataFlash card. 384 Enable support for the DataFlash card.
321 385
322config MTD_NAND_ATMEL_BUSWIDTH_16 386config MTD_NAND_ATMEL_BUSWIDTH_16
323 bool "Enable 16-bit data bus interface to NAND flash" 387 bool "Enable 16-bit data bus interface to NAND flash"
324 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK) 388 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
325 help 389 help
326 On AT91SAM926x boards both types of NAND flash can be present 390 On AT91SAM926x boards both types of NAND flash can be present
327 (8 and 16 bit data bus width). 391 (8 and 16 bit data bus width).
@@ -383,7 +447,7 @@ config AT91_EARLY_USART2
383 447
384config AT91_EARLY_USART3 448config AT91_EARLY_USART3
385 bool "USART3" 449 bool "USART3"
386 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) 450 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
387 451
388config AT91_EARLY_USART4 452config AT91_EARLY_USART4
389 bool "USART4" 453 bool "USART4"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c69ff237fd14..a6ed015d82ed 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -13,9 +13,11 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o 13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
16obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o 17obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 18obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
18obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
20 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
19obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
20obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 22obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
21 23
@@ -32,6 +34,7 @@ obj-$(CONFIG_MACH_KAFA) += board-kafa.o
32obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o 34obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
33obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o 35obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
34obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o 36obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
37obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
35 38
36# AT91SAM9260 board-specific support 39# AT91SAM9260 board-specific support
37obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o 40obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -40,9 +43,11 @@ obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
40obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o 43obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o
41obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o 44obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
42obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o 45obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o
46obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
43 47
44# AT91SAM9261 board-specific support 48# AT91SAM9261 board-specific support
45obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o 49obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
50obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
46 51
47# AT91SAM9263 board-specific support 52# AT91SAM9263 board-specific support
48obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 53obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
@@ -54,6 +59,10 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
54 59
55# AT91SAM9G20 board-specific support 60# AT91SAM9G20 board-specific support
56obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 61obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
62obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
63
64# AT91SAM9G45 board-specific support
65obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
57 66
58# AT91CAP9 board-specific support 67# AT91CAP9 board-specific support
59obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 68obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 071a2506a69f..3462b815054a 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y)
7 zreladdr-y := 0x70008000 7 zreladdr-y := 0x70008000
8params_phys-y := 0x70000100 8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000 9initrd_phys-y := 0x70410000
10else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
11 zreladdr-y := 0x70008000
12params_phys-y := 0x70000100
13initrd_phys-y := 0x70410000
10else 14else
11 zreladdr-y := 0x20008000 15 zreladdr-y := 0x20008000
12params_phys-y := 0x20000100 16params_phys-y := 0x20000100
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index d74c9ac007e7..ee4ea0e720cf 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -1113,6 +1113,122 @@ void __init at91_set_serial_console(unsigned portnr) {}
1113void __init at91_add_device_serial(void) {} 1113void __init at91_add_device_serial(void) {}
1114#endif 1114#endif
1115 1115
1116/* --------------------------------------------------------------------
1117 * CF/IDE
1118 * -------------------------------------------------------------------- */
1119
1120#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
1121 defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1122 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1123
1124static struct at91_cf_data cf0_data;
1125
1126static struct resource cf0_resources[] = {
1127 [0] = {
1128 .start = AT91_CHIPSELECT_4,
1129 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
1130 .flags = IORESOURCE_MEM,
1131 }
1132};
1133
1134static struct platform_device cf0_device = {
1135 .id = 0,
1136 .dev = {
1137 .platform_data = &cf0_data,
1138 },
1139 .resource = cf0_resources,
1140 .num_resources = ARRAY_SIZE(cf0_resources),
1141};
1142
1143static struct at91_cf_data cf1_data;
1144
1145static struct resource cf1_resources[] = {
1146 [0] = {
1147 .start = AT91_CHIPSELECT_5,
1148 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
1149 .flags = IORESOURCE_MEM,
1150 }
1151};
1152
1153static struct platform_device cf1_device = {
1154 .id = 1,
1155 .dev = {
1156 .platform_data = &cf1_data,
1157 },
1158 .resource = cf1_resources,
1159 .num_resources = ARRAY_SIZE(cf1_resources),
1160};
1161
1162void __init at91_add_device_cf(struct at91_cf_data *data)
1163{
1164 struct platform_device *pdev;
1165 unsigned long csa;
1166
1167 if (!data)
1168 return;
1169
1170 csa = at91_sys_read(AT91_MATRIX_EBICSA);
1171
1172 switch (data->chipselect) {
1173 case 4:
1174 at91_set_multi_drive(AT91_PIN_PC8, 0);
1175 at91_set_A_periph(AT91_PIN_PC8, 0);
1176 csa |= AT91_MATRIX_CS4A_SMC_CF1;
1177 cf0_data = *data;
1178 pdev = &cf0_device;
1179 break;
1180 case 5:
1181 at91_set_multi_drive(AT91_PIN_PC9, 0);
1182 at91_set_A_periph(AT91_PIN_PC9, 0);
1183 csa |= AT91_MATRIX_CS5A_SMC_CF2;
1184 cf1_data = *data;
1185 pdev = &cf1_device;
1186 break;
1187 default:
1188 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
1189 data->chipselect);
1190 return;
1191 }
1192
1193 at91_sys_write(AT91_MATRIX_EBICSA, csa);
1194
1195 if (data->rst_pin) {
1196 at91_set_multi_drive(data->rst_pin, 0);
1197 at91_set_gpio_output(data->rst_pin, 1);
1198 }
1199
1200 if (data->irq_pin) {
1201 at91_set_gpio_input(data->irq_pin, 0);
1202 at91_set_deglitch(data->irq_pin, 1);
1203 }
1204
1205 if (data->det_pin) {
1206 at91_set_gpio_input(data->det_pin, 0);
1207 at91_set_deglitch(data->det_pin, 1);
1208 }
1209
1210 at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */
1211 at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */
1212 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1213 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
1214
1215 if (data->flags & AT91_CF_TRUE_IDE)
1216#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1217 pdev->name = "pata_at91";
1218#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
1219 pdev->name = "at91_ide";
1220#else
1221#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
1222#endif
1223 else
1224 pdev->name = "at91_cf";
1225
1226 platform_device_register(pdev);
1227}
1228
1229#else
1230void __init at91_add_device_cf(struct at91_cf_data * data) {}
1231#endif
1116 1232
1117/* -------------------------------------------------------------------- */ 1233/* -------------------------------------------------------------------- */
1118/* 1234/*
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 3acd7d7e6a42..4ecf37996c77 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -16,6 +16,7 @@
16#include <asm/irq.h> 16#include <asm/irq.h>
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/mach/map.h> 18#include <asm/mach/map.h>
19#include <mach/cpu.h>
19#include <mach/at91sam9261.h> 20#include <mach/at91sam9261.h>
20#include <mach/at91_pmc.h> 21#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h> 22#include <mach/at91_rstc.h>
@@ -30,7 +31,11 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
30 .pfn = __phys_to_pfn(AT91_BASE_SYS), 31 .pfn = __phys_to_pfn(AT91_BASE_SYS),
31 .length = SZ_16K, 32 .length = SZ_16K,
32 .type = MT_DEVICE, 33 .type = MT_DEVICE,
33 }, { 34 },
35};
36
37static struct map_desc at91sam9261_sram_desc[] __initdata = {
38 {
34 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, 39 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
35 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), 40 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
36 .length = AT91SAM9261_SRAM_SIZE, 41 .length = AT91SAM9261_SRAM_SIZE,
@@ -38,6 +43,15 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
38 }, 43 },
39}; 44};
40 45
46static struct map_desc at91sam9g10_sram_desc[] __initdata = {
47 {
48 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
49 .pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
50 .length = AT91SAM9G10_SRAM_SIZE,
51 .type = MT_DEVICE,
52 },
53};
54
41/* -------------------------------------------------------------------- 55/* --------------------------------------------------------------------
42 * Clocks 56 * Clocks
43 * -------------------------------------------------------------------- */ 57 * -------------------------------------------------------------------- */
@@ -263,6 +277,12 @@ void __init at91sam9261_initialize(unsigned long main_clock)
263 /* Map peripherals */ 277 /* Map peripherals */
264 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); 278 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
265 279
280 if (cpu_is_at91sam9g10())
281 iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
282 else
283 iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
284
285
266 at91_arch_reset = at91sam9261_reset; 286 at91_arch_reset = at91sam9261_reset;
267 pm_power_off = at91sam9261_poweroff; 287 pm_power_off = at91sam9261_poweroff;
268 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) 288 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b7f233242315..55719a974276 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -707,9 +707,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
707 * AC97 707 * AC97
708 * -------------------------------------------------------------------- */ 708 * -------------------------------------------------------------------- */
709 709
710#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE) 710#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
711static u64 ac97_dmamask = DMA_BIT_MASK(32); 711static u64 ac97_dmamask = DMA_BIT_MASK(32);
712static struct atmel_ac97_data ac97_data; 712static struct ac97c_platform_data ac97_data;
713 713
714static struct resource ac97_resources[] = { 714static struct resource ac97_resources[] = {
715 [0] = { 715 [0] = {
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = {
725}; 725};
726 726
727static struct platform_device at91sam9263_ac97_device = { 727static struct platform_device at91sam9263_ac97_device = {
728 .name = "ac97c", 728 .name = "atmel_ac97c",
729 .id = 1, 729 .id = 0,
730 .dev = { 730 .dev = {
731 .dma_mask = &ac97_dmamask, 731 .dma_mask = &ac97_dmamask,
732 .coherent_dma_mask = DMA_BIT_MASK(32), 732 .coherent_dma_mask = DMA_BIT_MASK(32),
@@ -736,7 +736,7 @@ static struct platform_device at91sam9263_ac97_device = {
736 .num_resources = ARRAY_SIZE(ac97_resources), 736 .num_resources = ARRAY_SIZE(ac97_resources),
737}; 737};
738 738
739void __init at91_add_device_ac97(struct atmel_ac97_data *data) 739void __init at91_add_device_ac97(struct ac97c_platform_data *data)
740{ 740{
741 if (!data) 741 if (!data)
742 return; 742 return;
@@ -750,11 +750,11 @@ void __init at91_add_device_ac97(struct atmel_ac97_data *data)
750 if (data->reset_pin) 750 if (data->reset_pin)
751 at91_set_gpio_output(data->reset_pin, 0); 751 at91_set_gpio_output(data->reset_pin, 0);
752 752
753 ac97_data = *ek_data; 753 ac97_data = *data;
754 platform_device_register(&at91sam9263_ac97_device); 754 platform_device_register(&at91sam9263_ac97_device);
755} 755}
756#else 756#else
757void __init at91_add_device_ac97(struct atmel_ac97_data *data) {} 757void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
758#endif 758#endif
759 759
760 760
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
new file mode 100644
index 000000000000..85166b7e69a1
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -0,0 +1,360 @@
1/*
2 * Chip-specific setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/pm.h>
15
16#include <asm/irq.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <mach/at91sam9g45.h>
20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h>
22#include <mach/at91_shdwc.h>
23
24#include "generic.h"
25#include "clock.h"
26
27static struct map_desc at91sam9g45_io_desc[] __initdata = {
28 {
29 .virtual = AT91_VA_BASE_SYS,
30 .pfn = __phys_to_pfn(AT91_BASE_SYS),
31 .length = SZ_16K,
32 .type = MT_DEVICE,
33 }, {
34 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
35 .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
36 .length = AT91SAM9G45_SRAM_SIZE,
37 .type = MT_DEVICE,
38 }
39};
40
41/* --------------------------------------------------------------------
42 * Clocks
43 * -------------------------------------------------------------------- */
44
45/*
46 * The peripheral clocks.
47 */
48static struct clk pioA_clk = {
49 .name = "pioA_clk",
50 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioB_clk = {
54 .name = "pioB_clk",
55 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk pioC_clk = {
59 .name = "pioC_clk",
60 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk pioDE_clk = {
64 .name = "pioDE_clk",
65 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart0_clk = {
69 .name = "usart0_clk",
70 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart1_clk = {
74 .name = "usart1_clk",
75 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart2_clk = {
79 .name = "usart2_clk",
80 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk usart3_clk = {
84 .name = "usart3_clk",
85 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk mmc0_clk = {
89 .name = "mci0_clk",
90 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk twi0_clk = {
94 .name = "twi0_clk",
95 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk twi1_clk = {
99 .name = "twi1_clk",
100 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi0_clk = {
104 .name = "spi0_clk",
105 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi1_clk = {
109 .name = "spi1_clk",
110 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk ssc0_clk = {
114 .name = "ssc0_clk",
115 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc1_clk = {
119 .name = "ssc1_clk",
120 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk tcb_clk = {
124 .name = "tcb_clk",
125 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk pwm_clk = {
129 .name = "pwm_clk",
130 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk tsc_clk = {
134 .name = "tsc_clk",
135 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk dma_clk = {
139 .name = "dma_clk",
140 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk uhphs_clk = {
144 .name = "uhphs_clk",
145 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk lcdc_clk = {
149 .name = "lcdc_clk",
150 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk ac97_clk = {
154 .name = "ac97_clk",
155 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk macb_clk = {
159 .name = "macb_clk",
160 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk isi_clk = {
164 .name = "isi_clk",
165 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk udphs_clk = {
169 .name = "udphs_clk",
170 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk mmc1_clk = {
174 .name = "mci1_clk",
175 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179/* One additional fake clock for ohci */
180static struct clk ohci_clk = {
181 .name = "ohci_clk",
182 .pmc_mask = 0,
183 .type = CLK_TYPE_PERIPHERAL,
184 .parent = &uhphs_clk,
185};
186
187static struct clk *periph_clocks[] __initdata = {
188 &pioA_clk,
189 &pioB_clk,
190 &pioC_clk,
191 &pioDE_clk,
192 &usart0_clk,
193 &usart1_clk,
194 &usart2_clk,
195 &usart3_clk,
196 &mmc0_clk,
197 &twi0_clk,
198 &twi1_clk,
199 &spi0_clk,
200 &spi1_clk,
201 &ssc0_clk,
202 &ssc1_clk,
203 &tcb_clk,
204 &pwm_clk,
205 &tsc_clk,
206 &dma_clk,
207 &uhphs_clk,
208 &lcdc_clk,
209 &ac97_clk,
210 &macb_clk,
211 &isi_clk,
212 &udphs_clk,
213 &mmc1_clk,
214 // irq0
215 &ohci_clk,
216};
217
218/*
219 * The two programmable clocks.
220 * You must configure pin multiplexing to bring these signals out.
221 */
222static struct clk pck0 = {
223 .name = "pck0",
224 .pmc_mask = AT91_PMC_PCK0,
225 .type = CLK_TYPE_PROGRAMMABLE,
226 .id = 0,
227};
228static struct clk pck1 = {
229 .name = "pck1",
230 .pmc_mask = AT91_PMC_PCK1,
231 .type = CLK_TYPE_PROGRAMMABLE,
232 .id = 1,
233};
234
235static void __init at91sam9g45_register_clocks(void)
236{
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
240 clk_register(periph_clocks[i]);
241
242 clk_register(&pck0);
243 clk_register(&pck1);
244}
245
246/* --------------------------------------------------------------------
247 * GPIO
248 * -------------------------------------------------------------------- */
249
250static struct at91_gpio_bank at91sam9g45_gpio[] = {
251 {
252 .id = AT91SAM9G45_ID_PIOA,
253 .offset = AT91_PIOA,
254 .clock = &pioA_clk,
255 }, {
256 .id = AT91SAM9G45_ID_PIOB,
257 .offset = AT91_PIOB,
258 .clock = &pioB_clk,
259 }, {
260 .id = AT91SAM9G45_ID_PIOC,
261 .offset = AT91_PIOC,
262 .clock = &pioC_clk,
263 }, {
264 .id = AT91SAM9G45_ID_PIODE,
265 .offset = AT91_PIOD,
266 .clock = &pioDE_clk,
267 }, {
268 .id = AT91SAM9G45_ID_PIODE,
269 .offset = AT91_PIOE,
270 .clock = &pioDE_clk,
271 }
272};
273
274static void at91sam9g45_reset(void)
275{
276 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
277}
278
279static void at91sam9g45_poweroff(void)
280{
281 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
282}
283
284
285/* --------------------------------------------------------------------
286 * AT91SAM9G45 processor initialization
287 * -------------------------------------------------------------------- */
288
289void __init at91sam9g45_initialize(unsigned long main_clock)
290{
291 /* Map peripherals */
292 iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
293
294 at91_arch_reset = at91sam9g45_reset;
295 pm_power_off = at91sam9g45_poweroff;
296 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
297
298 /* Init clock subsystem */
299 at91_clock_init(main_clock);
300
301 /* Register the processor-specific clocks */
302 at91sam9g45_register_clocks();
303
304 /* Register GPIO subsystem */
305 at91_gpio_init(at91sam9g45_gpio, 5);
306}
307
308/* --------------------------------------------------------------------
309 * Interrupt initialization
310 * -------------------------------------------------------------------- */
311
312/*
313 * The default interrupt priority levels (0 = lowest, 7 = highest).
314 */
315static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
316 7, /* Advanced Interrupt Controller (FIQ) */
317 7, /* System Peripherals */
318 1, /* Parallel IO Controller A */
319 1, /* Parallel IO Controller B */
320 1, /* Parallel IO Controller C */
321 1, /* Parallel IO Controller D and E */
322 0,
323 5, /* USART 0 */
324 5, /* USART 1 */
325 5, /* USART 2 */
326 5, /* USART 3 */
327 0, /* Multimedia Card Interface 0 */
328 6, /* Two-Wire Interface 0 */
329 6, /* Two-Wire Interface 1 */
330 5, /* Serial Peripheral Interface 0 */
331 5, /* Serial Peripheral Interface 1 */
332 4, /* Serial Synchronous Controller 0 */
333 4, /* Serial Synchronous Controller 1 */
334 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
335 0, /* Pulse Width Modulation Controller */
336 0, /* Touch Screen Controller */
337 0, /* DMA Controller */
338 2, /* USB Host High Speed port */
339 3, /* LDC Controller */
340 5, /* AC97 Controller */
341 3, /* Ethernet */
342 0, /* Image Sensor Interface */
343 2, /* USB Device High speed port */
344 0,
345 0, /* Multimedia Card Interface 1 */
346 0,
347 0, /* Advanced Interrupt Controller (IRQ0) */
348};
349
350void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
351{
352 if (!priority)
353 priority = at91sam9g45_default_irq_priority;
354
355 /* Initialize the AIC interrupt controller */
356 at91_aic_init(priority);
357
358 /* Enable GPIO interrupts */
359 at91_gpio_irq_setup();
360}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
new file mode 100644
index 000000000000..d746e8621bc2
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -0,0 +1,1230 @@
1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/i2c-gpio.h>
18
19#include <linux/fb.h>
20#include <video/atmel_lcdc.h>
21
22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9g45.h>
25#include <mach/at91sam9g45_matrix.h>
26#include <mach/at91sam9_smc.h>
27
28#include "generic.h"
29
30
31/* --------------------------------------------------------------------
32 * USB Host (OHCI)
33 * -------------------------------------------------------------------- */
34
35#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36static u64 ohci_dmamask = DMA_BIT_MASK(32);
37static struct at91_usbh_data usbh_ohci_data;
38
39static struct resource usbh_ohci_resources[] = {
40 [0] = {
41 .start = AT91SAM9G45_OHCI_BASE,
42 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9G45_ID_UHPHS,
47 .end = AT91SAM9G45_ID_UHPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static struct platform_device at91_usbh_ohci_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_ohci_data,
59 },
60 .resource = usbh_ohci_resources,
61 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
62};
63
64void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
65{
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_ohci_data = *data;
78 platform_device_register(&at91_usbh_ohci_device);
79}
80#else
81void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
82#endif
83
84
85/* --------------------------------------------------------------------
86 * USB HS Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
90static struct resource usba_udc_resources[] = {
91 [0] = {
92 .start = AT91SAM9G45_UDPHS_FIFO,
93 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9G45_BASE_UDPHS,
98 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [2] = {
102 .start = AT91SAM9G45_ID_UDPHS,
103 .end = AT91SAM9G45_ID_UDPHS,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
109 [idx] = { \
110 .name = nam, \
111 .index = idx, \
112 .fifo_size = maxpkt, \
113 .nr_banks = maxbk, \
114 .can_dma = dma, \
115 .can_isoc = isoc, \
116 }
117
118static struct usba_ep_data usba_udc_ep[] __initdata = {
119 EP("ep0", 0, 64, 1, 0, 0),
120 EP("ep1", 1, 1024, 2, 1, 1),
121 EP("ep2", 2, 1024, 2, 1, 1),
122 EP("ep3", 3, 1024, 3, 1, 0),
123 EP("ep4", 4, 1024, 3, 1, 0),
124 EP("ep5", 5, 1024, 3, 1, 1),
125 EP("ep6", 6, 1024, 3, 1, 1),
126};
127
128#undef EP
129
130/*
131 * pdata doesn't have room for any endpoints, so we need to
132 * append room for the ones we need right after it.
133 */
134static struct {
135 struct usba_platform_data pdata;
136 struct usba_ep_data ep[7];
137} usba_udc_data;
138
139static struct platform_device at91_usba_udc_device = {
140 .name = "atmel_usba_udc",
141 .id = -1,
142 .dev = {
143 .platform_data = &usba_udc_data.pdata,
144 },
145 .resource = usba_udc_resources,
146 .num_resources = ARRAY_SIZE(usba_udc_resources),
147};
148
149void __init at91_add_device_usba(struct usba_platform_data *data)
150{
151 usba_udc_data.pdata.vbus_pin = -EINVAL;
152 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
153 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
154
155 if (data && data->vbus_pin > 0) {
156 at91_set_gpio_input(data->vbus_pin, 0);
157 at91_set_deglitch(data->vbus_pin, 1);
158 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
159 }
160
161 /* Pullup pin is handled internally by USB device peripheral */
162
163 /* Clocks */
164 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
165 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
166
167 platform_device_register(&at91_usba_udc_device);
168}
169#else
170void __init at91_add_device_usba(struct usba_platform_data *data) {}
171#endif
172
173
174/* --------------------------------------------------------------------
175 * Ethernet
176 * -------------------------------------------------------------------- */
177
178#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
179static u64 eth_dmamask = DMA_BIT_MASK(32);
180static struct at91_eth_data eth_data;
181
182static struct resource eth_resources[] = {
183 [0] = {
184 .start = AT91SAM9G45_BASE_EMAC,
185 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = AT91SAM9G45_ID_EMAC,
190 .end = AT91SAM9G45_ID_EMAC,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct platform_device at91sam9g45_eth_device = {
196 .name = "macb",
197 .id = -1,
198 .dev = {
199 .dma_mask = &eth_dmamask,
200 .coherent_dma_mask = DMA_BIT_MASK(32),
201 .platform_data = &eth_data,
202 },
203 .resource = eth_resources,
204 .num_resources = ARRAY_SIZE(eth_resources),
205};
206
207void __init at91_add_device_eth(struct at91_eth_data *data)
208{
209 if (!data)
210 return;
211
212 if (data->phy_irq_pin) {
213 at91_set_gpio_input(data->phy_irq_pin, 0);
214 at91_set_deglitch(data->phy_irq_pin, 1);
215 }
216
217 /* Pins used for MII and RMII */
218 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
219 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
220 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
221 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
222 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
223 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
224 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
225 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
226 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
227 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
228
229 if (!data->is_rmii) {
230 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
231 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
232 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
233 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
234 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
235 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
236 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
237 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
238 }
239
240 eth_data = *data;
241 platform_device_register(&at91sam9g45_eth_device);
242}
243#else
244void __init at91_add_device_eth(struct at91_eth_data *data) {}
245#endif
246
247
248/* --------------------------------------------------------------------
249 * NAND / SmartMedia
250 * -------------------------------------------------------------------- */
251
252#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
253static struct atmel_nand_data nand_data;
254
255#define NAND_BASE AT91_CHIPSELECT_3
256
257static struct resource nand_resources[] = {
258 [0] = {
259 .start = NAND_BASE,
260 .end = NAND_BASE + SZ_256M - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 [1] = {
264 .start = AT91_BASE_SYS + AT91_ECC,
265 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
266 .flags = IORESOURCE_MEM,
267 }
268};
269
270static struct platform_device at91sam9g45_nand_device = {
271 .name = "atmel_nand",
272 .id = -1,
273 .dev = {
274 .platform_data = &nand_data,
275 },
276 .resource = nand_resources,
277 .num_resources = ARRAY_SIZE(nand_resources),
278};
279
280void __init at91_add_device_nand(struct atmel_nand_data *data)
281{
282 unsigned long csa;
283
284 if (!data)
285 return;
286
287 csa = at91_sys_read(AT91_MATRIX_EBICSA);
288 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
289
290 /* enable pin */
291 if (data->enable_pin)
292 at91_set_gpio_output(data->enable_pin, 1);
293
294 /* ready/busy pin */
295 if (data->rdy_pin)
296 at91_set_gpio_input(data->rdy_pin, 1);
297
298 /* card detect pin */
299 if (data->det_pin)
300 at91_set_gpio_input(data->det_pin, 1);
301
302 nand_data = *data;
303 platform_device_register(&at91sam9g45_nand_device);
304}
305#else
306void __init at91_add_device_nand(struct atmel_nand_data *data) {}
307#endif
308
309
310/* --------------------------------------------------------------------
311 * TWI (i2c)
312 * -------------------------------------------------------------------- */
313
314/*
315 * Prefer the GPIO code since the TWI controller isn't robust
316 * (gets overruns and underruns under load) and can only issue
317 * repeated STARTs in one scenario (the driver doesn't yet handle them).
318 */
319#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
320static struct i2c_gpio_platform_data pdata_i2c0 = {
321 .sda_pin = AT91_PIN_PA20,
322 .sda_is_open_drain = 1,
323 .scl_pin = AT91_PIN_PA21,
324 .scl_is_open_drain = 1,
325 .udelay = 2, /* ~100 kHz */
326};
327
328static struct platform_device at91sam9g45_twi0_device = {
329 .name = "i2c-gpio",
330 .id = 0,
331 .dev.platform_data = &pdata_i2c0,
332};
333
334static struct i2c_gpio_platform_data pdata_i2c1 = {
335 .sda_pin = AT91_PIN_PB10,
336 .sda_is_open_drain = 1,
337 .scl_pin = AT91_PIN_PB11,
338 .scl_is_open_drain = 1,
339 .udelay = 2, /* ~100 kHz */
340};
341
342static struct platform_device at91sam9g45_twi1_device = {
343 .name = "i2c-gpio",
344 .id = 1,
345 .dev.platform_data = &pdata_i2c1,
346};
347
348void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
349{
350 i2c_register_board_info(i2c_id, devices, nr_devices);
351
352 if (i2c_id == 0) {
353 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
354 at91_set_multi_drive(AT91_PIN_PA20, 1);
355
356 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
357 at91_set_multi_drive(AT91_PIN_PA21, 1);
358
359 platform_device_register(&at91sam9g45_twi0_device);
360 } else {
361 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
362 at91_set_multi_drive(AT91_PIN_PB10, 1);
363
364 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
365 at91_set_multi_drive(AT91_PIN_PB11, 1);
366
367 platform_device_register(&at91sam9g45_twi1_device);
368 }
369}
370
371#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
372static struct resource twi0_resources[] = {
373 [0] = {
374 .start = AT91SAM9G45_BASE_TWI0,
375 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = AT91SAM9G45_ID_TWI0,
380 .end = AT91SAM9G45_ID_TWI0,
381 .flags = IORESOURCE_IRQ,
382 },
383};
384
385static struct platform_device at91sam9g45_twi0_device = {
386 .name = "at91_i2c",
387 .id = 0,
388 .resource = twi0_resources,
389 .num_resources = ARRAY_SIZE(twi0_resources),
390};
391
392static struct resource twi1_resources[] = {
393 [0] = {
394 .start = AT91SAM9G45_BASE_TWI1,
395 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = AT91SAM9G45_ID_TWI1,
400 .end = AT91SAM9G45_ID_TWI1,
401 .flags = IORESOURCE_IRQ,
402 },
403};
404
405static struct platform_device at91sam9g45_twi1_device = {
406 .name = "at91_i2c",
407 .id = 1,
408 .resource = twi1_resources,
409 .num_resources = ARRAY_SIZE(twi1_resources),
410};
411
412void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
413{
414 i2c_register_board_info(i2c_id, devices, nr_devices);
415
416 /* pins used for TWI interface */
417 if (i2c_id == 0) {
418 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PA20, 1);
420
421 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PA21, 1);
423
424 platform_device_register(&at91sam9g45_twi0_device);
425 } else {
426 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
427 at91_set_multi_drive(AT91_PIN_PB10, 1);
428
429 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
430 at91_set_multi_drive(AT91_PIN_PB11, 1);
431
432 platform_device_register(&at91sam9g45_twi1_device);
433 }
434}
435#else
436void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
437#endif
438
439
440/* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT91SAM9G45_BASE_SPI0,
450 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT91SAM9G45_ID_SPI0,
455 .end = AT91SAM9G45_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458};
459
460static struct platform_device at91sam9g45_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469};
470
471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
472
473static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT91SAM9G45_BASE_SPI1,
476 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT91SAM9G45_ID_SPI1,
481 .end = AT91SAM9G45_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device at91sam9g45_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495};
496
497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
498
499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500{
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
534
535 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
536 platform_device_register(&at91sam9g45_spi0_device);
537 }
538 if (enable_spi1) {
539 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
540 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
541 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
542
543 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
544 platform_device_register(&at91sam9g45_spi1_device);
545 }
546}
547#else
548void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
549#endif
550
551
552/* --------------------------------------------------------------------
553 * LCD Controller
554 * -------------------------------------------------------------------- */
555
556#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
557static u64 lcdc_dmamask = DMA_BIT_MASK(32);
558static struct atmel_lcdfb_info lcdc_data;
559
560static struct resource lcdc_resources[] = {
561 [0] = {
562 .start = AT91SAM9G45_LCDC_BASE,
563 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 [1] = {
567 .start = AT91SAM9G45_ID_LCDC,
568 .end = AT91SAM9G45_ID_LCDC,
569 .flags = IORESOURCE_IRQ,
570 },
571};
572
573static struct platform_device at91_lcdc_device = {
574 .name = "atmel_lcdfb",
575 .id = 0,
576 .dev = {
577 .dma_mask = &lcdc_dmamask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 .platform_data = &lcdc_data,
580 },
581 .resource = lcdc_resources,
582 .num_resources = ARRAY_SIZE(lcdc_resources),
583};
584
585void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
586{
587 if (!data)
588 return;
589
590 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
591
592 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
593 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
594 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
595 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
596 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
597 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
598 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
599 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
600 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
601 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
602 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
603 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
604 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
605 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
606 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
607 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
608 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
609 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
610 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
611 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
612 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
613 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
614 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
615 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
616 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
617 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
618 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
619 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
620 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
621
622 lcdc_data = *data;
623 platform_device_register(&at91_lcdc_device);
624}
625#else
626void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
627#endif
628
629
630/* --------------------------------------------------------------------
631 * Timer/Counter block
632 * -------------------------------------------------------------------- */
633
634#ifdef CONFIG_ATMEL_TCLIB
635static struct resource tcb0_resources[] = {
636 [0] = {
637 .start = AT91SAM9G45_BASE_TCB0,
638 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = AT91SAM9G45_ID_TCB,
643 .end = AT91SAM9G45_ID_TCB,
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct platform_device at91sam9g45_tcb0_device = {
649 .name = "atmel_tcb",
650 .id = 0,
651 .resource = tcb0_resources,
652 .num_resources = ARRAY_SIZE(tcb0_resources),
653};
654
655/* TCB1 begins with TC3 */
656static struct resource tcb1_resources[] = {
657 [0] = {
658 .start = AT91SAM9G45_BASE_TCB1,
659 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 [1] = {
663 .start = AT91SAM9G45_ID_TCB,
664 .end = AT91SAM9G45_ID_TCB,
665 .flags = IORESOURCE_IRQ,
666 },
667};
668
669static struct platform_device at91sam9g45_tcb1_device = {
670 .name = "atmel_tcb",
671 .id = 1,
672 .resource = tcb1_resources,
673 .num_resources = ARRAY_SIZE(tcb1_resources),
674};
675
676static void __init at91_add_device_tc(void)
677{
678 /* this chip has one clock and irq for all six TC channels */
679 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
680 platform_device_register(&at91sam9g45_tcb0_device);
681 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
682 platform_device_register(&at91sam9g45_tcb1_device);
683}
684#else
685static void __init at91_add_device_tc(void) { }
686#endif
687
688
689/* --------------------------------------------------------------------
690 * RTC
691 * -------------------------------------------------------------------- */
692
693#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
694static struct platform_device at91sam9g45_rtc_device = {
695 .name = "at91_rtc",
696 .id = -1,
697 .num_resources = 0,
698};
699
700static void __init at91_add_device_rtc(void)
701{
702 platform_device_register(&at91sam9g45_rtc_device);
703}
704#else
705static void __init at91_add_device_rtc(void) {}
706#endif
707
708
709/* --------------------------------------------------------------------
710 * RTT
711 * -------------------------------------------------------------------- */
712
713static struct resource rtt_resources[] = {
714 {
715 .start = AT91_BASE_SYS + AT91_RTT,
716 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
717 .flags = IORESOURCE_MEM,
718 }
719};
720
721static struct platform_device at91sam9g45_rtt_device = {
722 .name = "at91_rtt",
723 .id = 0,
724 .resource = rtt_resources,
725 .num_resources = ARRAY_SIZE(rtt_resources),
726};
727
728static void __init at91_add_device_rtt(void)
729{
730 platform_device_register(&at91sam9g45_rtt_device);
731}
732
733
734/* --------------------------------------------------------------------
735 * Watchdog
736 * -------------------------------------------------------------------- */
737
738#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
739static struct platform_device at91sam9g45_wdt_device = {
740 .name = "at91_wdt",
741 .id = -1,
742 .num_resources = 0,
743};
744
745static void __init at91_add_device_watchdog(void)
746{
747 platform_device_register(&at91sam9g45_wdt_device);
748}
749#else
750static void __init at91_add_device_watchdog(void) {}
751#endif
752
753
754/* --------------------------------------------------------------------
755 * PWM
756 * --------------------------------------------------------------------*/
757
758#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
759static u32 pwm_mask;
760
761static struct resource pwm_resources[] = {
762 [0] = {
763 .start = AT91SAM9G45_BASE_PWMC,
764 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = AT91SAM9G45_ID_PWMC,
769 .end = AT91SAM9G45_ID_PWMC,
770 .flags = IORESOURCE_IRQ,
771 },
772};
773
774static struct platform_device at91sam9g45_pwm0_device = {
775 .name = "atmel_pwm",
776 .id = -1,
777 .dev = {
778 .platform_data = &pwm_mask,
779 },
780 .resource = pwm_resources,
781 .num_resources = ARRAY_SIZE(pwm_resources),
782};
783
784void __init at91_add_device_pwm(u32 mask)
785{
786 if (mask & (1 << AT91_PWM0))
787 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
788
789 if (mask & (1 << AT91_PWM1))
790 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
791
792 if (mask & (1 << AT91_PWM2))
793 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
794
795 if (mask & (1 << AT91_PWM3))
796 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
797
798 pwm_mask = mask;
799
800 platform_device_register(&at91sam9g45_pwm0_device);
801}
802#else
803void __init at91_add_device_pwm(u32 mask) {}
804#endif
805
806
807/* --------------------------------------------------------------------
808 * SSC -- Synchronous Serial Controller
809 * -------------------------------------------------------------------- */
810
811#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
812static u64 ssc0_dmamask = DMA_BIT_MASK(32);
813
814static struct resource ssc0_resources[] = {
815 [0] = {
816 .start = AT91SAM9G45_BASE_SSC0,
817 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
818 .flags = IORESOURCE_MEM,
819 },
820 [1] = {
821 .start = AT91SAM9G45_ID_SSC0,
822 .end = AT91SAM9G45_ID_SSC0,
823 .flags = IORESOURCE_IRQ,
824 },
825};
826
827static struct platform_device at91sam9g45_ssc0_device = {
828 .name = "ssc",
829 .id = 0,
830 .dev = {
831 .dma_mask = &ssc0_dmamask,
832 .coherent_dma_mask = DMA_BIT_MASK(32),
833 },
834 .resource = ssc0_resources,
835 .num_resources = ARRAY_SIZE(ssc0_resources),
836};
837
838static inline void configure_ssc0_pins(unsigned pins)
839{
840 if (pins & ATMEL_SSC_TF)
841 at91_set_A_periph(AT91_PIN_PD1, 1);
842 if (pins & ATMEL_SSC_TK)
843 at91_set_A_periph(AT91_PIN_PD0, 1);
844 if (pins & ATMEL_SSC_TD)
845 at91_set_A_periph(AT91_PIN_PD2, 1);
846 if (pins & ATMEL_SSC_RD)
847 at91_set_A_periph(AT91_PIN_PD3, 1);
848 if (pins & ATMEL_SSC_RK)
849 at91_set_A_periph(AT91_PIN_PD4, 1);
850 if (pins & ATMEL_SSC_RF)
851 at91_set_A_periph(AT91_PIN_PD5, 1);
852}
853
854static u64 ssc1_dmamask = DMA_BIT_MASK(32);
855
856static struct resource ssc1_resources[] = {
857 [0] = {
858 .start = AT91SAM9G45_BASE_SSC1,
859 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
860 .flags = IORESOURCE_MEM,
861 },
862 [1] = {
863 .start = AT91SAM9G45_ID_SSC1,
864 .end = AT91SAM9G45_ID_SSC1,
865 .flags = IORESOURCE_IRQ,
866 },
867};
868
869static struct platform_device at91sam9g45_ssc1_device = {
870 .name = "ssc",
871 .id = 1,
872 .dev = {
873 .dma_mask = &ssc1_dmamask,
874 .coherent_dma_mask = DMA_BIT_MASK(32),
875 },
876 .resource = ssc1_resources,
877 .num_resources = ARRAY_SIZE(ssc1_resources),
878};
879
880static inline void configure_ssc1_pins(unsigned pins)
881{
882 if (pins & ATMEL_SSC_TF)
883 at91_set_A_periph(AT91_PIN_PD14, 1);
884 if (pins & ATMEL_SSC_TK)
885 at91_set_A_periph(AT91_PIN_PD12, 1);
886 if (pins & ATMEL_SSC_TD)
887 at91_set_A_periph(AT91_PIN_PD10, 1);
888 if (pins & ATMEL_SSC_RD)
889 at91_set_A_periph(AT91_PIN_PD11, 1);
890 if (pins & ATMEL_SSC_RK)
891 at91_set_A_periph(AT91_PIN_PD13, 1);
892 if (pins & ATMEL_SSC_RF)
893 at91_set_A_periph(AT91_PIN_PD15, 1);
894}
895
896/*
897 * SSC controllers are accessed through library code, instead of any
898 * kind of all-singing/all-dancing driver. For example one could be
899 * used by a particular I2S audio codec's driver, while another one
900 * on the same system might be used by a custom data capture driver.
901 */
902void __init at91_add_device_ssc(unsigned id, unsigned pins)
903{
904 struct platform_device *pdev;
905
906 /*
907 * NOTE: caller is responsible for passing information matching
908 * "pins" to whatever will be using each particular controller.
909 */
910 switch (id) {
911 case AT91SAM9G45_ID_SSC0:
912 pdev = &at91sam9g45_ssc0_device;
913 configure_ssc0_pins(pins);
914 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
915 break;
916 case AT91SAM9G45_ID_SSC1:
917 pdev = &at91sam9g45_ssc1_device;
918 configure_ssc1_pins(pins);
919 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
920 break;
921 default:
922 return;
923 }
924
925 platform_device_register(pdev);
926}
927
928#else
929void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
930#endif
931
932
933/* --------------------------------------------------------------------
934 * UART
935 * -------------------------------------------------------------------- */
936
937#if defined(CONFIG_SERIAL_ATMEL)
938static struct resource dbgu_resources[] = {
939 [0] = {
940 .start = AT91_VA_BASE_SYS + AT91_DBGU,
941 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = AT91_ID_SYS,
946 .end = AT91_ID_SYS,
947 .flags = IORESOURCE_IRQ,
948 },
949};
950
951static struct atmel_uart_data dbgu_data = {
952 .use_dma_tx = 0,
953 .use_dma_rx = 0,
954 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
955};
956
957static u64 dbgu_dmamask = DMA_BIT_MASK(32);
958
959static struct platform_device at91sam9g45_dbgu_device = {
960 .name = "atmel_usart",
961 .id = 0,
962 .dev = {
963 .dma_mask = &dbgu_dmamask,
964 .coherent_dma_mask = DMA_BIT_MASK(32),
965 .platform_data = &dbgu_data,
966 },
967 .resource = dbgu_resources,
968 .num_resources = ARRAY_SIZE(dbgu_resources),
969};
970
971static inline void configure_dbgu_pins(void)
972{
973 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
974 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
975}
976
977static struct resource uart0_resources[] = {
978 [0] = {
979 .start = AT91SAM9G45_BASE_US0,
980 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
982 },
983 [1] = {
984 .start = AT91SAM9G45_ID_US0,
985 .end = AT91SAM9G45_ID_US0,
986 .flags = IORESOURCE_IRQ,
987 },
988};
989
990static struct atmel_uart_data uart0_data = {
991 .use_dma_tx = 1,
992 .use_dma_rx = 1,
993};
994
995static u64 uart0_dmamask = DMA_BIT_MASK(32);
996
997static struct platform_device at91sam9g45_uart0_device = {
998 .name = "atmel_usart",
999 .id = 1,
1000 .dev = {
1001 .dma_mask = &uart0_dmamask,
1002 .coherent_dma_mask = DMA_BIT_MASK(32),
1003 .platform_data = &uart0_data,
1004 },
1005 .resource = uart0_resources,
1006 .num_resources = ARRAY_SIZE(uart0_resources),
1007};
1008
1009static inline void configure_usart0_pins(unsigned pins)
1010{
1011 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1012 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1013
1014 if (pins & ATMEL_UART_RTS)
1015 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1016 if (pins & ATMEL_UART_CTS)
1017 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1018}
1019
1020static struct resource uart1_resources[] = {
1021 [0] = {
1022 .start = AT91SAM9G45_BASE_US1,
1023 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1024 .flags = IORESOURCE_MEM,
1025 },
1026 [1] = {
1027 .start = AT91SAM9G45_ID_US1,
1028 .end = AT91SAM9G45_ID_US1,
1029 .flags = IORESOURCE_IRQ,
1030 },
1031};
1032
1033static struct atmel_uart_data uart1_data = {
1034 .use_dma_tx = 1,
1035 .use_dma_rx = 1,
1036};
1037
1038static u64 uart1_dmamask = DMA_BIT_MASK(32);
1039
1040static struct platform_device at91sam9g45_uart1_device = {
1041 .name = "atmel_usart",
1042 .id = 2,
1043 .dev = {
1044 .dma_mask = &uart1_dmamask,
1045 .coherent_dma_mask = DMA_BIT_MASK(32),
1046 .platform_data = &uart1_data,
1047 },
1048 .resource = uart1_resources,
1049 .num_resources = ARRAY_SIZE(uart1_resources),
1050};
1051
1052static inline void configure_usart1_pins(unsigned pins)
1053{
1054 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1055 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1056
1057 if (pins & ATMEL_UART_RTS)
1058 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1059 if (pins & ATMEL_UART_CTS)
1060 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1061}
1062
1063static struct resource uart2_resources[] = {
1064 [0] = {
1065 .start = AT91SAM9G45_BASE_US2,
1066 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1067 .flags = IORESOURCE_MEM,
1068 },
1069 [1] = {
1070 .start = AT91SAM9G45_ID_US2,
1071 .end = AT91SAM9G45_ID_US2,
1072 .flags = IORESOURCE_IRQ,
1073 },
1074};
1075
1076static struct atmel_uart_data uart2_data = {
1077 .use_dma_tx = 1,
1078 .use_dma_rx = 1,
1079};
1080
1081static u64 uart2_dmamask = DMA_BIT_MASK(32);
1082
1083static struct platform_device at91sam9g45_uart2_device = {
1084 .name = "atmel_usart",
1085 .id = 3,
1086 .dev = {
1087 .dma_mask = &uart2_dmamask,
1088 .coherent_dma_mask = DMA_BIT_MASK(32),
1089 .platform_data = &uart2_data,
1090 },
1091 .resource = uart2_resources,
1092 .num_resources = ARRAY_SIZE(uart2_resources),
1093};
1094
1095static inline void configure_usart2_pins(unsigned pins)
1096{
1097 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1098 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1099
1100 if (pins & ATMEL_UART_RTS)
1101 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1102 if (pins & ATMEL_UART_CTS)
1103 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1104}
1105
1106static struct resource uart3_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_US3,
1109 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = AT91SAM9G45_ID_US3,
1114 .end = AT91SAM9G45_ID_US3,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117};
1118
1119static struct atmel_uart_data uart3_data = {
1120 .use_dma_tx = 1,
1121 .use_dma_rx = 1,
1122};
1123
1124static u64 uart3_dmamask = DMA_BIT_MASK(32);
1125
1126static struct platform_device at91sam9g45_uart3_device = {
1127 .name = "atmel_usart",
1128 .id = 4,
1129 .dev = {
1130 .dma_mask = &uart3_dmamask,
1131 .coherent_dma_mask = DMA_BIT_MASK(32),
1132 .platform_data = &uart3_data,
1133 },
1134 .resource = uart3_resources,
1135 .num_resources = ARRAY_SIZE(uart3_resources),
1136};
1137
1138static inline void configure_usart3_pins(unsigned pins)
1139{
1140 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1141 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1142
1143 if (pins & ATMEL_UART_RTS)
1144 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1145 if (pins & ATMEL_UART_CTS)
1146 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1147}
1148
1149static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1150struct platform_device *atmel_default_console_device; /* the serial console device */
1151
1152void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1153{
1154 struct platform_device *pdev;
1155
1156 switch (id) {
1157 case 0: /* DBGU */
1158 pdev = &at91sam9g45_dbgu_device;
1159 configure_dbgu_pins();
1160 at91_clock_associate("mck", &pdev->dev, "usart");
1161 break;
1162 case AT91SAM9G45_ID_US0:
1163 pdev = &at91sam9g45_uart0_device;
1164 configure_usart0_pins(pins);
1165 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1166 break;
1167 case AT91SAM9G45_ID_US1:
1168 pdev = &at91sam9g45_uart1_device;
1169 configure_usart1_pins(pins);
1170 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1171 break;
1172 case AT91SAM9G45_ID_US2:
1173 pdev = &at91sam9g45_uart2_device;
1174 configure_usart2_pins(pins);
1175 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1176 break;
1177 case AT91SAM9G45_ID_US3:
1178 pdev = &at91sam9g45_uart3_device;
1179 configure_usart3_pins(pins);
1180 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1181 break;
1182 default:
1183 return;
1184 }
1185 pdev->id = portnr; /* update to mapped ID */
1186
1187 if (portnr < ATMEL_MAX_UART)
1188 at91_uarts[portnr] = pdev;
1189}
1190
1191void __init at91_set_serial_console(unsigned portnr)
1192{
1193 if (portnr < ATMEL_MAX_UART)
1194 atmel_default_console_device = at91_uarts[portnr];
1195}
1196
1197void __init at91_add_device_serial(void)
1198{
1199 int i;
1200
1201 for (i = 0; i < ATMEL_MAX_UART; i++) {
1202 if (at91_uarts[i])
1203 platform_device_register(at91_uarts[i]);
1204 }
1205
1206 if (!atmel_default_console_device)
1207 printk(KERN_INFO "AT91: No default serial console defined.\n");
1208}
1209#else
1210void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1211void __init at91_set_serial_console(unsigned portnr) {}
1212void __init at91_add_device_serial(void) {}
1213#endif
1214
1215
1216/* -------------------------------------------------------------------- */
1217/*
1218 * These devices are always present and don't need any board-specific
1219 * setup.
1220 */
1221static int __init at91_add_standard_devices(void)
1222{
1223 at91_add_device_rtc();
1224 at91_add_device_rtt();
1225 at91_add_device_watchdog();
1226 at91_add_device_tc();
1227 return 0;
1228}
1229
1230arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 970fd6b6753e..61e52b66bc72 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -174,6 +174,16 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
174 }, 174 },
175}; 175};
176 176
177/*
178 * IDE (CF True IDE mode)
179 */
180static struct at91_cf_data afeb9260_cf_data = {
181 .chipselect = 4,
182 .irq_pin = AT91_PIN_PA6,
183 .rst_pin = AT91_PIN_PA7,
184 .flags = AT91_CF_TRUE_IDE,
185};
186
177static void __init afeb9260_board_init(void) 187static void __init afeb9260_board_init(void)
178{ 188{
179 /* Serial */ 189 /* Serial */
@@ -202,6 +212,8 @@ static void __init afeb9260_board_init(void)
202 ARRAY_SIZE(afeb9260_i2c_devices)); 212 ARRAY_SIZE(afeb9260_i2c_devices));
203 /* Audio */ 213 /* Audio */
204 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); 214 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
215 /* IDE */
216 at91_add_device_cf(&afeb9260_cf_data);
205} 217}
206 218
207MACHINE_START(AFEB9260, "Custom afeb9260 board") 219MACHINE_START(AFEB9260, "Custom afeb9260 board")
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
new file mode 100644
index 000000000000..4bc2e9f6ebb5
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -0,0 +1,385 @@
1/*
2 * linux/arch/arm/mach-at91/board-cpu9krea.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/clk.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <linux/mtd/physmap.h>
32
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/board.h>
43#include <mach/gpio.h>
44#include <mach/at91sam9_smc.h>
45#include <mach/at91sam9260_matrix.h>
46
47#include "sam9_smc.h"
48#include "generic.h"
49
50static void __init cpu9krea_map_io(void)
51{
52 /* Initialize processor: 18.432 MHz crystal */
53 at91sam9260_initialize(18432000);
54
55 /* DGBU on ttyS0. (Rx & Tx only) */
56 at91_register_uart(0, 0, 0);
57
58 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
59 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
60 ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
61 ATMEL_UART_DCD | ATMEL_UART_RI);
62
63 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
64 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
65 ATMEL_UART_RTS);
66
67 /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
68 at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
69 ATMEL_UART_RTS);
70
71 /* USART3 on ttyS4. (Rx, Tx) */
72 at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
73
74 /* USART4 on ttyS5. (Rx, Tx) */
75 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
76
77 /* USART5 on ttyS6. (Rx, Tx) */
78 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
79
80 /* set serial console to ttyS0 (ie, DBGU) */
81 at91_set_serial_console(0);
82}
83
84static void __init cpu9krea_init_irq(void)
85{
86 at91sam9260_init_interrupts(NULL);
87}
88
89/*
90 * USB Host port
91 */
92static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
93 .ports = 2,
94};
95
96/*
97 * USB Device port
98 */
99static struct at91_udc_data __initdata cpu9krea_udc_data = {
100 .vbus_pin = AT91_PIN_PC8,
101 .pullup_pin = 0, /* pull-up driven by UDC */
102};
103
104/*
105 * MACB Ethernet device
106 */
107static struct at91_eth_data __initdata cpu9krea_macb_data = {
108 .is_rmii = 1,
109};
110
111/*
112 * NAND flash
113 */
114static struct atmel_nand_data __initdata cpu9krea_nand_data = {
115 .ale = 21,
116 .cle = 22,
117 .rdy_pin = AT91_PIN_PC13,
118 .enable_pin = AT91_PIN_PC14,
119 .bus_width_16 = 0,
120};
121
122#ifdef CONFIG_MACH_CPU9260
123static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
124 .ncs_read_setup = 0,
125 .nrd_setup = 1,
126 .ncs_write_setup = 0,
127 .nwe_setup = 1,
128
129 .ncs_read_pulse = 3,
130 .nrd_pulse = 3,
131 .ncs_write_pulse = 3,
132 .nwe_pulse = 3,
133
134 .read_cycle = 5,
135 .write_cycle = 5,
136
137 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
138 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
139 .tdf_cycles = 2,
140};
141#else
142static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
143 .ncs_read_setup = 0,
144 .nrd_setup = 2,
145 .ncs_write_setup = 0,
146 .nwe_setup = 2,
147
148 .ncs_read_pulse = 4,
149 .nrd_pulse = 4,
150 .ncs_write_pulse = 4,
151 .nwe_pulse = 4,
152
153 .read_cycle = 7,
154 .write_cycle = 7,
155
156 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
157 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
158 .tdf_cycles = 3,
159};
160#endif
161
162static void __init cpu9krea_add_device_nand(void)
163{
164 sam9_smc_configure(3, &cpu9krea_nand_smc_config);
165 at91_add_device_nand(&cpu9krea_nand_data);
166}
167
168/*
169 * NOR flash
170 */
171static struct physmap_flash_data cpuat9260_nor_data = {
172 .width = 2,
173};
174
175#define NOR_BASE AT91_CHIPSELECT_0
176#define NOR_SIZE SZ_64M
177
178static struct resource nor_flash_resources[] = {
179 {
180 .start = NOR_BASE,
181 .end = NOR_BASE + NOR_SIZE - 1,
182 .flags = IORESOURCE_MEM,
183 }
184};
185
186static struct platform_device cpu9krea_nor_flash = {
187 .name = "physmap-flash",
188 .id = 0,
189 .dev = {
190 .platform_data = &cpuat9260_nor_data,
191 },
192 .resource = nor_flash_resources,
193 .num_resources = ARRAY_SIZE(nor_flash_resources),
194};
195
196#ifdef CONFIG_MACH_CPU9260
197static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
198 .ncs_read_setup = 0,
199 .nrd_setup = 1,
200 .ncs_write_setup = 0,
201 .nwe_setup = 1,
202
203 .ncs_read_pulse = 10,
204 .nrd_pulse = 10,
205 .ncs_write_pulse = 6,
206 .nwe_pulse = 6,
207
208 .read_cycle = 12,
209 .write_cycle = 8,
210
211 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
212 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
213 | AT91_SMC_DBW_16,
214 .tdf_cycles = 2,
215};
216#else
217static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
218 .ncs_read_setup = 0,
219 .nrd_setup = 1,
220 .ncs_write_setup = 0,
221 .nwe_setup = 1,
222
223 .ncs_read_pulse = 13,
224 .nrd_pulse = 13,
225 .ncs_write_pulse = 8,
226 .nwe_pulse = 8,
227
228 .read_cycle = 15,
229 .write_cycle = 10,
230
231 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
232 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
233 | AT91_SMC_DBW_16,
234 .tdf_cycles = 2,
235};
236#endif
237
238static __init void cpu9krea_add_device_nor(void)
239{
240 unsigned long csa;
241
242 csa = at91_sys_read(AT91_MATRIX_EBICSA);
243 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
244
245 /* configure chip-select 0 (NOR) */
246 sam9_smc_configure(0, &cpu9krea_nor_smc_config);
247
248 platform_device_register(&cpu9krea_nor_flash);
249}
250
251/*
252 * LEDs
253 */
254static struct gpio_led cpu9krea_leds[] = {
255 { /* LED1 */
256 .name = "LED1",
257 .gpio = AT91_PIN_PC11,
258 .active_low = 1,
259 .default_trigger = "timer",
260 },
261 { /* LED2 */
262 .name = "LED2",
263 .gpio = AT91_PIN_PC12,
264 .active_low = 1,
265 .default_trigger = "heartbeat",
266 },
267 { /* LED3 */
268 .name = "LED3",
269 .gpio = AT91_PIN_PC7,
270 .active_low = 1,
271 .default_trigger = "none",
272 },
273 { /* LED4 */
274 .name = "LED4",
275 .gpio = AT91_PIN_PC9,
276 .active_low = 1,
277 .default_trigger = "none",
278 }
279};
280
281static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
282 {
283 I2C_BOARD_INFO("rtc-ds1307", 0x68),
284 .type = "ds1339",
285 },
286};
287
288/*
289 * GPIO Buttons
290 */
291#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
292static struct gpio_keys_button cpu9krea_buttons[] = {
293 {
294 .gpio = AT91_PIN_PC3,
295 .code = BTN_0,
296 .desc = "BP1",
297 .active_low = 1,
298 .wakeup = 1,
299 },
300 {
301 .gpio = AT91_PIN_PB20,
302 .code = BTN_1,
303 .desc = "BP2",
304 .active_low = 1,
305 .wakeup = 1,
306 }
307};
308
309static struct gpio_keys_platform_data cpu9krea_button_data = {
310 .buttons = cpu9krea_buttons,
311 .nbuttons = ARRAY_SIZE(cpu9krea_buttons),
312};
313
314static struct platform_device cpu9krea_button_device = {
315 .name = "gpio-keys",
316 .id = -1,
317 .num_resources = 0,
318 .dev = {
319 .platform_data = &cpu9krea_button_data,
320 }
321};
322
323static void __init cpu9krea_add_device_buttons(void)
324{
325 at91_set_gpio_input(AT91_PIN_PC3, 1); /* BP1 */
326 at91_set_deglitch(AT91_PIN_PC3, 1);
327 at91_set_gpio_input(AT91_PIN_PB20, 1); /* BP2 */
328 at91_set_deglitch(AT91_PIN_PB20, 1);
329
330 platform_device_register(&cpu9krea_button_device);
331}
332#else
333static void __init cpu9krea_add_device_buttons(void)
334{
335}
336#endif
337
338/*
339 * MCI (SD/MMC)
340 */
341static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
342 .slot_b = 0,
343 .wire4 = 1,
344 .det_pin = AT91_PIN_PA29,
345};
346
347static void __init cpu9krea_board_init(void)
348{
349 /* NOR */
350 cpu9krea_add_device_nor();
351 /* Serial */
352 at91_add_device_serial();
353 /* USB Host */
354 at91_add_device_usbh(&cpu9krea_usbh_data);
355 /* USB Device */
356 at91_add_device_udc(&cpu9krea_udc_data);
357 /* NAND */
358 cpu9krea_add_device_nand();
359 /* Ethernet */
360 at91_add_device_eth(&cpu9krea_macb_data);
361 /* MMC */
362 at91_add_device_mmc(0, &cpu9krea_mmc_data);
363 /* I2C */
364 at91_add_device_i2c(cpu9krea_i2c_devices,
365 ARRAY_SIZE(cpu9krea_i2c_devices));
366 /* LEDs */
367 at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds));
368 /* Push Buttons */
369 cpu9krea_add_device_buttons();
370}
371
372#ifdef CONFIG_MACH_CPU9260
373MACHINE_START(CPUAT9260, "Eukrea CPU9260")
374#else
375MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
376#endif
377 /* Maintainer: Eric Benard - EUKREA Electromatique */
378 .phys_io = AT91_BASE_SYS,
379 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
380 .boot_params = AT91_SDRAM_BASE + 0x100,
381 .timer = &at91sam926x_timer,
382 .map_io = cpu9krea_map_io,
383 .init_irq = cpu9krea_init_irq,
384 .init_machine = cpu9krea_board_init,
385MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
new file mode 100644
index 000000000000..a28d99656190
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -0,0 +1,185 @@
1/*
2 * linux/arch/arm/mach-at91/board-cpuat91.c
3 *
4 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/mtd/physmap.h>
27#include <linux/mtd/plat-ram.h>
28
29#include <mach/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/board.h>
39#include <mach/gpio.h>
40#include <mach/at91rm9200_mc.h>
41
42#include "generic.h"
43
44static struct gpio_led cpuat91_leds[] = {
45 {
46 .name = "led1",
47 .default_trigger = "heartbeat",
48 .active_low = 1,
49 .gpio = AT91_PIN_PC0,
50 },
51};
52
53static void __init cpuat91_map_io(void)
54{
55 /* Initialize processor: 18.432 MHz crystal */
56 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
57
58 /* DBGU on ttyS0. (Rx & Tx only) */
59 at91_register_uart(0, 0, 0);
60
61 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
62 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
63 ATMEL_UART_RTS);
64
65 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
66 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
67 ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
68 ATMEL_UART_DCD | ATMEL_UART_RI);
69
70 /* USART2 on ttyS3 (Rx, Tx) */
71 at91_register_uart(AT91RM9200_ID_US2, 3, 0);
72
73 /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
74 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
75 ATMEL_UART_RTS);
76
77 /* set serial console to ttyS0 (ie, DBGU) */
78 at91_set_serial_console(0);
79}
80
81static void __init cpuat91_init_irq(void)
82{
83 at91rm9200_init_interrupts(NULL);
84}
85
86static struct at91_eth_data __initdata cpuat91_eth_data = {
87 .is_rmii = 1,
88};
89
90static struct at91_usbh_data __initdata cpuat91_usbh_data = {
91 .ports = 1,
92};
93
94static struct at91_udc_data __initdata cpuat91_udc_data = {
95 .vbus_pin = AT91_PIN_PC15,
96 .pullup_pin = AT91_PIN_PC14,
97};
98
99static struct at91_mmc_data __initdata cpuat91_mmc_data = {
100 .det_pin = AT91_PIN_PC2,
101 .wire4 = 1,
102};
103
104static struct physmap_flash_data cpuat91_flash_data = {
105 .width = 2,
106};
107
108static struct resource cpuat91_flash_resource = {
109 .start = AT91_CHIPSELECT_0,
110 .end = AT91_CHIPSELECT_0 + SZ_16M - 1,
111 .flags = IORESOURCE_MEM,
112};
113
114static struct platform_device cpuat91_norflash = {
115 .name = "physmap-flash",
116 .id = 0,
117 .dev = {
118 .platform_data = &cpuat91_flash_data,
119 },
120 .resource = &cpuat91_flash_resource,
121 .num_resources = 1,
122};
123
124#ifdef CONFIG_MTD_PLATRAM
125struct platdata_mtd_ram at91_sram_pdata = {
126 .mapname = "SRAM",
127 .bankwidth = 2,
128};
129
130static struct resource at91_sram_resource[] = {
131 [0] = {
132 .start = AT91RM9200_SRAM_BASE,
133 .end = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
134 .flags = IORESOURCE_MEM,
135 },
136};
137
138static struct platform_device at91_sram = {
139 .name = "mtd-ram",
140 .id = 0,
141 .resource = at91_sram_resource,
142 .num_resources = ARRAY_SIZE(at91_sram_resource),
143 .dev = {
144 .platform_data = &at91_sram_pdata,
145 },
146};
147#endif /* MTD_PLATRAM */
148
149static struct platform_device *platform_devices[] __initdata = {
150 &cpuat91_norflash,
151#ifdef CONFIG_MTD_PLATRAM
152 &at91_sram,
153#endif /* CONFIG_MTD_PLATRAM */
154};
155
156static void __init cpuat91_board_init(void)
157{
158 /* Serial */
159 at91_add_device_serial();
160 /* LEDs. */
161 at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
162 /* Ethernet */
163 at91_add_device_eth(&cpuat91_eth_data);
164 /* USB Host */
165 at91_add_device_usbh(&cpuat91_usbh_data);
166 /* USB Device */
167 at91_add_device_udc(&cpuat91_udc_data);
168 /* MMC */
169 at91_add_device_mmc(0, &cpuat91_mmc_data);
170 /* I2C */
171 at91_add_device_i2c(NULL, 0);
172 /* Platform devices */
173 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
174}
175
176MACHINE_START(CPUAT91, "Eukrea")
177 /* Maintainer: Eric Benard - EUKREA Electromatique */
178 .phys_io = AT91_BASE_SYS,
179 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
180 .boot_params = AT91_SDRAM_BASE + 0x100,
181 .timer = &at91rm9200_timer,
182 .map_io = cpuat91_map_io,
183 .init_irq = cpuat91_init_irq,
184 .init_machine = cpuat91_board_init,
185MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index d5266da55311..f9b19993a7a9 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -287,7 +287,11 @@ static void __init ek_add_device_ts(void) {}
287 */ 287 */
288static struct at73c213_board_info at73c213_data = { 288static struct at73c213_board_info at73c213_data = {
289 .ssc_id = 1, 289 .ssc_id = 1,
290#if defined(CONFIG_MACH_AT91SAM9261EK)
290 .shortname = "AT91SAM9261-EK external DAC", 291 .shortname = "AT91SAM9261-EK external DAC",
292#else
293 .shortname = "AT91SAM9G10-EK external DAC",
294#endif
291}; 295};
292 296
293#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) 297#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -414,6 +418,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
414 .default_monspecs = &at91fb_default_stn_monspecs, 418 .default_monspecs = &at91fb_default_stn_monspecs,
415 .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, 419 .atmel_lcdfb_power_control = at91_lcdc_stn_power_control,
416 .guard_time = 1, 420 .guard_time = 1,
421#if defined(CONFIG_MACH_AT91SAM9G10EK)
422 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
423#endif
417}; 424};
418 425
419#else 426#else
@@ -467,6 +474,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
467 .default_monspecs = &at91fb_default_tft_monspecs, 474 .default_monspecs = &at91fb_default_tft_monspecs,
468 .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, 475 .atmel_lcdfb_power_control = at91_lcdc_tft_power_control,
469 .guard_time = 1, 476 .guard_time = 1,
477#if defined(CONFIG_MACH_AT91SAM9G10EK)
478 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
479#endif
470}; 480};
471#endif 481#endif
472 482
@@ -600,7 +610,11 @@ static void __init ek_board_init(void)
600 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 610 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
601} 611}
602 612
613#if defined(CONFIG_MACH_AT91SAM9261EK)
603MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") 614MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
615#else
616MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
617#endif
604 /* Maintainer: Atmel */ 618 /* Maintainer: Atmel */
605 .phys_io = AT91_BASE_SYS, 619 .phys_io = AT91_BASE_SYS,
606 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, 620 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 57d52528f224..1bf7bd4cbe13 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -364,9 +364,9 @@ static void __init ek_add_device_buttons(void) {}
364 364
365/* 365/*
366 * AC97 366 * AC97
367 * reset_pin is not connected: NRST
367 */ 368 */
368static struct atmel_ac97_data ek_ac97_data = { 369static struct ac97c_platform_data ek_ac97_data = {
369 .reset_pin = AT91_PIN_PA13,
370}; 370};
371 371
372 372
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index a55398ed1211..ca470d504ea0 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -273,6 +273,7 @@ static void __init ek_add_device_buttons(void) {}
273static struct i2c_board_info __initdata ek_i2c_devices[] = { 273static struct i2c_board_info __initdata ek_i2c_devices[] = {
274 { 274 {
275 I2C_BOARD_INFO("24c512", 0x50), 275 I2C_BOARD_INFO("24c512", 0x50),
276 I2C_BOARD_INFO("wm8731", 0x1b),
276 }, 277 },
277}; 278};
278 279
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
new file mode 100644
index 000000000000..b8558eae5229
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -0,0 +1,389 @@
1/*
2 * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10G45-EK board
6 *
7 * Copyright (C) 2009 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
22#include <linux/fb.h>
23#include <linux/gpio_keys.h>
24#include <linux/input.h>
25#include <linux/leds.h>
26#include <linux/clk.h>
27
28#include <mach/hardware.h>
29#include <video/atmel_lcdc.h>
30
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/irq.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <mach/hardware.h>
40#include <mach/board.h>
41#include <mach/gpio.h>
42#include <mach/at91sam9_smc.h>
43#include <mach/at91_shdwc.h>
44
45#include "sam9_smc.h"
46#include "generic.h"
47
48
49static void __init ek_map_io(void)
50{
51 /* Initialize processor: 12.000 MHz crystal */
52 at91sam9g45_initialize(12000000);
53
54 /* DGBU on ttyS0. (Rx & Tx only) */
55 at91_register_uart(0, 0, 0);
56
57 /* USART0 not connected on the -EK board */
58 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
59 at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
60
61 /* set serial console to ttyS0 (ie, DBGU) */
62 at91_set_serial_console(0);
63}
64
65static void __init ek_init_irq(void)
66{
67 at91sam9g45_init_interrupts(NULL);
68}
69
70
71/*
72 * USB HS Host port (common to OHCI & EHCI)
73 */
74static struct at91_usbh_data __initdata ek_usbh_hs_data = {
75 .ports = 2,
76 .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
77};
78
79
80/*
81 * USB HS Device port
82 */
83static struct usba_platform_data __initdata ek_usba_udc_data = {
84 .vbus_pin = AT91_PIN_PB19,
85};
86
87
88/*
89 * SPI devices.
90 */
91static struct spi_board_info ek_spi_devices[] = {
92 { /* DataFlash chip */
93 .modalias = "mtd_dataflash",
94 .chip_select = 0,
95 .max_speed_hz = 15 * 1000 * 1000,
96 .bus_num = 0,
97 },
98};
99
100
101/*
102 * MACB Ethernet device
103 */
104static struct at91_eth_data __initdata ek_macb_data = {
105 .phy_irq_pin = AT91_PIN_PD5,
106 .is_rmii = 1,
107};
108
109
110/*
111 * NAND flash
112 */
113static struct mtd_partition __initdata ek_nand_partition[] = {
114 {
115 .name = "Partition 1",
116 .offset = 0,
117 .size = SZ_64M,
118 },
119 {
120 .name = "Partition 2",
121 .offset = MTDPART_OFS_NXTBLK,
122 .size = MTDPART_SIZ_FULL,
123 },
124};
125
126static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
127{
128 *num_partitions = ARRAY_SIZE(ek_nand_partition);
129 return ek_nand_partition;
130}
131
132/* det_pin is not connected */
133static struct atmel_nand_data __initdata ek_nand_data = {
134 .ale = 21,
135 .cle = 22,
136 .rdy_pin = AT91_PIN_PC8,
137 .enable_pin = AT91_PIN_PC14,
138 .partition_info = nand_partitions,
139#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
140 .bus_width_16 = 1,
141#else
142 .bus_width_16 = 0,
143#endif
144};
145
146static struct sam9_smc_config __initdata ek_nand_smc_config = {
147 .ncs_read_setup = 0,
148 .nrd_setup = 2,
149 .ncs_write_setup = 0,
150 .nwe_setup = 2,
151
152 .ncs_read_pulse = 4,
153 .nrd_pulse = 4,
154 .ncs_write_pulse = 4,
155 .nwe_pulse = 4,
156
157 .read_cycle = 7,
158 .write_cycle = 7,
159
160 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
161 .tdf_cycles = 3,
162};
163
164static void __init ek_add_device_nand(void)
165{
166 /* setup bus-width (8 or 16) */
167 if (ek_nand_data.bus_width_16)
168 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
169 else
170 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
171
172 /* configure chip-select 3 (NAND) */
173 sam9_smc_configure(3, &ek_nand_smc_config);
174
175 at91_add_device_nand(&ek_nand_data);
176}
177
178
179/*
180 * LCD Controller
181 */
182#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
183static struct fb_videomode at91_tft_vga_modes[] = {
184 {
185 .name = "LG",
186 .refresh = 60,
187 .xres = 480, .yres = 272,
188 .pixclock = KHZ2PICOS(9000),
189
190 .left_margin = 1, .right_margin = 1,
191 .upper_margin = 40, .lower_margin = 1,
192 .hsync_len = 45, .vsync_len = 1,
193
194 .sync = 0,
195 .vmode = FB_VMODE_NONINTERLACED,
196 },
197};
198
199static struct fb_monspecs at91fb_default_monspecs = {
200 .manufacturer = "LG",
201 .monitor = "LB043WQ1",
202
203 .modedb = at91_tft_vga_modes,
204 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
205 .hfmin = 15000,
206 .hfmax = 17640,
207 .vfmin = 57,
208 .vfmax = 67,
209};
210
211#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
212 | ATMEL_LCDC_DISTYPE_TFT \
213 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
214
215/* Driver datas */
216static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
217 .lcdcon_is_backlight = true,
218 .default_bpp = 32,
219 .default_dmacon = ATMEL_LCDC_DMAEN,
220 .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
221 .default_monspecs = &at91fb_default_monspecs,
222 .guard_time = 9,
223 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
224};
225
226#else
227static struct atmel_lcdfb_info __initdata ek_lcdc_data;
228#endif
229
230
231/*
232 * GPIO Buttons
233 */
234#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
235static struct gpio_keys_button ek_buttons[] = {
236 { /* BP1, "leftclic" */
237 .code = BTN_LEFT,
238 .gpio = AT91_PIN_PB6,
239 .active_low = 1,
240 .desc = "left_click",
241 .wakeup = 1,
242 },
243 { /* BP2, "rightclic" */
244 .code = BTN_RIGHT,
245 .gpio = AT91_PIN_PB7,
246 .active_low = 1,
247 .desc = "right_click",
248 .wakeup = 1,
249 },
250 /* BP3, "joystick" */
251 {
252 .code = KEY_LEFT,
253 .gpio = AT91_PIN_PB14,
254 .active_low = 1,
255 .desc = "Joystick Left",
256 },
257 {
258 .code = KEY_RIGHT,
259 .gpio = AT91_PIN_PB15,
260 .active_low = 1,
261 .desc = "Joystick Right",
262 },
263 {
264 .code = KEY_UP,
265 .gpio = AT91_PIN_PB16,
266 .active_low = 1,
267 .desc = "Joystick Up",
268 },
269 {
270 .code = KEY_DOWN,
271 .gpio = AT91_PIN_PB17,
272 .active_low = 1,
273 .desc = "Joystick Down",
274 },
275 {
276 .code = KEY_ENTER,
277 .gpio = AT91_PIN_PB18,
278 .active_low = 1,
279 .desc = "Joystick Press",
280 },
281};
282
283static struct gpio_keys_platform_data ek_button_data = {
284 .buttons = ek_buttons,
285 .nbuttons = ARRAY_SIZE(ek_buttons),
286};
287
288static struct platform_device ek_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &ek_button_data,
294 }
295};
296
297static void __init ek_add_device_buttons(void)
298{
299 int i;
300
301 for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
302 at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
303 at91_set_deglitch(ek_buttons[i].gpio, 1);
304 }
305
306 platform_device_register(&ek_button_device);
307}
308#else
309static void __init ek_add_device_buttons(void) {}
310#endif
311
312
313/*
314 * LEDs ... these could all be PWM-driven, for variable brightness
315 */
316static struct gpio_led ek_leds[] = {
317 { /* "top" led, red, powerled */
318 .name = "d8",
319 .gpio = AT91_PIN_PD30,
320 .default_trigger = "heartbeat",
321 },
322 { /* "left" led, green, userled2, pwm3 */
323 .name = "d6",
324 .gpio = AT91_PIN_PD0,
325 .active_low = 1,
326 .default_trigger = "nand-disk",
327 },
328#if !(defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE))
329 { /* "right" led, green, userled1, pwm1 */
330 .name = "d7",
331 .gpio = AT91_PIN_PD31,
332 .active_low = 1,
333 .default_trigger = "mmc0",
334 },
335#endif
336};
337
338
339/*
340 * PWM Leds
341 */
342static struct gpio_led ek_pwm_led[] = {
343#if defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE)
344 { /* "right" led, green, userled1, pwm1 */
345 .name = "d7",
346 .gpio = 1, /* is PWM channel number */
347 .active_low = 1,
348 .default_trigger = "none",
349 },
350#endif
351};
352
353
354
355static void __init ek_board_init(void)
356{
357 /* Serial */
358 at91_add_device_serial();
359 /* USB HS Host */
360 at91_add_device_usbh_ohci(&ek_usbh_hs_data);
361 /* USB HS Device */
362 at91_add_device_usba(&ek_usba_udc_data);
363 /* SPI */
364 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
365 /* Ethernet */
366 at91_add_device_eth(&ek_macb_data);
367 /* NAND */
368 ek_add_device_nand();
369 /* I2C */
370 at91_add_device_i2c(0, NULL, 0);
371 /* LCD Controller */
372 at91_add_device_lcdc(&ek_lcdc_data);
373 /* Push Buttons */
374 ek_add_device_buttons();
375 /* LEDs */
376 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
377 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
378}
379
380MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
381 /* Maintainer: Atmel */
382 .phys_io = AT91_BASE_SYS,
383 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
384 .boot_params = AT91_SDRAM_BASE + 0x100,
385 .timer = &at91sam926x_timer,
386 .map_io = ek_map_io,
387 .init_irq = ek_init_irq,
388 .init_machine = ek_board_init,
389MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index f6b5672cabd6..9d07679efce7 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -15,6 +15,8 @@
15#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
16#include <linux/fb.h> 16#include <linux/fb.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/input.h>
19#include <linux/gpio_keys.h>
18 20
19#include <video/atmel_lcdc.h> 21#include <video/atmel_lcdc.h>
20 22
@@ -208,6 +210,79 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
208#endif 210#endif
209 211
210 212
213/*
214 * LEDs
215 */
216static struct gpio_led ek_leds[] = {
217 { /* "bottom" led, green, userled1 to be defined */
218 .name = "ds1",
219 .gpio = AT91_PIN_PD15,
220 .active_low = 1,
221 .default_trigger = "none",
222 },
223 { /* "bottom" led, green, userled2 to be defined */
224 .name = "ds2",
225 .gpio = AT91_PIN_PD16,
226 .active_low = 1,
227 .default_trigger = "none",
228 },
229 { /* "power" led, yellow */
230 .name = "ds3",
231 .gpio = AT91_PIN_PD14,
232 .default_trigger = "heartbeat",
233 }
234};
235
236
237/*
238 * GPIO Buttons
239 */
240#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
241static struct gpio_keys_button ek_buttons[] = {
242 {
243 .gpio = AT91_PIN_PB0,
244 .code = BTN_2,
245 .desc = "Right Click",
246 .active_low = 1,
247 .wakeup = 1,
248 },
249 {
250 .gpio = AT91_PIN_PB1,
251 .code = BTN_1,
252 .desc = "Left Click",
253 .active_low = 1,
254 .wakeup = 1,
255 }
256};
257
258static struct gpio_keys_platform_data ek_button_data = {
259 .buttons = ek_buttons,
260 .nbuttons = ARRAY_SIZE(ek_buttons),
261};
262
263static struct platform_device ek_button_device = {
264 .name = "gpio-keys",
265 .id = -1,
266 .num_resources = 0,
267 .dev = {
268 .platform_data = &ek_button_data,
269 }
270};
271
272static void __init ek_add_device_buttons(void)
273{
274 at91_set_gpio_input(AT91_PIN_PB1, 1); /* btn1 */
275 at91_set_deglitch(AT91_PIN_PB1, 1);
276 at91_set_gpio_input(AT91_PIN_PB0, 1); /* btn2 */
277 at91_set_deglitch(AT91_PIN_PB0, 1);
278
279 platform_device_register(&ek_button_device);
280}
281#else
282static void __init ek_add_device_buttons(void) {}
283#endif
284
285
211static void __init ek_board_init(void) 286static void __init ek_board_init(void)
212{ 287{
213 /* Serial */ 288 /* Serial */
@@ -226,6 +301,10 @@ static void __init ek_board_init(void)
226 at91_add_device_lcdc(&ek_lcdc_data); 301 at91_add_device_lcdc(&ek_lcdc_data);
227 /* Touch Screen Controller */ 302 /* Touch Screen Controller */
228 at91_add_device_tsadcc(); 303 at91_add_device_tsadcc();
304 /* LEDs */
305 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
306 /* Push Buttons */
307 ek_add_device_buttons();
229} 308}
230 309
231MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") 310MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index bac578fe0d3d..c042dcf4725f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -47,20 +47,25 @@
47 * Chips have some kind of clocks : group them by functionality 47 * Chips have some kind of clocks : group them by functionality
48 */ 48 */
49#define cpu_has_utmi() ( cpu_is_at91cap9() \ 49#define cpu_has_utmi() ( cpu_is_at91cap9() \
50 || cpu_is_at91sam9rl()) 50 || cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9g45())
51 52
52#define cpu_has_800M_plla() (cpu_is_at91sam9g20()) 53#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
54 || cpu_is_at91sam9g45())
53 55
54#define cpu_has_pllb() (!cpu_is_at91sam9rl()) 56#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
55 57
56#define cpu_has_upll() (0) 58#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
59 || cpu_is_at91sam9g45()))
60
61#define cpu_has_upll() (cpu_is_at91sam9g45())
57 62
58/* USB host HS & FS */ 63/* USB host HS & FS */
59#define cpu_has_uhp() (!cpu_is_at91sam9rl()) 64#define cpu_has_uhp() (!cpu_is_at91sam9rl())
60 65
61/* USB device FS only */ 66/* USB device FS only */
62#define cpu_has_udpfs() (!cpu_is_at91sam9rl()) 67#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
63 68 || cpu_is_at91sam9g45()))
64 69
65static LIST_HEAD(clocks); 70static LIST_HEAD(clocks);
66static DEFINE_SPINLOCK(clk_lock); 71static DEFINE_SPINLOCK(clk_lock);
@@ -133,6 +138,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
133{ 138{
134 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); 139 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
135 140
141 if (cpu_is_at91sam9g45()) {
142 if (is_on)
143 uckr |= AT91_PMC_BIASEN;
144 else
145 uckr &= ~AT91_PMC_BIASEN;
146 }
147
136 if (is_on) { 148 if (is_on) {
137 is_on = AT91_PMC_LOCKU; 149 is_on = AT91_PMC_LOCKU;
138 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); 150 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
@@ -310,6 +322,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
310 unsigned long flags; 322 unsigned long flags;
311 unsigned prescale; 323 unsigned prescale;
312 unsigned long actual; 324 unsigned long actual;
325 unsigned long prev = ULONG_MAX;
313 326
314 if (!clk_is_programmable(clk)) 327 if (!clk_is_programmable(clk))
315 return -EINVAL; 328 return -EINVAL;
@@ -317,8 +330,16 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
317 330
318 actual = clk->parent->rate_hz; 331 actual = clk->parent->rate_hz;
319 for (prescale = 0; prescale < 7; prescale++) { 332 for (prescale = 0; prescale < 7; prescale++) {
320 if (actual && actual <= rate) 333 if (actual > rate)
334 prev = actual;
335
336 if (actual && actual <= rate) {
337 if ((prev - rate) < (rate - actual)) {
338 actual = prev;
339 prescale--;
340 }
321 break; 341 break;
342 }
322 actual >>= 1; 343 actual >>= 1;
323 } 344 }
324 345
@@ -373,6 +394,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
373 return -EBUSY; 394 return -EBUSY;
374 if (!clk_is_primary(parent) || !clk_is_programmable(clk)) 395 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
375 return -EINVAL; 396 return -EINVAL;
397
398 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
399 return -EINVAL;
400
376 spin_lock_irqsave(&clk_lock, flags); 401 spin_lock_irqsave(&clk_lock, flags);
377 402
378 clk->rate_hz = parent->rate_hz; 403 clk->rate_hz = parent->rate_hz;
@@ -601,7 +626,9 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
601 uhpck.pmc_mask = AT91RM9200_PMC_UHP; 626 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
602 udpck.pmc_mask = AT91RM9200_PMC_UDP; 627 udpck.pmc_mask = AT91RM9200_PMC_UDP;
603 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 628 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
604 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { 629 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
630 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
631 cpu_is_at91sam9g10()) {
605 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 632 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
606 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 633 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
607 } else if (cpu_is_at91cap9()) { 634 } else if (cpu_is_at91cap9()) {
@@ -637,6 +664,7 @@ int __init at91_clock_init(unsigned long main_clock)
637{ 664{
638 unsigned tmp, freq, mckr; 665 unsigned tmp, freq, mckr;
639 int i; 666 int i;
667 int pll_overclock = false;
640 668
641 /* 669 /*
642 * When the bootloader initialized the main oscillator correctly, 670 * When the bootloader initialized the main oscillator correctly,
@@ -654,12 +682,25 @@ int __init at91_clock_init(unsigned long main_clock)
654 682
655 /* report if PLLA is more than mildly overclocked */ 683 /* report if PLLA is more than mildly overclocked */
656 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); 684 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
657 if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) 685 if (cpu_has_300M_plla()) {
658 || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) 686 if (plla.rate_hz > 300000000)
687 pll_overclock = true;
688 } else if (cpu_has_800M_plla()) {
689 if (plla.rate_hz > 800000000)
690 pll_overclock = true;
691 } else {
692 if (plla.rate_hz > 209000000)
693 pll_overclock = true;
694 }
695 if (pll_overclock)
659 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); 696 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
660 697
698 if (cpu_is_at91sam9g45()) {
699 mckr = at91_sys_read(AT91_PMC_MCKR);
700 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
701 }
661 702
662 if (cpu_has_upll() && !cpu_has_pllb()) { 703 if (!cpu_has_pllb() && cpu_has_upll()) {
663 /* setup UTMI clock as the fourth primary clock 704 /* setup UTMI clock as the fourth primary clock
664 * (instead of pllb) */ 705 * (instead of pllb) */
665 utmi_clk.type |= CLK_TYPE_PRIMARY; 706 utmi_clk.type |= CLK_TYPE_PRIMARY;
@@ -701,6 +742,9 @@ int __init at91_clock_init(unsigned long main_clock)
701 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ 742 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
702 if (mckr & AT91_PMC_PDIV) 743 if (mckr & AT91_PMC_PDIV)
703 freq /= 2; /* processor clock division */ 744 freq /= 2; /* processor clock division */
745 } else if (cpu_is_at91sam9g45()) {
746 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
747 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
704 } else { 748 } else {
705 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 749 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
706 } 750 }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..88e413b38480 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock); 14extern void __init at91sam9261_initialize(unsigned long main_clock);
15extern void __init at91sam9263_initialize(unsigned long main_clock); 15extern void __init at91sam9263_initialize(unsigned long main_clock);
16extern void __init at91sam9rl_initialize(unsigned long main_clock); 16extern void __init at91sam9rl_initialize(unsigned long main_clock);
17extern void __init at91sam9g45_initialize(unsigned long main_clock);
17extern void __init at91x40_initialize(unsigned long main_clock); 18extern void __init at91x40_initialize(unsigned long main_clock);
18extern void __init at91cap9_initialize(unsigned long main_clock); 19extern void __init at91cap9_initialize(unsigned long main_clock);
19 20
@@ -23,6 +24,7 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
23extern void __init at91sam9261_init_interrupts(unsigned int priority[]); 24extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
24extern void __init at91sam9263_init_interrupts(unsigned int priority[]); 25extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
25extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); 26extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
27extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
26extern void __init at91x40_init_interrupts(unsigned int priority[]); 28extern void __init at91x40_init_interrupts(unsigned int priority[]);
27extern void __init at91cap9_init_interrupts(unsigned int priority[]); 29extern void __init at91cap9_init_interrupts(unsigned int priority[]);
28extern void __init at91_aic_init(unsigned int priority[]); 30extern void __init at91_aic_init(unsigned int priority[]);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index f2236f0e101f..ae4772e744ac 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -44,13 +44,11 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
44 unsigned offset, int val); 44 unsigned offset, int val);
45static int at91_gpiolib_direction_input(struct gpio_chip *chip, 45static int at91_gpiolib_direction_input(struct gpio_chip *chip,
46 unsigned offset); 46 unsigned offset);
47static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
48 47
49#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ 48#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
50 { \ 49 { \
51 .chip = { \ 50 .chip = { \
52 .label = name, \ 51 .label = name, \
53 .request = at91_gpiolib_request, \
54 .direction_input = at91_gpiolib_direction_input, \ 52 .direction_input = at91_gpiolib_direction_input, \
55 .direction_output = at91_gpiolib_direction_output, \ 53 .direction_output = at91_gpiolib_direction_output, \
56 .get = at91_gpiolib_get, \ 54 .get = at91_gpiolib_get, \
@@ -588,19 +586,6 @@ static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
588 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); 586 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
589} 587}
590 588
591static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
592{
593 unsigned pin = chip->base + offset;
594 void __iomem *pio = pin_to_controller(pin);
595 unsigned mask = pin_to_mask(pin);
596
597 /* Cannot request GPIOs that are in alternate function mode */
598 if (!(__raw_readl(pio + PIO_PSR) & mask))
599 return -EPERM;
600
601 return 0;
602}
603
604static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) 589static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
605{ 590{
606 int i; 591 int i;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 3a348ca20773..87de8be17484 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -95,6 +95,9 @@
95#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 95#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
96#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ 96#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
97 97
98#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
99#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
100
98#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ 101#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
99#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ 102#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
100 103
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
new file mode 100644
index 000000000000..a526869aee37
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -0,0 +1,155 @@
1/*
2 * Chip-specific header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_H
16#define AT91SAM9G45_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Controller Interrupt */
23#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
24#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
25#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
26#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
27#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
28#define AT91SAM9G45_ID_US0 7 /* USART 0 */
29#define AT91SAM9G45_ID_US1 8 /* USART 1 */
30#define AT91SAM9G45_ID_US2 9 /* USART 2 */
31#define AT91SAM9G45_ID_US3 10 /* USART 3 */
32#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
33#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
34#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
35#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
36#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
37#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
38#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
39#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
40#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
41#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
42#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
43#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
44#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
45#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
46#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
47#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
48#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
49#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
50#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
51#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
52#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91SAM9G45_BASE_UDPHS 0xfff78000
58#define AT91SAM9G45_BASE_TCB0 0xfff7c000
59#define AT91SAM9G45_BASE_TC0 0xfff7c000
60#define AT91SAM9G45_BASE_TC1 0xfff7c040
61#define AT91SAM9G45_BASE_TC2 0xfff7c080
62#define AT91SAM9G45_BASE_MCI0 0xfff80000
63#define AT91SAM9G45_BASE_TWI0 0xfff84000
64#define AT91SAM9G45_BASE_TWI1 0xfff88000
65#define AT91SAM9G45_BASE_US0 0xfff8c000
66#define AT91SAM9G45_BASE_US1 0xfff90000
67#define AT91SAM9G45_BASE_US2 0xfff94000
68#define AT91SAM9G45_BASE_US3 0xfff98000
69#define AT91SAM9G45_BASE_SSC0 0xfff9c000
70#define AT91SAM9G45_BASE_SSC1 0xfffa0000
71#define AT91SAM9G45_BASE_SPI0 0xfffa4000
72#define AT91SAM9G45_BASE_SPI1 0xfffa8000
73#define AT91SAM9G45_BASE_AC97C 0xfffac000
74#define AT91SAM9G45_BASE_TSC 0xfffb0000
75#define AT91SAM9G45_BASE_ISI 0xfffb4000
76#define AT91SAM9G45_BASE_PWMC 0xfffb8000
77#define AT91SAM9G45_BASE_EMAC 0xfffbc000
78#define AT91SAM9G45_BASE_AES 0xfffc0000
79#define AT91SAM9G45_BASE_TDES 0xfffc4000
80#define AT91SAM9G45_BASE_SHA 0xfffc8000
81#define AT91SAM9G45_BASE_TRNG 0xfffcc000
82#define AT91SAM9G45_BASE_MCI1 0xfffd0000
83#define AT91SAM9G45_BASE_TCB1 0xfffd4000
84#define AT91SAM9G45_BASE_TC3 0xfffd4000
85#define AT91SAM9G45_BASE_TC4 0xfffd4040
86#define AT91SAM9G45_BASE_TC5 0xfffd4080
87#define AT91_BASE_SYS 0xffffe200
88
89/*
90 * System Peripherals (offset from AT91_BASE_SYS)
91 */
92#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
93#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
94#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
95#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
96#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
97#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
98#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
99#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
100#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
101#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
102#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
103#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
104#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
105#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
106#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
107#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
108#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
109#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
110#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
111#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
112#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
113
114#define AT91_USART0 AT91SAM9G45_BASE_US0
115#define AT91_USART1 AT91SAM9G45_BASE_US1
116#define AT91_USART2 AT91SAM9G45_BASE_US2
117#define AT91_USART3 AT91SAM9G45_BASE_US3
118
119/*
120 * Internal Memory.
121 */
122#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
123#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
124
125#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
126#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
127
128#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
129#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
130#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
131#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
132#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
133
134#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
135
136#define CONSISTENT_DMA_SIZE SZ_4M
137
138/*
139 * DMA peripheral identifiers
140 * for hardware handshaking interface
141 */
142#define AT_DMA_ID_MCI0 0
143#define AT_DMA_ID_SPI0_TX 1
144#define AT_DMA_ID_SPI0_RX 2
145#define AT_DMA_ID_SPI1_TX 3
146#define AT_DMA_ID_SPI1_RX 4
147#define AT_DMA_ID_SSC0_TX 5
148#define AT_DMA_ID_SSC0_RX 6
149#define AT_DMA_ID_SSC1_TX 7
150#define AT_DMA_ID_SSC1_RX 8
151#define AT_DMA_ID_AC97_TX 9
152#define AT_DMA_ID_AC97_RX 10
153#define AT_DMA_ID_MCI1 13
154
155#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
new file mode 100644
index 000000000000..c972d60e0aeb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -0,0 +1,153 @@
1/*
2 * Matrix-centric header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
33#define AT91_MATRIX_ULBT_FOUR (2 << 0)
34#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
35#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
36#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0)
39
40#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
51#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54
55#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
74#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
75#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
76#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
77#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
78#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
79#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
80#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83
84#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2)
88#define AT91_MATRIX_RCB3 (1 << 3)
89#define AT91_MATRIX_RCB4 (1 << 4)
90#define AT91_MATRIX_RCB5 (1 << 5)
91#define AT91_MATRIX_RCB6 (1 << 6)
92#define AT91_MATRIX_RCB7 (1 << 7)
93#define AT91_MATRIX_RCB8 (1 << 8)
94#define AT91_MATRIX_RCB9 (1 << 9)
95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11)
97
98#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_32 (6 << 4)
105#define AT91_MATRIX_DTCM_64 (7 << 4)
106#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109
110#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0)
114
115#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
119#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
120#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
121#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
122#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
123#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
124#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
125#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
126#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
127#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
128#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
129#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
130#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
131#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
132#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
133#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
134#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
135#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
136#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
137#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140
141#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146
147#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0)
151#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
152
153#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index e6afff849b85..13f27a4b882d 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -37,6 +37,7 @@
37#include <linux/leds.h> 37#include <linux/leds.h>
38#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
39#include <linux/usb/atmel_usba_udc.h> 39#include <linux/usb/atmel_usba_udc.h>
40#include <sound/atmel-ac97c.h>
40 41
41 /* USB Device */ 42 /* USB Device */
42struct at91_udc_data { 43struct at91_udc_data {
@@ -80,7 +81,8 @@ struct at91_eth_data {
80}; 81};
81extern void __init at91_add_device_eth(struct at91_eth_data *data); 82extern void __init at91_add_device_eth(struct at91_eth_data *data);
82 83
83#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) 84#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
85 || defined(CONFIG_ARCH_AT91SAM9G45)
84#define eth_platform_data at91_eth_data 86#define eth_platform_data at91_eth_data
85#endif 87#endif
86 88
@@ -90,6 +92,7 @@ struct at91_usbh_data {
90 u8 vbus_pin[2]; /* port power-control pin */ 92 u8 vbus_pin[2]; /* port power-control pin */
91}; 93};
92extern void __init at91_add_device_usbh(struct at91_usbh_data *data); 94extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
95extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
93 96
94 /* NAND / SmartMedia */ 97 /* NAND / SmartMedia */
95struct atmel_nand_data { 98struct atmel_nand_data {
@@ -105,7 +108,11 @@ struct atmel_nand_data {
105extern void __init at91_add_device_nand(struct atmel_nand_data *data); 108extern void __init at91_add_device_nand(struct atmel_nand_data *data);
106 109
107 /* I2C*/ 110 /* I2C*/
111#if defined(CONFIG_ARCH_AT91SAM9G45)
112extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
113#else
108extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); 114extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
115#endif
109 116
110 /* SPI */ 117 /* SPI */
111extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); 118extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
@@ -168,10 +175,7 @@ struct atmel_lcdfb_info;
168extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); 175extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
169 176
170 /* AC97 */ 177 /* AC97 */
171struct atmel_ac97_data { 178extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
172 u8 reset_pin; /* reset */
173};
174extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
175 179
176 /* ISI */ 180 /* ISI */
177extern void __init at91_add_device_isi(void); 181extern void __init at91_add_device_isi(void);
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c554c3e4d553..34a9502c48bc 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -21,8 +21,10 @@
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9G10 0x819903a0
24#define ARCH_ID_AT91SAM9G20 0x019905a0 25#define ARCH_ID_AT91SAM9G20 0x019905a0
25#define ARCH_ID_AT91SAM9RL64 0x019b03a0 26#define ARCH_ID_AT91SAM9RL64 0x019b03a0
27#define ARCH_ID_AT91SAM9G45 0x819b05a0
26#define ARCH_ID_AT91CAP9 0x039A03A0 28#define ARCH_ID_AT91CAP9 0x039A03A0
27 29
28#define ARCH_ID_AT91SAM9XE128 0x329973a0 30#define ARCH_ID_AT91SAM9XE128 0x329973a0
@@ -39,6 +41,15 @@ static inline unsigned long at91_cpu_identify(void)
39 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 41 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
40} 42}
41 43
44#define ARCH_EXID_AT91SAM9M11 0x00000001
45#define ARCH_EXID_AT91SAM9M10 0x00000002
46#define ARCH_EXID_AT91SAM9G45 0x00000004
47
48static inline unsigned long at91_exid_identify(void)
49{
50 return at91_sys_read(AT91_DBGU_EXID);
51}
52
42 53
43#define ARCH_FAMILY_AT91X92 0x09200000 54#define ARCH_FAMILY_AT91X92 0x09200000
44#define ARCH_FAMILY_AT91SAM9 0x01900000 55#define ARCH_FAMILY_AT91SAM9 0x01900000
@@ -87,6 +98,12 @@ static inline unsigned long at91cap9_rev_identify(void)
87#define cpu_is_at91sam9261() (0) 98#define cpu_is_at91sam9261() (0)
88#endif 99#endif
89 100
101#ifdef CONFIG_ARCH_AT91SAM9G10
102#define cpu_is_at91sam9g10() (at91_cpu_identify() == ARCH_ID_AT91SAM9G10)
103#else
104#define cpu_is_at91sam9g10() (0)
105#endif
106
90#ifdef CONFIG_ARCH_AT91SAM9263 107#ifdef CONFIG_ARCH_AT91SAM9263
91#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) 108#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
92#else 109#else
@@ -99,6 +116,12 @@ static inline unsigned long at91cap9_rev_identify(void)
99#define cpu_is_at91sam9rl() (0) 116#define cpu_is_at91sam9rl() (0)
100#endif 117#endif
101 118
119#ifdef CONFIG_ARCH_AT91SAM9G45
120#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
121#else
122#define cpu_is_at91sam9g45() (0)
123#endif
124
102#ifdef CONFIG_ARCH_AT91CAP9 125#ifdef CONFIG_ARCH_AT91CAP9
103#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) 126#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
104#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) 127#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index da0b681c652c..a0df8b022df2 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -20,12 +20,14 @@
20#include <mach/at91rm9200.h> 20#include <mach/at91rm9200.h>
21#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) 21#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
22#include <mach/at91sam9260.h> 22#include <mach/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261) 23#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
24#include <mach/at91sam9261.h> 24#include <mach/at91sam9261.h>
25#elif defined(CONFIG_ARCH_AT91SAM9263) 25#elif defined(CONFIG_ARCH_AT91SAM9263)
26#include <mach/at91sam9263.h> 26#include <mach/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL) 27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <mach/at91sam9rl.h> 28#include <mach/at91sam9rl.h>
29#elif defined(CONFIG_ARCH_AT91SAM9G45)
30#include <mach/at91sam9g45.h>
29#elif defined(CONFIG_ARCH_AT91CAP9) 31#elif defined(CONFIG_ARCH_AT91CAP9)
30#include <mach/at91cap9.h> 32#include <mach/at91cap9.h>
31#elif defined(CONFIG_ARCH_AT91X40) 33#elif defined(CONFIG_ARCH_AT91X40)
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index d84c9948becf..31ac2d97f14c 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -42,6 +42,11 @@
42#define AT91SAM9_MASTER_CLOCK 99300000 42#define AT91SAM9_MASTER_CLOCK 99300000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 44
45#elif defined(CONFIG_ARCH_AT91SAM9G10)
46
47#define AT91SAM9_MASTER_CLOCK 133000000
48#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
49
45#elif defined(CONFIG_ARCH_AT91SAM9263) 50#elif defined(CONFIG_ARCH_AT91SAM9263)
46 51
47#if defined(CONFIG_MACH_USB_A9263) 52#if defined(CONFIG_MACH_USB_A9263)
@@ -62,6 +67,11 @@
62#define AT91SAM9_MASTER_CLOCK 132096000 67#define AT91SAM9_MASTER_CLOCK 132096000
63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 68#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
64 69
70#elif defined(CONFIG_ARCH_AT91SAM9G45)
71
72#define AT91SAM9_MASTER_CLOCK 133333333
73#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
74
65#elif defined(CONFIG_ARCH_AT91CAP9) 75#elif defined(CONFIG_ARCH_AT91CAP9)
66 76
67#define AT91CAP9_MASTER_CLOCK 100000000 77#define AT91CAP9_MASTER_CLOCK 100000000
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e26c4fe61fae..4028724d490d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,8 @@ static int at91_pm_verify_clocks(void)
201 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 201 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
202 return 0; 202 return 0;
203 } 203 }
204 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { 204 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
205 || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
205 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { 206 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
206 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 207 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
207 return 0; 208 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 07:27:58 -0500