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-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h103
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h129
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h99
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h117
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h143
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12.h65
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h105
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h71
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h11
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h86
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d4.h33
11 files changed, 0 insertions, 962 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
deleted file mode 100644
index e67317c67761..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Common definitions.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_H
17#define AT91RM9200_H
18
19/*
20 * Peripheral identifiers/interrupts.
21 */
22#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
23#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
24#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
25#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
26#define AT91RM9200_ID_US0 6 /* USART 0 */
27#define AT91RM9200_ID_US1 7 /* USART 1 */
28#define AT91RM9200_ID_US2 8 /* USART 2 */
29#define AT91RM9200_ID_US3 9 /* USART 3 */
30#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
31#define AT91RM9200_ID_UDP 11 /* USB Device Port */
32#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
33#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
34#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
37#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
38#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
39#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
40#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
41#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
42#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
43#define AT91RM9200_ID_UHP 23 /* USB Host port */
44#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
45#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
46#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
47#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
48#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
49#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
50#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
51#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
52
53
54/*
55 * Peripheral physical base addresses.
56 */
57#define AT91RM9200_BASE_TCB0 0xfffa0000
58#define AT91RM9200_BASE_TC0 0xfffa0000
59#define AT91RM9200_BASE_TC1 0xfffa0040
60#define AT91RM9200_BASE_TC2 0xfffa0080
61#define AT91RM9200_BASE_TCB1 0xfffa4000
62#define AT91RM9200_BASE_TC3 0xfffa4000
63#define AT91RM9200_BASE_TC4 0xfffa4040
64#define AT91RM9200_BASE_TC5 0xfffa4080
65#define AT91RM9200_BASE_UDP 0xfffb0000
66#define AT91RM9200_BASE_MCI 0xfffb4000
67#define AT91RM9200_BASE_TWI 0xfffb8000
68#define AT91RM9200_BASE_EMAC 0xfffbc000
69#define AT91RM9200_BASE_US0 0xfffc0000
70#define AT91RM9200_BASE_US1 0xfffc4000
71#define AT91RM9200_BASE_US2 0xfffc8000
72#define AT91RM9200_BASE_US3 0xfffcc000
73#define AT91RM9200_BASE_SSC0 0xfffd0000
74#define AT91RM9200_BASE_SSC1 0xfffd4000
75#define AT91RM9200_BASE_SSC2 0xfffd8000
76#define AT91RM9200_BASE_SPI 0xfffe0000
77
78
79/*
80 * System Peripherals
81 */
82#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
83#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
84#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
85#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
86#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
87#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
88#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
89#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
90
91/*
92 * Internal Memory.
93 */
94#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
95#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
96
97#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
98#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
99
100#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
101
102
103#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
deleted file mode 100644
index 416c7b6c56d3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9260.h
3 *
4 * (C) 2006 Andrew Victor
5 *
6 * Common definitions.
7 * Based on AT91SAM9260 datasheet revision A (Preliminary).
8 *
9 * Includes also definitions for AT91SAM9XE and AT91SAM9G families
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91SAM9260_H
18#define AT91SAM9260_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
26#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
27#define AT91SAM9260_ID_US0 6 /* USART 0 */
28#define AT91SAM9260_ID_US1 7 /* USART 1 */
29#define AT91SAM9260_ID_US2 8 /* USART 2 */
30#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
31#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
32#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
33#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
34#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
35#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
36#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
37#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
38#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
39#define AT91SAM9260_ID_UHP 20 /* USB Host port */
40#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
41#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
42#define AT91SAM9260_ID_US3 23 /* USART 3 */
43#define AT91SAM9260_ID_US4 24 /* USART 4 */
44#define AT91SAM9260_ID_US5 25 /* USART 5 */
45#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
46#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
47#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
48#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
49#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
50#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
51
52
53/*
54 * User Peripheral physical base addresses.
55 */
56#define AT91SAM9260_BASE_TCB0 0xfffa0000
57#define AT91SAM9260_BASE_TC0 0xfffa0000
58#define AT91SAM9260_BASE_TC1 0xfffa0040
59#define AT91SAM9260_BASE_TC2 0xfffa0080
60#define AT91SAM9260_BASE_UDP 0xfffa4000
61#define AT91SAM9260_BASE_MCI 0xfffa8000
62#define AT91SAM9260_BASE_TWI 0xfffac000
63#define AT91SAM9260_BASE_US0 0xfffb0000
64#define AT91SAM9260_BASE_US1 0xfffb4000
65#define AT91SAM9260_BASE_US2 0xfffb8000
66#define AT91SAM9260_BASE_SSC 0xfffbc000
67#define AT91SAM9260_BASE_ISI 0xfffc0000
68#define AT91SAM9260_BASE_EMAC 0xfffc4000
69#define AT91SAM9260_BASE_SPI0 0xfffc8000
70#define AT91SAM9260_BASE_SPI1 0xfffcc000
71#define AT91SAM9260_BASE_US3 0xfffd0000
72#define AT91SAM9260_BASE_US4 0xfffd4000
73#define AT91SAM9260_BASE_US5 0xfffd8000
74#define AT91SAM9260_BASE_TCB1 0xfffdc000
75#define AT91SAM9260_BASE_TC3 0xfffdc000
76#define AT91SAM9260_BASE_TC4 0xfffdc040
77#define AT91SAM9260_BASE_TC5 0xfffdc080
78#define AT91SAM9260_BASE_ADC 0xfffe0000
79
80/*
81 * System Peripherals
82 */
83#define AT91SAM9260_BASE_ECC 0xffffe800
84#define AT91SAM9260_BASE_SDRAMC 0xffffea00
85#define AT91SAM9260_BASE_SMC 0xffffec00
86#define AT91SAM9260_BASE_MATRIX 0xffffee00
87#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
88#define AT91SAM9260_BASE_PIOA 0xfffff400
89#define AT91SAM9260_BASE_PIOB 0xfffff600
90#define AT91SAM9260_BASE_PIOC 0xfffff800
91#define AT91SAM9260_BASE_RSTC 0xfffffd00
92#define AT91SAM9260_BASE_SHDWC 0xfffffd10
93#define AT91SAM9260_BASE_RTT 0xfffffd20
94#define AT91SAM9260_BASE_PIT 0xfffffd30
95#define AT91SAM9260_BASE_WDT 0xfffffd40
96#define AT91SAM9260_BASE_GPBR 0xfffffd50
97
98
99/*
100 * Internal Memory.
101 */
102#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
103#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
104
105#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
106#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
107#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
108#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
109#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
110#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
111
112#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
113
114#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
115#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
116
117#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
118#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
119
120#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
121#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
122#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
123#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
124#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
125#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
126
127#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
128
129#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
deleted file mode 100644
index a041406d06ee..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9261.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Common definitions.
7 * Based on AT91SAM9261 datasheet revision E. (Preliminary)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9261_H
16#define AT91SAM9261_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
22#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
23#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
24#define AT91SAM9261_ID_US0 6 /* USART 0 */
25#define AT91SAM9261_ID_US1 7 /* USART 1 */
26#define AT91SAM9261_ID_US2 8 /* USART 2 */
27#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
28#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
29#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
30#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
31#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
32#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
33#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
34#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
35#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
36#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
37#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
38#define AT91SAM9261_ID_UHP 20 /* USB Host port */
39#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
40#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
41#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
42#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
43
44
45/*
46 * User Peripheral physical base addresses.
47 */
48#define AT91SAM9261_BASE_TCB0 0xfffa0000
49#define AT91SAM9261_BASE_TC0 0xfffa0000
50#define AT91SAM9261_BASE_TC1 0xfffa0040
51#define AT91SAM9261_BASE_TC2 0xfffa0080
52#define AT91SAM9261_BASE_UDP 0xfffa4000
53#define AT91SAM9261_BASE_MCI 0xfffa8000
54#define AT91SAM9261_BASE_TWI 0xfffac000
55#define AT91SAM9261_BASE_US0 0xfffb0000
56#define AT91SAM9261_BASE_US1 0xfffb4000
57#define AT91SAM9261_BASE_US2 0xfffb8000
58#define AT91SAM9261_BASE_SSC0 0xfffbc000
59#define AT91SAM9261_BASE_SSC1 0xfffc0000
60#define AT91SAM9261_BASE_SSC2 0xfffc4000
61#define AT91SAM9261_BASE_SPI0 0xfffc8000
62#define AT91SAM9261_BASE_SPI1 0xfffcc000
63
64
65/*
66 * System Peripherals
67 */
68#define AT91SAM9261_BASE_SMC 0xffffec00
69#define AT91SAM9261_BASE_MATRIX 0xffffee00
70#define AT91SAM9261_BASE_SDRAMC 0xffffea00
71#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
72#define AT91SAM9261_BASE_PIOA 0xfffff400
73#define AT91SAM9261_BASE_PIOB 0xfffff600
74#define AT91SAM9261_BASE_PIOC 0xfffff800
75#define AT91SAM9261_BASE_RSTC 0xfffffd00
76#define AT91SAM9261_BASE_SHDWC 0xfffffd10
77#define AT91SAM9261_BASE_RTT 0xfffffd20
78#define AT91SAM9261_BASE_PIT 0xfffffd30
79#define AT91SAM9261_BASE_WDT 0xfffffd40
80#define AT91SAM9261_BASE_GPBR 0xfffffd50
81
82
83/*
84 * Internal Memory.
85 */
86#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
87#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
88
89#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
90#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
91
92#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
93#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
94
95#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
96#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
97
98
99#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
deleted file mode 100644
index d201029d60b3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9263.h
3 *
4 * (C) 2007 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_H
16#define AT91SAM9263_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
22#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
23#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
24#define AT91SAM9263_ID_US0 7 /* USART 0 */
25#define AT91SAM9263_ID_US1 8 /* USART 1 */
26#define AT91SAM9263_ID_US2 9 /* USART 2 */
27#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
28#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
29#define AT91SAM9263_ID_CAN 12 /* CAN */
30#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
31#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
32#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
33#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
34#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
35#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
36#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
37#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
38#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
39#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
40#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
41#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
42#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
43#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
44#define AT91SAM9263_ID_UHP 29 /* USB Host port */
45#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
46#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
47
48
49/*
50 * User Peripheral physical base addresses.
51 */
52#define AT91SAM9263_BASE_UDP 0xfff78000
53#define AT91SAM9263_BASE_TCB0 0xfff7c000
54#define AT91SAM9263_BASE_TC0 0xfff7c000
55#define AT91SAM9263_BASE_TC1 0xfff7c040
56#define AT91SAM9263_BASE_TC2 0xfff7c080
57#define AT91SAM9263_BASE_MCI0 0xfff80000
58#define AT91SAM9263_BASE_MCI1 0xfff84000
59#define AT91SAM9263_BASE_TWI 0xfff88000
60#define AT91SAM9263_BASE_US0 0xfff8c000
61#define AT91SAM9263_BASE_US1 0xfff90000
62#define AT91SAM9263_BASE_US2 0xfff94000
63#define AT91SAM9263_BASE_SSC0 0xfff98000
64#define AT91SAM9263_BASE_SSC1 0xfff9c000
65#define AT91SAM9263_BASE_AC97C 0xfffa0000
66#define AT91SAM9263_BASE_SPI0 0xfffa4000
67#define AT91SAM9263_BASE_SPI1 0xfffa8000
68#define AT91SAM9263_BASE_CAN 0xfffac000
69#define AT91SAM9263_BASE_PWMC 0xfffb8000
70#define AT91SAM9263_BASE_EMAC 0xfffbc000
71#define AT91SAM9263_BASE_ISI 0xfffc4000
72#define AT91SAM9263_BASE_2DGE 0xfffc8000
73
74/*
75 * System Peripherals
76 */
77#define AT91SAM9263_BASE_ECC0 0xffffe000
78#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
79#define AT91SAM9263_BASE_SMC0 0xffffe400
80#define AT91SAM9263_BASE_ECC1 0xffffe600
81#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
82#define AT91SAM9263_BASE_SMC1 0xffffea00
83#define AT91SAM9263_BASE_MATRIX 0xffffec00
84#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
85#define AT91SAM9263_BASE_PIOA 0xfffff200
86#define AT91SAM9263_BASE_PIOB 0xfffff400
87#define AT91SAM9263_BASE_PIOC 0xfffff600
88#define AT91SAM9263_BASE_PIOD 0xfffff800
89#define AT91SAM9263_BASE_PIOE 0xfffffa00
90#define AT91SAM9263_BASE_RSTC 0xfffffd00
91#define AT91SAM9263_BASE_SHDWC 0xfffffd10
92#define AT91SAM9263_BASE_RTT0 0xfffffd20
93#define AT91SAM9263_BASE_PIT 0xfffffd30
94#define AT91SAM9263_BASE_WDT 0xfffffd40
95#define AT91SAM9263_BASE_RTT1 0xfffffd50
96#define AT91SAM9263_BASE_GPBR 0xfffffd60
97
98#define AT91_SMC AT91_SMC0
99
100/*
101 * Internal Memory.
102 */
103#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
104#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
105
106#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
107#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
108
109#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
110#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
111
112#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
113#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
114#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
115
116
117#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
deleted file mode 100644
index 8eba1021f533..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Chip-specific header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_H
16#define AT91SAM9G45_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
22#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
23#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
24#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
25#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
26#define AT91SAM9G45_ID_US0 7 /* USART 0 */
27#define AT91SAM9G45_ID_US1 8 /* USART 1 */
28#define AT91SAM9G45_ID_US2 9 /* USART 2 */
29#define AT91SAM9G45_ID_US3 10 /* USART 3 */
30#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
31#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
32#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
33#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
34#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
35#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
36#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
37#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
39#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
40#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
41#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
42#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
43#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
44#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
45#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
46#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
47#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
48#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
49#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
50#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
51
52/*
53 * User Peripheral physical base addresses.
54 */
55#define AT91SAM9G45_BASE_UDPHS 0xfff78000
56#define AT91SAM9G45_BASE_TCB0 0xfff7c000
57#define AT91SAM9G45_BASE_TC0 0xfff7c000
58#define AT91SAM9G45_BASE_TC1 0xfff7c040
59#define AT91SAM9G45_BASE_TC2 0xfff7c080
60#define AT91SAM9G45_BASE_MCI0 0xfff80000
61#define AT91SAM9G45_BASE_TWI0 0xfff84000
62#define AT91SAM9G45_BASE_TWI1 0xfff88000
63#define AT91SAM9G45_BASE_US0 0xfff8c000
64#define AT91SAM9G45_BASE_US1 0xfff90000
65#define AT91SAM9G45_BASE_US2 0xfff94000
66#define AT91SAM9G45_BASE_US3 0xfff98000
67#define AT91SAM9G45_BASE_SSC0 0xfff9c000
68#define AT91SAM9G45_BASE_SSC1 0xfffa0000
69#define AT91SAM9G45_BASE_SPI0 0xfffa4000
70#define AT91SAM9G45_BASE_SPI1 0xfffa8000
71#define AT91SAM9G45_BASE_AC97C 0xfffac000
72#define AT91SAM9G45_BASE_TSC 0xfffb0000
73#define AT91SAM9G45_BASE_ISI 0xfffb4000
74#define AT91SAM9G45_BASE_PWMC 0xfffb8000
75#define AT91SAM9G45_BASE_EMAC 0xfffbc000
76#define AT91SAM9G45_BASE_AES 0xfffc0000
77#define AT91SAM9G45_BASE_TDES 0xfffc4000
78#define AT91SAM9G45_BASE_SHA 0xfffc8000
79#define AT91SAM9G45_BASE_TRNG 0xfffcc000
80#define AT91SAM9G45_BASE_MCI1 0xfffd0000
81#define AT91SAM9G45_BASE_TCB1 0xfffd4000
82#define AT91SAM9G45_BASE_TC3 0xfffd4000
83#define AT91SAM9G45_BASE_TC4 0xfffd4040
84#define AT91SAM9G45_BASE_TC5 0xfffd4080
85
86/*
87 * System Peripherals
88 */
89#define AT91SAM9G45_BASE_ECC 0xffffe200
90#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
91#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
92#define AT91SAM9G45_BASE_DMA 0xffffec00
93#define AT91SAM9G45_BASE_SMC 0xffffe800
94#define AT91SAM9G45_BASE_MATRIX 0xffffea00
95#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
96#define AT91SAM9G45_BASE_PIOA 0xfffff200
97#define AT91SAM9G45_BASE_PIOB 0xfffff400
98#define AT91SAM9G45_BASE_PIOC 0xfffff600
99#define AT91SAM9G45_BASE_PIOD 0xfffff800
100#define AT91SAM9G45_BASE_PIOE 0xfffffa00
101#define AT91SAM9G45_BASE_RSTC 0xfffffd00
102#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
103#define AT91SAM9G45_BASE_RTT 0xfffffd20
104#define AT91SAM9G45_BASE_PIT 0xfffffd30
105#define AT91SAM9G45_BASE_WDT 0xfffffd40
106#define AT91SAM9G45_BASE_RTC 0xfffffdb0
107#define AT91SAM9G45_BASE_GPBR 0xfffffd60
108
109/*
110 * Internal Memory.
111 */
112#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
113#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
114
115#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
116#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
117
118#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
119#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
120#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
121#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
122#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
123
124/*
125 * DMA peripheral identifiers
126 * for hardware handshaking interface
127 */
128#define AT_DMA_ID_MCI0 0
129#define AT_DMA_ID_SPI0_TX 1
130#define AT_DMA_ID_SPI0_RX 2
131#define AT_DMA_ID_SPI1_TX 3
132#define AT_DMA_ID_SPI1_RX 4
133#define AT_DMA_ID_SSC0_TX 5
134#define AT_DMA_ID_SSC0_RX 6
135#define AT_DMA_ID_SSC1_TX 7
136#define AT_DMA_ID_SSC1_RX 8
137#define AT_DMA_ID_AC97_TX 9
138#define AT_DMA_ID_AC97_RX 10
139#define AT_DMA_ID_AES_TX 11
140#define AT_DMA_ID_AES_RX 12
141#define AT_DMA_ID_MCI1 13
142
143#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
deleted file mode 100644
index 0151bcf6163c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * SoC specific header file for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation
5 *
6 * Common definitions, based on AT91SAM9N12 SoC datasheet
7 *
8 * Licensed under GPLv2 or later
9 */
10
11#ifndef _AT91SAM9N12_H_
12#define _AT91SAM9N12_H_
13
14/*
15 * Peripheral identifiers/interrupts.
16 */
17#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
18#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
19#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
20#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
21#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
22#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
23#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
24#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
25#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
26#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
27#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
28#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
29#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
30#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
31#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
32#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
33#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
34#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
35#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
36#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
37#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
38#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
39#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
40#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
41#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
42
43/*
44 * User Peripheral physical base addresses.
45 */
46#define AT91SAM9N12_BASE_USART0 0xf801c000
47#define AT91SAM9N12_BASE_USART1 0xf8020000
48#define AT91SAM9N12_BASE_USART2 0xf8024000
49#define AT91SAM9N12_BASE_USART3 0xf8028000
50
51/*
52 * System Peripherals
53 */
54#define AT91SAM9N12_BASE_RTC 0xfffffeb0
55
56/*
57 * Internal Memory.
58 */
59#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
60#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
61
62#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
63#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
64
65#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
deleted file mode 100644
index a15db56d33fa..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9260.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Common definitions.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_H
15#define AT91SAM9RL_H
16
17/*
18 * Peripheral identifiers/interrupts.
19 */
20#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
21#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
22#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
23#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
24#define AT91SAM9RL_ID_US0 6 /* USART 0 */
25#define AT91SAM9RL_ID_US1 7 /* USART 1 */
26#define AT91SAM9RL_ID_US2 8 /* USART 2 */
27#define AT91SAM9RL_ID_US3 9 /* USART 3 */
28#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
29#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
30#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
31#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
32#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
33#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
34#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
35#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
36#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
37#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
38#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
39#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
40#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
41#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
42#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
43#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
44
45
46/*
47 * User Peripheral physical base addresses.
48 */
49#define AT91SAM9RL_BASE_TCB0 0xfffa0000
50#define AT91SAM9RL_BASE_TC0 0xfffa0000
51#define AT91SAM9RL_BASE_TC1 0xfffa0040
52#define AT91SAM9RL_BASE_TC2 0xfffa0080
53#define AT91SAM9RL_BASE_MCI 0xfffa4000
54#define AT91SAM9RL_BASE_TWI0 0xfffa8000
55#define AT91SAM9RL_BASE_TWI1 0xfffac000
56#define AT91SAM9RL_BASE_US0 0xfffb0000
57#define AT91SAM9RL_BASE_US1 0xfffb4000
58#define AT91SAM9RL_BASE_US2 0xfffb8000
59#define AT91SAM9RL_BASE_US3 0xfffbc000
60#define AT91SAM9RL_BASE_SSC0 0xfffc0000
61#define AT91SAM9RL_BASE_SSC1 0xfffc4000
62#define AT91SAM9RL_BASE_PWMC 0xfffc8000
63#define AT91SAM9RL_BASE_SPI 0xfffcc000
64#define AT91SAM9RL_BASE_TSC 0xfffd0000
65#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
66#define AT91SAM9RL_BASE_AC97C 0xfffd8000
67
68
69/*
70 * System Peripherals (offset from AT91_BASE_SYS)
71 */
72#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
73
74#define AT91SAM9RL_BASE_DMA 0xffffe600
75#define AT91SAM9RL_BASE_ECC 0xffffe800
76#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
77#define AT91SAM9RL_BASE_SMC 0xffffec00
78#define AT91SAM9RL_BASE_MATRIX 0xffffee00
79#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
80#define AT91SAM9RL_BASE_PIOA 0xfffff400
81#define AT91SAM9RL_BASE_PIOB 0xfffff600
82#define AT91SAM9RL_BASE_PIOC 0xfffff800
83#define AT91SAM9RL_BASE_PIOD 0xfffffa00
84#define AT91SAM9RL_BASE_RSTC 0xfffffd00
85#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
86#define AT91SAM9RL_BASE_RTT 0xfffffd20
87#define AT91SAM9RL_BASE_PIT 0xfffffd30
88#define AT91SAM9RL_BASE_WDT 0xfffffd40
89#define AT91SAM9RL_BASE_GPBR 0xfffffd60
90#define AT91SAM9RL_BASE_RTC 0xfffffe00
91
92
93/*
94 * Internal Memory.
95 */
96#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
97#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
98
99#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
100#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
101
102#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
103#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
104
105#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
deleted file mode 100644
index 2fc76c49e97c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Chip-specific header file for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2009-2012 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9x5 datasheet.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef AT91SAM9X5_H
13#define AT91SAM9X5_H
14
15/*
16 * Peripheral identifiers/interrupts.
17 */
18#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
19#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
20#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
21#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
22#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
23#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
24#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
25#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
26#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
27#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
28#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
29#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
30#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
31#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
32#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
33#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
34#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
35#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
36#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
37#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
38#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
39#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
40#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
41#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
42#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
43#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
44#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
45#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
46#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
47#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
48#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
49
50/*
51 * User Peripheral physical base addresses.
52 */
53#define AT91SAM9X5_BASE_USART0 0xf801c000
54#define AT91SAM9X5_BASE_USART1 0xf8020000
55#define AT91SAM9X5_BASE_USART2 0xf8024000
56
57/*
58 * System Peripherals
59 */
60#define AT91SAM9X5_BASE_RTC 0xfffffeb0
61
62/*
63 * Internal Memory.
64 */
65#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
66#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
67
68#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
69#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
70
71#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index cacbaa52418f..2f8ce2d69fdb 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -24,17 +24,6 @@
24/* sama5d4 */ 24/* sama5d4 */
25#define AT91_BASE_DBGU2 0xfc069000 25#define AT91_BASE_DBGU2 0xfc069000
26 26
27#include <mach/at91rm9200.h>
28#include <mach/at91sam9260.h>
29#include <mach/at91sam9261.h>
30#include <mach/at91sam9263.h>
31#include <mach/at91sam9rl.h>
32#include <mach/at91sam9g45.h>
33#include <mach/at91sam9x5.h>
34#include <mach/at91sam9n12.h>
35#include <mach/sama5d3.h>
36#include <mach/sama5d4.h>
37
38/* 27/*
39 * On all at91 except rm9200 and x40 have the System Controller starts 28 * On all at91 except rm9200 and x40 have the System Controller starts
40 * at address 0xffffc000 and has a size of 16KiB. 29 * at address 0xffffc000 and has a size of 16KiB.
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
deleted file mode 100644
index 25613d8c6dcd..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * Chip-specific header file for the SAMA5D3 family
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * Common definitions.
8 * Based on SAMA5D3 datasheet.
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#ifndef SAMA5D3_H
14#define SAMA5D3_H
15
16/*
17 * Peripheral identifiers/interrupts.
18 */
19#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
20#define AT91_ID_SYS 1 /* System Peripherals */
21#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
22#define AT91_ID_PIT 3 /* PIT */
23#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */
24#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */
25#define SAMA5D3_ID_PIOA 6 /* PIOA */
26#define SAMA5D3_ID_PIOB 7 /* PIOB */
27#define SAMA5D3_ID_PIOC 8 /* PIOC */
28#define SAMA5D3_ID_PIOD 9 /* PIOD */
29#define SAMA5D3_ID_PIOE 10 /* PIOE */
30#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */
31#define SAMA5D3_ID_USART0 12 /* USART0 */
32#define SAMA5D3_ID_USART1 13 /* USART1 */
33#define SAMA5D3_ID_USART2 14 /* USART2 */
34#define SAMA5D3_ID_USART3 15 /* USART3 */
35#define SAMA5D3_ID_UART0 16 /* UART 0 */
36#define SAMA5D3_ID_UART1 17 /* UART 1 */
37#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */
38#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */
39#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */
40#define SAMA5D3_ID_HSMCI0 21 /* MCI */
41#define SAMA5D3_ID_HSMCI1 22 /* MCI */
42#define SAMA5D3_ID_HSMCI2 23 /* MCI */
43#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */
44#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */
45#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */
46#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */
47#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */
48#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */
49#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */
50#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */
51#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */
52#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */
53#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */
54#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */
55#define SAMA5D3_ID_LCDC 36 /* LCD Controller */
56#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */
57#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */
58#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */
59#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */
60#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */
61#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */
62#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */
63#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */
64#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
65#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
66
67/*
68 * User Peripheral physical base addresses.
69 */
70#define SAMA5D3_BASE_USART0 0xf001c000
71#define SAMA5D3_BASE_USART1 0xf0020000
72#define SAMA5D3_BASE_USART2 0xf8020000
73#define SAMA5D3_BASE_USART3 0xf8024000
74
75/*
76 * System Peripherals
77 */
78#define SAMA5D3_BASE_RTC 0xfffffeb0
79
80/*
81 * Internal Memory
82 */
83#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
84#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */
85
86#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
deleted file mode 100644
index f256a45d9854..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Chip-specific header file for the SAMA5D4 family
3 *
4 * Copyright (C) 2013 Atmel Corporation,
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Common definitions.
8 * Based on SAMA5D4 datasheet.
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#ifndef SAMA5D4_H
14#define SAMA5D4_H
15
16/*
17 * User Peripheral physical base addresses.
18 */
19#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
20#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
21#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
22#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
23
24/* Some other peripherals */
25#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
26
27/*
28 * Internal Memory.
29 */
30#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
31#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
32
33#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 11:07:03 -0500