diff options
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r-- | arch/arm/mach-at91/at91rm9200_time.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-at91/at91sam9n12.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 6 |
3 files changed, 8 insertions, 11 deletions
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 2acdff4c1dfe..180b3024bec3 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c | |||
@@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |||
174 | static struct clock_event_device clkevt = { | 174 | static struct clock_event_device clkevt = { |
175 | .name = "at91_tick", | 175 | .name = "at91_tick", |
176 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 176 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
177 | .shift = 32, | ||
177 | .rating = 150, | 178 | .rating = 150, |
178 | .set_next_event = clkevt32k_next_event, | 179 | .set_next_event = clkevt32k_next_event, |
179 | .set_mode = clkevt32k_mode, | 180 | .set_mode = clkevt32k_mode, |
@@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void) | |||
264 | at91_st_write(AT91_ST_RTMR, 1); | 265 | at91_st_write(AT91_ST_RTMR, 1); |
265 | 266 | ||
266 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ | 267 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
268 | clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); | ||
269 | clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); | ||
270 | clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; | ||
267 | clkevt.cpumask = cpumask_of(0); | 271 | clkevt.cpumask = cpumask_of(0); |
268 | clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, | 272 | clockevents_register_device(&clkevt); |
269 | 2, AT91_ST_ALMV); | ||
270 | 273 | ||
271 | /* register clocksource */ | 274 | /* register clocksource */ |
272 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); | 275 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 13cdbcd48f51..c7d670d11802 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c | |||
@@ -223,13 +223,7 @@ static void __init at91sam9n12_map_io(void) | |||
223 | at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); | 223 | at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); |
224 | } | 224 | } |
225 | 225 | ||
226 | void __init at91sam9n12_initialize(void) | ||
227 | { | ||
228 | at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); | ||
229 | } | ||
230 | |||
231 | AT91_SOC_START(at91sam9n12) | 226 | AT91_SOC_START(at91sam9n12) |
232 | .map_io = at91sam9n12_map_io, | 227 | .map_io = at91sam9n12_map_io, |
233 | .register_clocks = at91sam9n12_register_clocks, | 228 | .register_clocks = at91sam9n12_register_clocks, |
234 | .init = at91sam9n12_initialize, | ||
235 | AT91_SOC_END | 229 | AT91_SOC_END |
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 31df12029c4e..2bd7f51b0b82 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
@@ -179,9 +179,9 @@ extern void __iomem *at91_pmc_base; | |||
179 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ | 179 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
180 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ | 180 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ |
181 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ | 181 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ |
182 | #define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ | 182 | #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ |
183 | #define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ | 183 | #define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ |
184 | #define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ | 184 | #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ |
185 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | 185 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
186 | 186 | ||
187 | #endif | 187 | #endif |