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-rw-r--r--arch/arm/mach-at91/Kconfig11
-rw-r--r--arch/arm/mach-at91/Makefile3
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c11
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c45
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c45
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c189
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h22
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h130
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h10
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-at91/pm.h49
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S74
18 files changed, 575 insertions, 48 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8f27e2..939bccd70569 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
366 366
367endif 367endif
368 368
369if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
370comment "AT91SAM9260/AT91SAM9G20 boards"
371
372config MACH_SNAPPER_9260
373 bool "Bluewater Systems Snapper 9260/9G20 module"
374 help
375 Select this if you are using the Bluewater Systems Snapper 9260 or
376 Snapper 9G20 modules.
377 <http://www.bluewatersys.com/>
378endif
379
369# ---------------------------------------------------------- 380# ----------------------------------------------------------
370 381
371if ARCH_AT91SAM9G45 382if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e58222..ca2ac003f41f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
68 68
69# AT91SAM9260/AT91SAM9G20 board-specific support
70obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
71
69# AT91SAM9G45 board-specific support 72# AT91SAM9G45 board-specific support
70obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o 73obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
71 74
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 85166b7e69a1..753c0d31a3d3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
20#include <mach/at91_pmc.h> 20#include <mach/at91_pmc.h>
21#include <mach/at91_rstc.h> 21#include <mach/at91_rstc.h>
22#include <mach/at91_shdwc.h> 22#include <mach/at91_shdwc.h>
23#include <mach/cpu.h>
23 24
24#include "generic.h" 25#include "generic.h"
25#include "clock.h" 26#include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
176 .type = CLK_TYPE_PERIPHERAL, 177 .type = CLK_TYPE_PERIPHERAL,
177}; 178};
178 179
180/* Video decoder clock - Only for sam9m10/sam9m11 */
181static struct clk vdec_clk = {
182 .name = "vdec_clk",
183 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
184 .type = CLK_TYPE_PERIPHERAL,
185};
186
179/* One additional fake clock for ohci */ 187/* One additional fake clock for ohci */
180static struct clk ohci_clk = { 188static struct clk ohci_clk = {
181 .name = "ohci_clk", 189 .name = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
239 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) 247 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
240 clk_register(periph_clocks[i]); 248 clk_register(periph_clocks[i]);
241 249
250 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
251 clk_register(&vdec_clk);
252
242 clk_register(&pck0); 253 clk_register(&pck0);
243 clk_register(&pck1); 254 clk_register(&pck1);
244} 255}
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
index a4102d72cc9b..c49f5c003ee1 100644
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
@@ -26,6 +26,9 @@
26#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
27#include <linux/spi/at73c213.h> 27#include <linux/spi/at73c213.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/consumer.h>
29 32
30#include <mach/hardware.h> 33#include <mach/hardware.h>
31#include <asm/setup.h> 34#include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
235 } 238 }
236}; 239};
237 240
241#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
242static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
243 REGULATOR_SUPPLY("AVDD", "0-001b"),
244 REGULATOR_SUPPLY("HPVDD", "0-001b"),
245 REGULATOR_SUPPLY("DBVDD", "0-001b"),
246 REGULATOR_SUPPLY("DCVDD", "0-001b"),
247};
248
249static struct regulator_init_data ek_avdd_reg_init_data = {
250 .constraints = {
251 .name = "3V3",
252 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
253 },
254 .consumer_supplies = ek_audio_consumer_supplies,
255 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
256};
257
258static struct fixed_voltage_config ek_vdd_pdata = {
259 .supply_name = "board-3V3",
260 .microvolts = 3300000,
261 .gpio = -EINVAL,
262 .enabled_at_boot = 0,
263 .init_data = &ek_avdd_reg_init_data,
264};
265static struct platform_device ek_voltage_regulator = {
266 .name = "reg-fixed-voltage",
267 .id = -1,
268 .num_resources = 0,
269 .dev = {
270 .platform_data = &ek_vdd_pdata,
271 },
272};
273static void __init ek_add_regulators(void)
274{
275 platform_device_register(&ek_voltage_regulator);
276}
277#else
278static void __init ek_add_regulators(void) {}
279#endif
280
238static struct i2c_board_info __initdata ek_i2c_devices[] = { 281static struct i2c_board_info __initdata ek_i2c_devices[] = {
239 { 282 {
240 I2C_BOARD_INFO("24c512", 0x50), 283 I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
256 ek_add_device_nand(); 299 ek_add_device_nand();
257 /* Ethernet */ 300 /* Ethernet */
258 at91_add_device_eth(&ek_macb_data); 301 at91_add_device_eth(&ek_macb_data);
302 /* Regulators */
303 ek_add_regulators();
259 /* MMC */ 304 /* MMC */
260#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) 305#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
261 at91_add_device_mci(0, &ek_mmc_data); 306 at91_add_device_mci(0, &ek_mmc_data);
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c11fd47aec5d..6ea9808b8868 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -27,6 +27,9 @@
27#include <linux/gpio_keys.h> 27#include <linux/gpio_keys.h>
28#include <linux/input.h> 28#include <linux/input.h>
29#include <linux/clk.h> 29#include <linux/clk.h>
30#include <linux/regulator/machine.h>
31#include <linux/regulator/fixed.h>
32#include <linux/regulator/consumer.h>
30 33
31#include <mach/hardware.h> 34#include <mach/hardware.h>
32#include <asm/setup.h> 35#include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
269static void __init ek_add_device_buttons(void) {} 272static void __init ek_add_device_buttons(void) {}
270#endif 273#endif
271 274
275#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
276static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
277 REGULATOR_SUPPLY("AVDD", "0-001b"),
278 REGULATOR_SUPPLY("HPVDD", "0-001b"),
279 REGULATOR_SUPPLY("DBVDD", "0-001b"),
280 REGULATOR_SUPPLY("DCVDD", "0-001b"),
281};
282
283static struct regulator_init_data ek_avdd_reg_init_data = {
284 .constraints = {
285 .name = "3V3",
286 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
287 },
288 .consumer_supplies = ek_audio_consumer_supplies,
289 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
290};
291
292static struct fixed_voltage_config ek_vdd_pdata = {
293 .supply_name = "board-3V3",
294 .microvolts = 3300000,
295 .gpio = -EINVAL,
296 .enabled_at_boot = 0,
297 .init_data = &ek_avdd_reg_init_data,
298};
299static struct platform_device ek_voltage_regulator = {
300 .name = "reg-fixed-voltage",
301 .id = -1,
302 .num_resources = 0,
303 .dev = {
304 .platform_data = &ek_vdd_pdata,
305 },
306};
307static void __init ek_add_regulators(void)
308{
309 platform_device_register(&ek_voltage_regulator);
310}
311#else
312static void __init ek_add_regulators(void) {}
313#endif
314
272 315
273static struct i2c_board_info __initdata ek_i2c_devices[] = { 316static struct i2c_board_info __initdata ek_i2c_devices[] = {
274 { 317 {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
294 ek_add_device_nand(); 337 ek_add_device_nand();
295 /* Ethernet */ 338 /* Ethernet */
296 at91_add_device_eth(&ek_macb_data); 339 at91_add_device_eth(&ek_macb_data);
340 /* Regulators */
341 ek_add_regulators();
297 /* MMC */ 342 /* MMC */
298 at91_add_device_mmc(0, &ek_mmc_data); 343 at91_add_device_mmc(0, &ek_mmc_data);
299 /* I2C */ 344 /* I2C */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 000000000000..2c08ae4ad3a1
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
1/*
2 * linux/arch/arm/mach-at91/board-snapper9260.c
3 *
4 * Copyright (C) 2010 Bluewater System Ltd
5 *
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/i2c/pca953x.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33
34#include <mach/hardware.h>
35#include <mach/board.h>
36#include <mach/at91sam9_smc.h>
37
38#include "sam9_smc.h"
39#include "generic.h"
40
41#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
42
43static void __init snapper9260_map_io(void)
44{
45 at91sam9260_initialize(18432000);
46
47 /* Debug on ttyS0 */
48 at91_register_uart(0, 0, 0);
49 at91_set_serial_console(0);
50
51 at91_register_uart(AT91SAM9260_ID_US0, 1,
52 ATMEL_UART_CTS | ATMEL_UART_RTS);
53 at91_register_uart(AT91SAM9260_ID_US1, 2,
54 ATMEL_UART_CTS | ATMEL_UART_RTS);
55 at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
56}
57
58static void __init snapper9260_init_irq(void)
59{
60 at91sam9260_init_interrupts(NULL);
61}
62
63static struct at91_usbh_data __initdata snapper9260_usbh_data = {
64 .ports = 2,
65};
66
67static struct at91_udc_data __initdata snapper9260_udc_data = {
68 .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5),
69 .vbus_active_low = 1,
70 .vbus_polled = 1,
71};
72
73static struct at91_eth_data snapper9260_macb_data = {
74 .is_rmii = 1,
75};
76
77static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
78 {
79 .name = "Preboot",
80 .offset = 0,
81 .size = SZ_128K,
82 },
83 {
84 .name = "Bootloader",
85 .offset = MTDPART_OFS_APPEND,
86 .size = SZ_256K,
87 },
88 {
89 .name = "Environment",
90 .offset = MTDPART_OFS_APPEND,
91 .size = SZ_128K,
92 },
93 {
94 .name = "Kernel",
95 .offset = MTDPART_OFS_APPEND,
96 .size = SZ_4M,
97 },
98 {
99 .name = "Filesystem",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
102 },
103};
104
105static struct mtd_partition * __init
106snapper9260_nand_partition_info(int size, int *num_partitions)
107{
108 *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
109 return snapper9260_nand_partitions;
110}
111
112static struct atmel_nand_data __initdata snapper9260_nand_data = {
113 .ale = 21,
114 .cle = 22,
115 .rdy_pin = AT91_PIN_PC13,
116 .partition_info = snapper9260_nand_partition_info,
117 .bus_width_16 = 0,
118};
119
120static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
121 .ncs_read_setup = 0,
122 .nrd_setup = 0,
123 .ncs_write_setup = 0,
124 .nwe_setup = 0,
125
126 .ncs_read_pulse = 5,
127 .nrd_pulse = 2,
128 .ncs_write_pulse = 5,
129 .nwe_pulse = 2,
130
131 .read_cycle = 7,
132 .write_cycle = 7,
133
134 .mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
135 AT91_SMC_EXNWMODE_DISABLE),
136 .tdf_cycles = 1,
137};
138
139static struct pca953x_platform_data snapper9260_io_expander_data = {
140 .gpio_base = SNAPPER9260_IO_EXP_GPIO(0),
141};
142
143static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
144 {
145 /* IO expander */
146 I2C_BOARD_INFO("max7312", 0x28),
147 .platform_data = &snapper9260_io_expander_data,
148 },
149 {
150 /* Audio codec */
151 I2C_BOARD_INFO("tlv320aic23", 0x1a),
152 },
153 {
154 /* RTC */
155 I2C_BOARD_INFO("isl1208", 0x6f),
156 },
157};
158
159static void __init snapper9260_add_device_nand(void)
160{
161 at91_set_A_periph(AT91_PIN_PC14, 0);
162 sam9_smc_configure(3, &snapper9260_nand_smc_config);
163 at91_add_device_nand(&snapper9260_nand_data);
164}
165
166static void __init snapper9260_board_init(void)
167{
168 at91_add_device_i2c(snapper9260_i2c_devices,
169 ARRAY_SIZE(snapper9260_i2c_devices));
170 at91_add_device_serial();
171 at91_add_device_usbh(&snapper9260_usbh_data);
172 at91_add_device_udc(&snapper9260_udc_data);
173 at91_add_device_eth(&snapper9260_macb_data);
174 at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
175 ATMEL_SSC_TD | ATMEL_SSC_RD));
176 snapper9260_add_device_nand();
177}
178
179MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
180 .phys_io = AT91_BASE_SYS,
181 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
182 .boot_params = AT91_SDRAM_BASE + 0x100,
183 .timer = &at91sam926x_timer,
184 .map_io = snapper9260_map_io,
185 .init_irq = snapper9260_init_irq,
186 .init_machine = snapper9260_board_init,
187MACHINE_END
188
189
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75..9c6af9737485 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
84 */ 84 */
85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) 85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) 87#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffdd..976f4a6c3353 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
15#ifndef AT91CAP9_DDRSDR_H 15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H 16#define AT91CAP9_DDRSDR_H
17 17
18#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ 18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ 19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0 20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1 21#define AT91_DDRSDRC_MODE_NOP 1
@@ -25,10 +25,10 @@
25#define AT91_DDRSDRC_MODE_EXT_LMR 5 25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6 26#define AT91_DDRSDRC_MODE_DEEP 6
27 27
28#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ 28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30 30
31#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ 31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ 32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0) 33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0) 34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
@@ -49,7 +49,7 @@
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ 49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51 51
52#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ 52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
@@ -59,13 +59,13 @@
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ 59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61 61
62#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ 62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ 63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ 64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67 67
68#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ 68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0 70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -80,14 +80,14 @@
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) 80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) 81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82 82
83#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ 83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0 85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2 87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89 89
90#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ 90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
@@ -98,5 +98,11 @@
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ 98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ 99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100 100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
101 107
102#endif 108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb..4e79036d3b80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
84 * System Peripherals (offset from AT91_BASE_SYS) 84 * System Peripherals (offset from AT91_BASE_SYS)
85 */ 85 */
86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 86#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
87#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 87#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 88#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 89#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 90#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484..2b5618518129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
68/* 68/*
69 * System Peripherals (offset from AT91_BASE_SYS) 69 * System Peripherals (offset from AT91_BASE_SYS)
70 */ 70 */
71#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 71#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..d27b15ba8ebf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
1/*
2 * Header file for the Atmel DDR/SDR SDRAM Controller
3 *
4 * Copyright (C) 2010 Atmel Corporation
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef AT91SAM9_DDRSDR_H
13#define AT91SAM9_DDRSDR_H
14
15#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
16#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
17#define AT91_DDRSDRC_MODE_NORMAL 0
18#define AT91_DDRSDRC_MODE_NOP 1
19#define AT91_DDRSDRC_MODE_PRECHARGE 2
20#define AT91_DDRSDRC_MODE_LMR 3
21#define AT91_DDRSDRC_MODE_REFRESH 4
22#define AT91_DDRSDRC_MODE_EXT_LMR 5
23#define AT91_DDRSDRC_MODE_DEEP 6
24
25#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
26#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
27
28#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
29#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
30#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
31#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
32#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
33#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
34#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
35#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
36#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
37#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
38#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
39#define AT91_DDRSDRC_NR_11 (0 << 2)
40#define AT91_DDRSDRC_NR_12 (1 << 2)
41#define AT91_DDRSDRC_NR_13 (2 << 2)
42#define AT91_DDRSDRC_NR_14 (3 << 2)
43#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
44#define AT91_DDRSDRC_CAS_2 (2 << 4)
45#define AT91_DDRSDRC_CAS_3 (3 << 4)
46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
56#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
57#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
58#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
66#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
67#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
81#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
82#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
83#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
84#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
85#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
86#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
87#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
88#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
89#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
90#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
91#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
109
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123
124/* Register access macros */
125#define at91_ramc_read(num, reg) \
126 at91_sys_read(AT91_DDRSDRC##num + reg)
127#define at91_ramc_write(num, reg, value) \
128 at91_sys_write(AT91_DDRSDRC##num + reg, value)
129
130#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7ca..100f5a592926 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
17#define AT91SAM9_SDRAMC_H 17#define AT91SAM9_SDRAMC_H
18 18
19/* SDRAM Controller (SDRAMC) registers */ 19/* SDRAM Controller (SDRAMC) registers */
20#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ 20#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ 21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91_SDRAMC_MODE_NORMAL 0 22#define AT91_SDRAMC_MODE_NORMAL 0
23#define AT91_SDRAMC_MODE_NOP 1 23#define AT91_SDRAMC_MODE_NOP 1
@@ -27,10 +27,10 @@
27#define AT91_SDRAMC_MODE_EXT_LMR 5 27#define AT91_SDRAMC_MODE_EXT_LMR 5
28#define AT91_SDRAMC_MODE_DEEP 6 28#define AT91_SDRAMC_MODE_DEEP 6
29 29
30#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ 30#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
32 32
33#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ 33#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
35#define AT91_SDRAMC_NC_8 (0 << 0) 35#define AT91_SDRAMC_NC_8 (0 << 0)
36#define AT91_SDRAMC_NC_9 (1 << 0) 36#define AT91_SDRAMC_NC_9 (1 << 0)
@@ -57,7 +57,7 @@
57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ 57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ 58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
59 59
60#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ 60#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ 61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62#define AT91_SDRAMC_LPCB_DISABLE 0 62#define AT91_SDRAMC_LPCB_DISABLE 0
63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
@@ -71,16 +71,21 @@
71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) 71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) 72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
73 73
74#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ 74#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
75#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ 75#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
76#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ 76#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
77#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ 77#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ 78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
79 79
80#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ 80#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ 81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
85 90
86#endif 91#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86..87ba8517ad98 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
74 */ 74 */
75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) 75#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 76#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 77#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 78#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 80#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed848c9f8..58528aa9c8a8 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
44 /* USB Device */ 44 /* USB Device */
45struct at91_udc_data { 45struct at91_udc_data {
46 u8 vbus_pin; /* high == host powering us */ 46 u8 vbus_pin; /* high == host powering us */
47 u8 vbus_active_low; /* vbus polarity */
48 u8 vbus_polled; /* Use polling, not interrupt */
47 u8 pullup_pin; /* active == D+ pulled up */ 49 u8 pullup_pin; /* active == D+ pulled up */
48 u8 pullup_active_low; /* true == pullup_pin is active low */ 50 u8 pullup_active_low; /* true == pullup_pin is active low */
49}; 51};
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 833659d1200a..3bef931d0b1c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
52 52
53#define ARCH_EXID_AT91SAM9M11 0x00000001 53#define ARCH_EXID_AT91SAM9M11 0x00000001
54#define ARCH_EXID_AT91SAM9M10 0x00000002 54#define ARCH_EXID_AT91SAM9M10 0x00000002
55#define ARCH_EXID_AT91SAM9G46 0x00000003
55#define ARCH_EXID_AT91SAM9G45 0x00000004 56#define ARCH_EXID_AT91SAM9G45 0x00000004
56 57
57static inline unsigned long at91_exid_identify(void) 58static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
128#ifdef CONFIG_ARCH_AT91SAM9G45 129#ifdef CONFIG_ARCH_AT91SAM9G45
129#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) 130#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
130#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) 131#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
132#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
133 (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
134#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
135 (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
136#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
137 (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
131#else 138#else
132#define cpu_is_at91sam9g45() (0) 139#define cpu_is_at91sam9g45() (0)
133#define cpu_is_at91sam9g45es() (0) 140#define cpu_is_at91sam9g45es() (0)
141#define cpu_is_at91sam9m10() (0)
142#define cpu_is_at91sam9g46() (0)
143#define cpu_is_at91sam9m11() (0)
134#endif 144#endif
135 145
136#ifdef CONFIG_ARCH_AT91CAP9 146#ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e31c9c5..bfdd8ab26dc8 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
19#define PIN_BASE NR_AIC_IRQS 19#define PIN_BASE NR_AIC_IRQS
20 20
21#define MAX_GPIO_BANKS 5 21#define MAX_GPIO_BANKS 5
22#define NR_BUILTIN_GPIO (PIN_BASE + (MAX_GPIO_BANKS * 32))
22 23
23/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ 24/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24 25
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a..8c87d0c1b8f8 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
30{ 30{
31 u32 saved_lpr, lpr; 31 u32 saved_lpr, lpr;
32 32
33 saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR); 33 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
34 34
35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 35 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
36 at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 36 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
37 return saved_lpr; 37 return saved_lpr;
38} 38}
39 39
40#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr) 40#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
41
42#elif defined(CONFIG_ARCH_AT91SAM9G45)
43#include <mach/at91sam9_ddrsdr.h>
44
45/* We manage both DDRAM/SDRAM controllers, we need more than one value to
46 * remember.
47 */
48static u32 saved_lpr1;
49
50static inline u32 sdram_selfrefresh_enable(void)
51{
52 /* Those tow values allow us to delay self-refresh activation
53 * to the maximum. */
54 u32 lpr0, lpr1;
55 u32 saved_lpr0;
56
57 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
58 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
59 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
60
61 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
62 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
63 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
64
65 /* self-refresh mode now */
66 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
67 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
68
69 return saved_lpr0;
70}
71
72#define sdram_selfrefresh_disable(saved_lpr0) \
73 do { \
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
75 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
76 } while (0)
41 77
42#else 78#else
43#include <mach/at91sam9_sdramc.h> 79#include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
47 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 83 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
48 * handle those cases both here and in the Suspend-To-RAM support. 84 * handle those cases both here and in the Suspend-To-RAM support.
49 */ 85 */
50#define AT91_SDRAMC AT91_SDRAMC0
51#warning Assuming EB1 SDRAM controller is *NOT* used 86#warning Assuming EB1 SDRAM controller is *NOT* used
52#endif 87#endif
53 88
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
55{ 90{
56 u32 saved_lpr, lpr; 91 u32 saved_lpr, lpr;
57 92
58 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR); 93 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
59 94
60 lpr = saved_lpr & ~AT91_SDRAMC_LPCB; 95 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
61 at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH); 96 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
62 return saved_lpr; 97 return saved_lpr;
63} 98}
64 99
65#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) 100#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
66 101
67#endif 102#endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71..b6b00a1f6125 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/at91_pmc.h> 17#include <mach/at91_pmc.h>
18 18
19#ifdef CONFIG_ARCH_AT91RM9200 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9)
22#include <mach/at91cap9_ddrsdr.h> 22#include <mach/at91cap9_ddrsdr.h>
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h>
23#else 25#else
24#include <mach/at91sam9_sdramc.h> 26#include <mach/at91sam9_sdramc.h>
25#endif 27#endif
@@ -30,7 +32,6 @@
30 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; 32 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
31 * handle those cases both here and in the Suspend-To-RAM support. 33 * handle those cases both here and in the Suspend-To-RAM support.
32 */ 34 */
33#define AT91_SDRAMC AT91_SDRAMC0
34#warning Assuming EB1 SDRAM controller is *NOT* used 35#warning Assuming EB1 SDRAM controller is *NOT* used
35#endif 36#endif
36 37
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
113 /* 114 /*
114 * Register usage: 115 * Register usage:
115 * R1 = Base address of AT91_PMC 116 * R1 = Base address of AT91_PMC
116 * R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200) 117 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
117 * R3 = temporary register 118 * R3 = temporary register
118 * R4 = temporary register 119 * R4 = temporary register
120 * R5 = Base address of second RAM Controller or 0 if not present
119 */ 121 */
120 ldr r1, .at91_va_base_pmc 122 ldr r1, .at91_va_base_pmc
121 ldr r2, .at91_va_base_sdramc 123 ldr r2, .at91_va_base_sdramc
124 ldr r5, .at91_va_base_ramc1
122 125
123 /* Drain write buffer */ 126 /* Drain write buffer */
124 mcr p15, 0, r0, c7, c10, 4 127 mcr p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
127 /* Put SDRAM in self-refresh mode */ 130 /* Put SDRAM in self-refresh mode */
128 mov r3, #1 131 mov r3, #1
129 str r3, [r2, #AT91_SDRAMC_SRR] 132 str r3, [r2, #AT91_SDRAMC_SRR]
130#elif defined(CONFIG_ARCH_AT91CAP9) 133#elif defined(CONFIG_ARCH_AT91CAP9) \
131 /* Enable SDRAM self-refresh mode */ 134 || defined(CONFIG_ARCH_AT91SAM9G45)
132 ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
133 str r3, .saved_sam9_lpr
134 135
135 mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 136 /* prepare for DDRAM self-refresh mode */
136 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 137 ldr r3, [r2, #AT91_DDRSDRC_LPR]
138 str r3, .saved_sam9_lpr
139 bic r3, #AT91_DDRSDRC_LPCB
140 orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
141
142 /* figure out if we use the second ram controller */
143 cmp r5, #0
144 ldrne r4, [r5, #AT91_DDRSDRC_LPR]
145 strne r4, .saved_sam9_lpr1
146 bicne r4, #AT91_DDRSDRC_LPCB
147 orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
148
149 /* Enable DDRAM self-refresh mode */
150 str r3, [r2, #AT91_DDRSDRC_LPR]
151 strne r4, [r5, #AT91_DDRSDRC_LPR]
137#else 152#else
138 /* Enable SDRAM self-refresh mode */ 153 /* Enable SDRAM self-refresh mode */
139 ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 154 ldr r3, [r2, #AT91_SDRAMC_LPR]
140 str r3, .saved_sam9_lpr 155 str r3, .saved_sam9_lpr
141 156
142 mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 157 bic r3, #AT91_SDRAMC_LPCB
143 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 158 orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
159 str r3, [r2, #AT91_SDRAMC_LPR]
144#endif 160#endif
145 161
146 /* Save Master clock setting */ 162 /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
247 263
248#ifdef CONFIG_ARCH_AT91RM9200 264#ifdef CONFIG_ARCH_AT91RM9200
249 /* Do nothing - self-refresh is automatically disabled. */ 265 /* Do nothing - self-refresh is automatically disabled. */
250#elif defined(CONFIG_ARCH_AT91CAP9) 266#elif defined(CONFIG_ARCH_AT91CAP9) \
251 /* Restore LPR on AT91CAP9 */ 267 || defined(CONFIG_ARCH_AT91SAM9G45)
268 /* Restore LPR on AT91 with DDRAM */
252 ldr r3, .saved_sam9_lpr 269 ldr r3, .saved_sam9_lpr
253 str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC] 270 str r3, [r2, #AT91_DDRSDRC_LPR]
271
272 /* if we use the second ram controller */
273 cmp r5, #0
274 ldrne r4, .saved_sam9_lpr1
275 strne r4, [r5, #AT91_DDRSDRC_LPR]
276
254#else 277#else
255 /* Restore LPR on AT91SAM9 */ 278 /* Restore LPR on AT91 with SDRAM */
256 ldr r3, .saved_sam9_lpr 279 ldr r3, .saved_sam9_lpr
257 str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC] 280 str r3, [r2, #AT91_SDRAMC_LPR]
258#endif 281#endif
259 282
260 /* Restore registers, and return */ 283 /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
273.saved_sam9_lpr: 296.saved_sam9_lpr:
274 .word 0 297 .word 0
275 298
299.saved_sam9_lpr1:
300 .word 0
301
276.at91_va_base_pmc: 302.at91_va_base_pmc:
277 .word AT91_VA_BASE_SYS + AT91_PMC 303 .word AT91_VA_BASE_SYS + AT91_PMC
278 304
279#ifdef CONFIG_ARCH_AT91RM9200 305#ifdef CONFIG_ARCH_AT91RM9200
280.at91_va_base_sdramc: 306.at91_va_base_sdramc:
281 .word AT91_VA_BASE_SYS 307 .word AT91_VA_BASE_SYS
282#elif defined(CONFIG_ARCH_AT91CAP9) 308#elif defined(CONFIG_ARCH_AT91CAP9) \
309 || defined(CONFIG_ARCH_AT91SAM9G45)
283.at91_va_base_sdramc: 310.at91_va_base_sdramc:
284 .word AT91_VA_BASE_SYS + AT91_DDRSDRC 311 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
285#else 312#else
286.at91_va_base_sdramc: 313.at91_va_base_sdramc:
287 .word AT91_VA_BASE_SYS + AT91_SDRAMC 314 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
315#endif
316
317.at91_va_base_ramc1:
318#if defined(CONFIG_ARCH_AT91SAM9G45)
319 .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
320#else
321 .word 0
288#endif 322#endif
289 323
290ENTRY(at91_slow_clock_sz) 324ENTRY(at91_slow_clock_sz)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 18:57:54 -0500